the c5x devices offer these advantages

7/29/2019 The C5x Devices Offer These Advantages

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Architectural Overview of

TMS320C5x


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DSPs: Texas Instruments TMS320

Series

C1X, C2X

Fixed-point devices with 16-bit data bus width

Used in toys, hard disk drives, modems and active car

suspensions C3X

Floating-point devices with 32-bit data bus width, which

provides much wider dynamic range as compared to fixed-

point devices Because of higher accuracy, used in hi-fi systems, voice

mail systems and 3D graphic processing


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Series (cont.)

C4X

32-bit floating-point device designed for parallel processing

Optimized on-chip communication channel enables severaldevices to be put together to form a parallel cluster

Used in virtual reality, recognition and parallel processingsystems

C5X

Low power fixed-point DSPs

Used for personal and portable electronics such as cell phones,digital music players, and digital cameras


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Series (cont.)

C6X

High performance DSPs, with speeds up to 1 GHz

Both fixed and floating-point devices

Used in wired and wireless broadband networks, imagingapplications and professional audio

C8X

Multimedia processors, with parallel processing on a single chipwith advanced DSPs and a controlling RISC processor

Used in high performance telephony, 3D computer graphics,virtual reality and a number of multimedia applications


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Typical Applications for the TMS320 Family


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Typical Applications for the TMS320 Family


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The C5x devices offer these advantages:

Enhanced TMS320 architectural design for increased performance and

versatility

Modular architectural design for fast development of spin-off devices

Advanced integrated-circuit processing technology for increasedperformance and low power consumption

Source code compatibility with C1x, C2x, and C2xx DSPs for fast andeasy performance upgrades

Enhanced instruction set for faster algorithms and for optimized high-level language operation

Reduced power consumption and increased radiation hardness because

of new static design techniques


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C5x Functional Block Diagram


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Bus StructureSeparate program and data buses allow simultaneous access to program

instructions and data, providing a high degree of parallelism.For example: while data is multiplied, a previous product can be loaded into,

added to, or subtracted from the accumulator and, at the same time, a new

address can be generated. Such parallelism supports a powerful set of

arithmetic, logic, and bit-manipulation operations that can all be performed in

a single machine cycle.In addition, the C5x includes the control mechanisms to manage interrupts,

repeated operations, and function calling.

The C5x architecture is built around four major buses:


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The PAB provides addresses to program memory space

for both reads and writes.

The PB carries the instruction code and immediateoperands from program memory space to the CPU.

The DB interconnects various elements of the CPU todata memory space.

The program and data buses can work together totransfer data from on-chip data memory and internal orexternal program memory to the multiplier for single-cycle multiply/accumulate operations.


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Central Processing Unit (CPU)

The C5x CPU consists of these elements:

The C5x CPU maintains source-code compatibility with the C1x and C2xgenerations while achieving high performance and greater versatility.Improvements include a 32-bit accumulator buffer, additional scalingcapabilities, and a host of new instructions.

The instruction set exploits the additional hardware features and is flexible ina wide range of applications.

Data management has been improved through the use of new block moveinstructions and memory-mapped register instructions.


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Central Arithmetic Logic Unit (CALU)

The CPU uses the CALU to perform 2s-complement arithmetic.

The CALU consists of these elements:


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Parallel Logic Unit (PLU)

The CPU includes an independent PLU, which operatesseparately from, but in parallel with, the ALU.

The PLU performs Boolean operations or the bitmanipulations required of high-speed controllers.

The PLU can set, clear, test, or toggle bits in a statusregister, control register, or any data memory location.

The PLU provides a direct logic operation path to data

memory values without affecting the contents of theACC or PREG.

Results of a PLU function are written back to theoriginal data memory location.


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Auxiliary Register Arithmetic Unit (ARAU)

The auxiliary register file contains eight memory-mapped auxiliaryregisters (AR0AR7), which can be used for indirect addressing ofthe data memory or for temporary data storage. Indirect auxiliaryregister addressing (see Figure 1) allows placement of the datamemory address of an instruction operand into one of the AR. The

ARs are pointed to by a 3-bit auxiliary register pointer (ARP) that isloaded with a value from 07, designating AR0AR7, respectively.The ARs and the ARP can be loaded from data memory, the ACC orthe PREG or by an immediate operand defined in the instruction.

The auxiliary register file (AR0AR7) is connected to the auxiliaryregister arithmetic unit (ARAU), shown in Figure 2. The ARAU can

auto index the current AR while the data memory location is beingaddressed; it indexes Either by 1 or by the contents of the indexregister (INDX). As a result, the CALU is not needed for addressmanipulation when tables of information are accessed; it is free forother operations in parallel.


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Index Register (INDX)

The 16-bit INDX is used by the ARAU as a step value (addition or subtraction

by more than 1) to modify the address in the ARs during indirect

addressing. For example: when the ARAU steps across a row of a matrix,the indirect address is incremented by 1. However, when the ARAU steps

down a column ,the address is incremented by the dimension of the

matrix.

The ARAU can Add or subtract the value stored in the INDX from the current

AR as part of the indirect address operation.

INDX can also map the dimension of the address block used for bit-reversal

addressing.

Auxiliary Register Compare Register (ARCR)

The 16-bit ARCR is used for address boundary comparison. The CMPR

instruction compares the ARCR to the selected AR and places the result of the

compare in the TC(test/control flag bit) bit of ST1(status register 1).Block Move Address Register (BMAR)

The 16-bit BMAR holds an address value to be used with block moves and

multiply/accumulate operations. This register provides the 16-bit address for

an indirect-addressed second operand.


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Block Repeat Registers (RPTC, BRCR, PASR, PAER)

The 16-bit repeat counter register (RPTC) holds the repeat count in a repeat

single-instruction operation and is loaded by the RPT(Repeat next instructionspecified by data memory value) and RPTZ (Clear ACC and PREG) instructions.

The 16-bit block repeat counter register (BRCR) holds the count value for the

block repeat feature. This value is loaded before a block repeat operation is

initiated. The value can be changed while a block repeat is in progress;

however, take care to avoid infinite loops.

The block repeat program address Start register (PASR) indicates the 16-bit address

where the repeated block of Code starts.

The block repeat program address end register (PAER) indicates The 16-bit address

where the repeated block of code ends. The PASR and PAER are loaded by the RPTB

instruction.

Product Register (PREG)

The 32-bit PREG holds the result of a multiply operation. The high and low words ofPREG can be accessed individually.


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Memory-Mapped Registers

The C5x has 96 registers mapped into page 0 of thedata memory space.

All C5x DSPs have 28 CPU registers and 16 input/output(I/O) port registers but have different numbers of

peripheral and reserved registers .

Since the memory-mapped registers are a component ofthe data memory space, they can be written to and readfrom in the same way as any other data memorylocation.

The memory-mapped registers are used for indirect dataaddress pointers, temporary storage,CPU status andcontrol,or integer arithmetic processing through theARAU.


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Program ControllerThe program controller contains logic circuitry that

1. decodes the operational instructions

2. manages the CPU pipeline3. stores the status of CPU operations

4. decodes the conditional operations.

Parallelism of architecture lets theC5x perform three concurrent memoryoperations in any given machine cycle:

fetch an instruction,

read an operandwrite an operand.

The program controller consists of these elements:


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Program Counter (PC)

The C5x has a 16-bit program counter (PC) which contains the address of internal orexternal program memory used to fetch instructions.

The PC addresses program memory, either on-chip or off-chip, via the program address bus(PAB).

Through the PAB, an instruction is loaded into the instruction register (IREG). Then the PC isready to start the next instruction fetch cycle.

Hardware Stack

The stack which is 16 bits wide and 8 levels deep, is accessible via the PUSH

and POP instructions.

Whenever the contents of the PC are pushed onto the top of the stack (TOS),

the previous contents of each level are pushed down, and the bottom (eighth)location of the stack is lost.

Therefore, data is lost if more than eight successive pushes occur before a pop. The reverse

happens on pop operations.

The software can use the stack to save and restore context or for other purposes

through the following software instructions:

POP, which pops a value from the stack to the accumulator low byte

POPD, which pops a value from the stack to a data memory address

PSHD, which pushes a data-memory value into the stack

PUSH, which pushes the contents of the accumulator low byte into the stack


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Status and Control Registers

The C5x has four status and control registers:

1) Circular buffer control register (CBCR) andprocessor mode status register (PMST) containstatus and control information. Since theseregisters are memory-mapped, they can be

stored into and loaded from data memory;therefore, the status of the CPU can be saved andrestored for subroutines and interrupt serviceroutines (ISRs).

2) Status registers ST0 and ST1 contain the status ofvarious conditions and modes compatible withthe C2x.


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On-Chip Memory

The C5x architecture contains a considerable amount of onchip memory to aid in system performance and integration:

Program read-only memory (ROM)

Data/program dual-access RAM (DARAM) Data/program single-access RAM (SARAM)

The C5x has a total address range of 224K words 16 bits.The memory space is divided into four individually

selectable memory segments: 64K-word program memoryspace, 64K-word local data memory space, 64K-wordinput/output ports, and 32K-word global data memoryspace.


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Program ROM

All C5x DSPs carry a 16-bit on-chip maskable

programmable ROM.The C50 and C57S DSPs have boot loader code

resident in the on-chip ROM, all other C5x DSPs offer theboot loader code as an option.

This memory is used for booting program code fromslower external ROM or EPROM to fast on-chip or externalRAM. Once the custom program has been booted into RAM,the boot ROM space can be removed from program memoryspace by setting the MP/MC bit in the processor mode statusregister (PMST).

The on-chip ROM is selected at reset by driving theMP/MC pin low. If the on-chip ROM is not selected, the C5xdevices start execution from off-chip memory.


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Data/Program Dual-Access RAM

All C5x DSPs carry a 1056-word 16-bit on-chip dual-access RAM (DARAM). The

DARAM is divided into three individually selectable memory blocks: 512-word data

or program DARAM block B0, 512-word data DARAM block B1, and 32-word data

DARAM block B2. The DARAM is primarily intended to store data values but, when

needed, can be used to store programs as well. DARAM blocks B1 and B2 are always

configured as data memory; however, DARAM block B0 can be configured by

software as data or program memory.

The DARAM can be configured in one of two ways:All 1056 words 16 bits configured as data memory

544 words 16 bits configured as data memory and 512 words 16 bits

configured as program memory.

DARAM improves the operational speed of the C5x CPU. The CPU operates with a 4-

deep pipeline. In this pipeline, the CPU reads data on the third stage and writes dataon the fourth stage. Hence, for a given instruction sequence, the second instruction

could be reading data at the same time the first instruction is writing data. The dual

data buses (DB and DAB) allow the CPU to read from and write to DARAM in the

same machine cycle.


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Data/Program Single-Access RAMAll C5x DSPs except the C52 carry a 16-bit on-chip single-access RAM(SARAM) of various sizes

.Code can be booted from an offchip ROM and then executed at full speed, once it is loaded into

the on-chip SARAM.The SARAM can be configured by software in one of three ways:

All SARAM configured as data memory

All SARAM configured as program memory

SARAM configured as both data memory and program memory

The SARAM is divided into 1K- and/or 2K-word blocks contiguous in address memory space. All

C5x CPUs support parallel accesses to these SARAM blocks. However, one SARAM block can

be accessed only once per machine cycle. In other words, the CPU can read from or write to one

SARAM block while accessing another SARAM block. When the CPU requests multiple

accesses, the SARAM schedules the accesses by providing a not-ready condition to the CPU and

executing the multiple accesses one cycle at a time.

SARAM supports more flexible address mapping than DARAM because SARAM can be mapped to

both program and data memory space simultaneously. However, because of simultaneous

program and data mapping, an instruction fetch and data fetch that could be performed in one

machine cycle with DARAM may take two machine cycles with SARAM.


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On-Chip Memory Protection

The C5x DSPs have a maskable option that protects the

contents of on-chip memories. When the related bit is

set, no externally originating instruction can access

the on-chip memory spaces.


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On-Chip Peripherals

All C5x DSPs have the same CPU structure; however, they have

different onchip peripherals connected to their CPUs. The C5x

DSP on-chip peripherals available are:


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Clock Generator

The clock generator consists of an internal oscillator and a phase-locked loop

(PLL) circuit. The clock generator can be driven internally by a crystal

resonator circuit or driven externally by a clock source. The PLL circuit can

generate an internal CPU clock by multiplying the clock source by a

specific factor, so you can use a clock source with a lower frequency than

that of the CPU.

Hardware Timer

A 16-bit hardware timer with a 4-bit prescaler is available. This programmable

timer clocks at a rate that is between 1/2 and 1/32 of the machine cycle

rate (CLKOUT1), depending upon the timers divide-down ratio. The timer

can be stopped, restarted, reset, or disabled by specific status bits.

Software-Programmable Wait-State Generators

Software-programmable wait-state logic is incorporated in C5x DSPs allowingwait-state generation without any external hardware for interfacing with

slower off-chip memory and I/O devices. This feature consists of multiple

waitstate generating circuits. Each circuit is user-programmable to operate

in different wait states for off-chip memory accesses.


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Parallel I/O Ports

A total of 64K I/O ports are available, sixteen of these ports are memory-mapped indata memory space. Each of the I/O ports can be addressed by the IN or the OUTinstruction. The memory mapped I/O ports can be accessed with any instruction thatreads from or writes to data memory. The IS signal indicates a read or writeoperation through an I/O port. The C5x can easily interface with external I/O devicesthrough the I/O ports while requiring minimal off-chip address decoding circuits.

Host Port Interface (HPI)

The HPI available on the C57S and LC57 is an 8-bit parallel I/O port that provides aninterface to a host processor. Information is exchanged between the DSP and the hostprocessor through on-chip memory that is accessible to both the host processor andthe C57.


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Serial PortThree different kinds of serial ports are available:

A general-purpose serial port,

A time-division multiplexed (TDM) serial port

A buffered serial port (BSP)

Each C5x contains at least one general-purpose, high-speed synchronous,full- duplexed serial port interface that provides direct communicationwith serial devices such as codec's , serial analog-to-digital (A/D)converters, and other serial systems.

The serial port is capable of operating at up to one fourth the machine cyclerate (CLKOUT1).

The serial port transmitter and receiver are double-buffered and individuallycontrolled by maskable external interrupt signals. Data is framed either asbytes or as words.

Buffered Serial Port (BSP)The BSP available on the C56 and C57 devices is a full-duplexed, doublebuffered serial port and an auto buffering unit (ABU). The BSP providesflexibility on the data stream length. The ABU supports high-speed datatransfer and reduces interrupt latencies.


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TDM Serial Port

The TDM serial port available on the C50, C51, and C53 devices is a full

duplexed serial port that can be configured by software either for

synchronous operations or for time-division multiplexed operations. TheTDM serial port is commonly used in multiprocessor applications

User-Maskable Interrupts

Four external interrupt lines (INT1INT4) and five internal interrupts, a

timer interrupt and four serial port interrupts, are user maskable. When an

interrupt service routine (ISR) is executed, the contents of the program

counter are saved on an 8-level hardware stack, and the contents of eleven

specific CPU registers are automatically saved (shadowed) on a 1-level-

deep stack. When a return from interrupt instruction is executed, the CPU

registers contents are restored.

the c5x devices offer these advantages

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