the chip, heart of an rfid tag

March 6th 2009 SEREC - ETHZ - RFID - Visions and reality 1

A COMPANY OF THE

The chip, heart of an RFID Tag

Thierry RozRFID Business Unit Manager


EM's Mission

Design and production of integrated circuits for the watchmaking industry since 1975

Today more than 90% of its business is outside of the watch industry

Watch-making Industry

MicroelectronicsIndustry


EM in the World

Marin - Switzerland

Headquarter – Design Center - Fab

Colorado Springs - USA

Design Center

Prague – Czech Republic

Design Center

Bangkok - Thailand

Packages – Electronic Modules

Know How centered in Marin –Switzerland

Multiple design sites to collectworldwide experience at EM'sand its customer's benefits


Introduction

Will economy of scale really help massive RFID deployement ?

Massive RFID deployement : Nickel Tag or Penny Tag ?

One significant part of an RFID tag is the chip. What influences the chip cost ?


EM RFID Track Record

Over 2 billions RFID circuits in the field

Sold more than 410 millions RFID chips in 2008

Sells RFID circuits for more than 20 years

Among the top 3 RFID chip manufacturers in world


Market position according ABI research in 2007

With courtesy of ABI research


EM's RFID Background

20% Standard ICs80% Custom Specific

Product offer in125 KHz13.56 MHz, UHF2.45 GHz

Low cost silicon supplier with experience in mass production

Cooperation with various tag and reader manufacturers

~20%

~80%


Item-Level Tagging in Apparel Industry

MARKS & SPENCER (UK)

To offer the highest possible level of product availabitity to customers

Through an accurate and efficient supply chain

Right Goods

Right Place

Right Time

120 Stores


RFID Label Cost Breakdown

30-40%

30%

30-40%

Total Costs

Silicon

Inlay

Label

Raw materialSilicon, chemicals

Manpower

Production equipment (line)Amortization costs

Tooling (mask set)Chip design + test facility

Raw materialSubstrate, conductor

Manpower

Automated chip/inlay assemblyequipment

Amortization costsAntenna design + RF test

facility

Raw materialPaper, adhesives, ink

Logistics, personalization, manpower

Automated lamination equipment

Amortization costs

Variable CostsFixed Costs


Silicon Cost Driving factors

Wafer Cost Function CostFeature sizeStandard Cost (ISO, EPC, …)Patent (IP) CostsEconomy of scale


Wafer Costs

Raw Material CostManufacturing CostsProgramming, TestingConditionning

BacklappingSawingBumpingDelivery Format (wafer, straps, …)


Function Cost

Function (anticollision, command interpreter, crypto)Memory type (Read Only, WORM, R-W, Flash)Mixed signal (sensors, A/D, …)RF technology (High frequency)Higher complexity => lower features size


Average Wafer Cost vs. Feature Size

Source Selantec 2006

0.00.51.01.52.02.53.03.54.04.55.0

90nm 0.13um 0.18um 0.25um 0.35um 0.50um 1.00um

Feature size

Cos

t Fac

tor


Feature size : scribe line cost

91.5% usable surface75.6% usable surface


Reducing feature size ok, but…

Reduce die size to carry more chips per wafer, there are limits:

Currently, few inlay manufacturers are able to efficiently handle chips smaller than 500 μm in size.Some functions do not scale efficiently with processUsable vs. unusable wafer surface ratio decreasing with chip size

ConclusionThere is a critical minimum surface under which reducing die size will increase handling and material costs again


Impact of Standard

Benefits:Enables mass adoption for cross user deployment in open systems / environments

Drawbacks:All user requirements considered with the same importanceCompromises often lead to complex solutionsSlow developmentEvolving Standards (ISO14443, ISO18000)


Standard Costs

EM4122EM4122 EM4223 - ISO18000-6AEM4223 - ISO18000-6A

EM4223 twice the surface of EM4122 (same techno)EPC C1G2 complexity = 12'000 gates

EM4223 twice the surface of EM4122 (same techno)EPC C1G2 complexity = 12'000 gates

600 gates600 gates

3500 gates3500 gates


Estimated Evolution of EPC C1G2 Die Size

0.5μm

EM4123

Chip SizeToday

Chip Size2007

Chip Size2010

0.13μm0.18μm

Class1G2

EM TTO


Patent Costs

15000 patents are related to RFID: Patents apply toProtocol, Chip implementation, Chip attachment,Label conversion,Reader design,Usage of the RF spectrum

Existing patent claimsTypically 5% of chip + 5% of tag price + 7.5% of reader price

Latency on patent claimsStandards


Economy of scale : 1

Billions (109) of additional tags per year, distributed over major foundries, will lead to thousands (103) of additional wafers per months and per foundry

The economy of scale brought by leveraging on quantities from 100 to 5000 wafers per month is in the range of few percents (%) not factors

source Selantec 2006


Impact of 1 additional billion chips on production

One 8" wafer holds 120’000 EPC chips

8" wafer equivalent capacity:

TSMC 2006 : 8 MWorld MOS 2006 : 100 M

1 billion chips =>0.1% TSMC capacity0.008% World MOS capacity

700010 000 000 000

7001 000 000 000

70100 000 000

710 000 000

Monthly WafersAnnual Chip Qty


Conclusions

Chip cost is sensitive to feature sizeChip cost is affected by additional process features (Memory, Analog,RF...)Chip cost is affected by delivery format (tested, sawn, bump, shipping,…)RFID chip quantities even in billions do not weigh much on world production capacity

Golden rule : keep it as simple as possible, don’t pay for features you don’t use !


Thank you for your attention

Questions ?

Thierry Roz ( [email protected] )

the chip, heart of an rfid tag

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