The Design Process, RTL, Netlists, and Verilog

Erik Seligman

CS 510, Lecture 3, January 2009

Goals of This Lecture

Review basics of VLSI design process Review important RTL design concepts Review (or learn) Verilog language

All these should be review• Verilog may be new

– if you’ve used different RTL languages

• But all concepts should be familiar

RTL and Netlists in the Design Process

Review: Design Process

Architecture

RTL

Netlists

Layout/Backend

FV In The Design Process

Architecture

RTL

Netlists

Layout/Backend

FPV

FEV

CDC, TOV

Who Does Formal Verification? General DEs

• FEV for RTL-netlist closure– Often run high-level flows, little understanding

• Other areas optional– FPV, CDC, TOV mostly left to specialists

FV Specialists• Run most forms of FV

• But tools / methods have improved greatly– My contention: many DEs could gain from use!

Focus of This Class

RTL (Register Transfer Level) is most mature area for FV• FEV: Formal Equivalence

– RTL-netlist, or RTL-RTL

• FPV: Formal Property Verification

• CDC, TOV most useful at RTL level Netlists (schematics)

• FEV Critical: must be equivalent to RTL– Also netlist-netlist FEV for late changes useful

• CDC, TOV also sometimes done on netlists

RTL Design In Verilog

What Is Verilog?

Hardware definition language Similar abstraction level to VHDL Multiple iterations

• Verilog 95: First standard version

• Verilog 2001: More features, very popular in modern designs

• SystemVerilog: Leading edge, will be unified with Verilog standard in 2009

– IEEE p1800 committee

Verilog Basics

Case-sensitive Event-based semantics

• Many events may occur at each time step

Contains static and procedural code• Procedural = software-like: execute in order within

procedure

• No order among procedures or static code

Nonblocking and blocking assignments• Blocking = immediate

• Nonblocking = hold until end of time step

Common Operators

Arithmetic: *,/,+,- Equality (comparison): ==, != Bitwise AND,OR,NOT: &, |, ~

• Don’t confuse with logical &&, ||

• Unary &,| can be applied to reduce a vector: &foo[2:0] = foo[2] & foo[1] & foo[0]

Concatenation: {}• foo[2:0] = {bar[1],bar[0],1’b0};

Data types

Most commonly used: wire, reg• wire = combinational value

• reg = more general, combo or state– But NOT automatically a latch or flop: depends

on usage

2-D Vector declaration a little odd• 1-D, packed: wire [3:0] foo;

• 1-D, unpacked: wire foo[3:0]; // DON’T USE

• 2-D: wire [3:0] foo [1:0];

Compiler Macros Preprocessed, similar to #define in C++ Exact text substituted at preprocess time

• Thus hidden in many tools• Recommend parameter instead of `define for consts• Include ‘;’ only if defining full statement!

`define MYCONST 1`define THIS_IS_BAD 1;parameter MYCONST2 = 1;`define MYAND(x,y) (x & y)

…assign foo = `MYCONST & sig; // OKassign bar = `THIS_IS_BAD & sig; // error!assign baz = MYCONST2 & sig; // OKassign xyz = `MYAND(sig1,sig2) & sig; // OK

Synthesizable Verilog

“Synthesizable” subset of verilog• Accepted by synthesis & FV tools

• Some fancy features disallowed– Example: time delays (#n)

This class will focus on synthesizable verilog• Required by most FV tools

Basic Verilog example

module mymod (i1, clk, o1);input wire i1;input wire clk;output reg o1;always @(posedge clk) begin o1 <= i1; endendmodule;

Basic Verilog example

module mymod (i1, clk, o1);input wire i1;input wire clk;output reg o1;always @(posedge clk) begin o1 <= i1; endendmodule;

Basic Verilog example

module mymod (i1, clk, o1);input wire i1;input wire clk;output reg o1;always @(posedge clk) begin o1 <= i1; endendmodule;

Basic Verilog example

module mymod (i1, clk, o1);input wire i1;input wire clk;output reg o1;always @(posedge clk) begin o1 <= i1; endendmodule;

Basic Verilog example

module mymod (i1, clk, o1);input wire i1;input wire clk;output reg o1;always @(posedge clk) begin o1 <= i1; endendmodule;

More RTL Examples

Latch example

module mymod (i1, clk, o1);input wire i1;input wire clk;output reg o1;always @(clk) begin if (clk) o1 <= i1; endendmodule;

Mux examplemodule mymod (i1, i2, sel, clk, o1);input wire i1, i2, sel;input wire clk;output reg o1;wire mux_out;

assign mux_out = (sel) ? i1 : i2;

always @(posedge clk) begin o1 <= mux_out; endendmodule;

State Machine example…parameter STATE0=0, STATE1=1, STATE2=2, STATE_ERR=3;reg [1:0] sm;reg [1:0] sm_next;

always @(sm or i1) begincase (sm) STATE0: sm_next = STATE1;

STATE1: sm_next = i1 ? STATE1: STATE2; STATE2: sm_next = STATE0;

default: sm_next = STATE_ERR; endcaseendalways @(posedge clk) begin sm <= sm_next; end…

Looping and Conditionals

…wire [3:0] enable;wire [3:0] newval;reg [3:0] foo;

always @(posedge clk) beginfor (int i=0; i<3; i++) begin

if (enable[i]) beginfoo[i] <= newval[i];

end endend…

Race Condition Example…reg foo;reg foo_next;

always @(i1) beginfoo_next = i1;

endalways @(i1) begin

foo_next = ~i1;endalways @(posedge clk) begin foo <= foo_next; end…

Not a Race Condition

…reg foo;reg foo_next;

always @(i1) beginfoo_next = i1;foo_next = ~i1;

endalways @(posedge clk) begin foo <= foo_next; end…

Submodule instantiationmodule submod (i1, i2, sel, clk, o1); input wire i1, i2, sel; input wire clk; output reg o1; …endmodule;

module topmod(…) … submod subinst1 (.i1(foo), .i2(bar), .sel(sel), .clk(topclock), .o1(out)); …

endmodule

Generate Blocksmodule submod (i1, i2, sel, clk, o1); input wire i1, i2, sel; input wire clk; output reg o1; …endmodule;

module topmod(…) …genvar i;generate for (i=0; i<4; i++) begin submod subinst1 (.i1(foo[i]), .i2(bar), .sel(sel), .clk(topclock), .o1(out[i]));

end endgenerate …endmodule

Verilog Netlists

What is a netlist?

Lower-level representation than RTL Maybe translated from drawn schematics

• But often no schematic if synthesized

Represents transistor-level logic• If synthesized, transistors wrapped in library cells

• Library cells contain true transistor logic

• Raw transistors may appear for custom schematic design

Often Spice rather than Verilog used for transistor netlist

Synthesis Example: RTL

always @(posedge clk) beginfor (int i=0; i<3; i++) begin

if (enable[i]) beginfoo[i] <= newval[i];

end endend

Synthesis Example: Verilog Netlist

y00EnFlop(foo_0,newval_0,enable_0, clk);

y00EnFlop(foo_1,newval_1,enable_1, clk);

y00EnFlop(foo_2,newval_2,enable_2, clk);

y00EnFlop(foo_3,newval_3,enable_3, clk);

Transistor-Level Design Review

Basic CMOS Inverter

• P-stack passes 1s

• N-stack passes 0s

CMOS NAND gate

CMOS Complex Gate Example: ~(in1&in2 | in3)

State Elements: Latch

• Latch = level-sensitive

• How do we make an edge-sensitive flop?

Domino Logic: NAND example

Some References

http://www.verilog.net http://en.wikipedia.org/wiki/Verilog http://www.asic-world.com/verilog/veritut.

html http://en.wikipedia.org/wiki/CMOS http://assets.cambridge.org/97805218/73

345/excerpt/9780521873345_excerpt.pdf