the frequency and complexity

8/11/2019 The Frequency and Complexity

1/10www.ednmag.com March 16, 2000 | ed n 61

ANALYZING SIGNAL INTEGRITY IS NOT LIKE GAZING INTO A

CRYSTAL BALL OR SHAKING BONES OVER A DESIGN TO

DETERMINE ITS VIABILITY. YOU MUST IMPLEMENT A SET OF

TOOLS, SOFTWARE, AND REPORTING MECHANISMS TO

DETERMINE WHETHER A DESIGN IS ACCEPTABLE TO SHIP.

As the frequency and complexity of high-performance system designs increase,signal-in-tegrity analysis becomes exceedingly complex.

High-performance challenges include 1-GHz pro-cessors; edge rates of less than 100 psec; large num-bers of unique interconnected pc boards; ASIC pack-ages; and many signaling technologies, includinghigh-speed transistor logic (HSTL),low-voltage dif-

ferential signal (LVDS),positive-emitter-coupledlogic (PECL), opendrain, PCI, and low-voltage transistor-transis-tor logic (LVTTL). Accu-rately predicting systemperformance and avoidingsignal-integrity issues re-quires attention to detailsand sophisticated auto-mated processes. Fortu-nately, you can use various

processes and techniquesto meet the challenge andobtain success in the firstpass of all of your high-speed system designs.

Signal-integrity analysisaims to ensure that worst-case simulations for everyanalyzed network in asystem encompass actualmeasured data. The wave-forms in Figure 1 comparemeasured results with sim-

ulations of a complex mul-tidrop network. The signal

traverses packages, series resistors, connectors, anda long length of etch. According to the figure, themeasured waveform sits within the envelope of thetwo simulation waveforms.

To achieve this goal, dedicated and experiencedengineers work to ensure that the electrical design ofthe pc boards meets the system-design requirements.These engineers must use robust automated signal-

The nuts and bolts of

signal-integrity analysis

The goal of signal-integrity analysis is for the actual measured result to sit within a widow of worst-case simulations.

designfeature By Robert J Haller, Compaq Computer Corp

MEASURED WAVEFORM

FF SIMULATED

WAVEFORM

SS SIMULATED

WAVEFORM

F igure 1

V

nSEC


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designfeature Signal-integrity analysis

62 ed n | March 16, 2000 www.ednmag.com

integrity-design and -verification pro-cesses and accurate simulation models toensure signal quality across all high-speed digital signals, clocks, the powerdistribution in pc-board modules, and

interconnects. You must employ sche-matic-capture tools and circuit simula-tors for both pre- and post-layout simu-lations and make early decisions re-garding technology and package types,signal-to-return ratios, network treeing,topology, and termination.

Next,use automated CAD tools to ver-ify the signal nets prior to module release(Figure 2). These tools must includeSpice and behavioral I/O-buffer-infor-mation-specification (IBIS) simulationfor generating wire delays. Modeling the

multiboard environment is crucial ifhigh-speed signals traverse connectorboundaries. You should generate wire-delay files and feed them into a static-timing tool to verify the module per-formance as well as the chip I/Operformance.

Spice is the industry standard for elec-trical simulation because of its accuracyand the availability of free source code.Behavioral simulators have the advantageof fast runtimes, sometimes an order ofmagnitude faster than Spice. Some be-

havioral simulators also have extremelypowerful what-if capabilities, whichmake these simulators attractive to both

beginners and experienced signal-in-tegrity engineers. Theoretically, modelswill abundantly become available thatwill further behavioral-model growth.Spice and behavioral simulators each

have advantages. Behavioral simulatorscan analyze and report positive and neg-ative overshoot,nonmonotonicities,andring-back by virtue of excessive wire de-lays much faster than Spice. But Spicesaccuracy is necessary when youre ana-lyzing 1-GHz processors with little tim-ing margin.It is essential to analyze mod-ule-level crosstalk using one of the manyavailable tools. With the many signal-swing, etch-width, etch-spacing, and re-ceiver-susceptibility issues, the crosstalkproblem is too big to manage with sim-

ple wire and spacing rules.Using an automated process to extractnet configurations directly from layout tofeed into Spice prevents manual inter-vention and the possibility of human er-ror. Although time constraints may pro-hibit running 1000 network boardsthrough Spice overnight, having the au-tomated-extraction capability enhancesyour ability to quickly examine criticalnetworks on the module and frees thecritical signal-integrity engineers to ex-amine and solve real problems instead of

hand constructing and disassemblingSpice decks. Most companies that takesignal integrity seriously perform end-

to-end Spice simulations of representa-tive critical nets and use multiline com-plex-package and connector models.This approach lets you look at waveformbehavior from the input of the output

cell to the output of the input cell.In addition to having accurate models,a robust process flow, and talented signal-integrity engineers and module design-ers, you must also set up a formal mod-ule review process and strategy. Holdmodule reviews at least twice during thedesign process and at least once when theschematic set stabilizes.These reviews al-low the signal-integrity engineers andtheir peers to review any prelayout Spicesimulations, to ensure the proper imple-mentation of the clocking system and to

double check any reset or power-se-quencing requirements.A final layout re-view should be a gate to release the mod-ule. Investing time and effort into thetools, the analysis, and the review processwill simplify the design-verificationprocess.

PLAN, PROCESS, AND PERFORM

The work necessary to perform a thor-ough signal-integrity analysis generallycomprises the planning phase, the pro-cessing phase, and the performing phase.

Planning the work is the first step. Youneed to figure out how many modules toanalyze and how to analyze them. High-

SCHEMATICCAPTURE

PHYSICALLAYOUT

DATABASEEXTRACTOR CROSSTALK

CROSSTALKREPORT

SPICE SPICEAUTOMATIC

ROUTER

STATICTIMING

VERIFICATION

BEHAVIORALSIMULATION

INTERACTIVEGRAPHICAL

USERINTERFACE

PLOTS

REPORTS LENGTH,NET CONNECTIVITY,ATTACHMENTS,DIRECTORY OF PARTS/COMPONENTS, ANDPOSTSCRIPT

PLOTS

PLOTSREPORT OVER/UNDER-SHOOT REPORT

F igure 2

The signal-integrity process flow includes schematic capture, physical layout, Spice, and behavioral simulation.


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speed modules, such as CPUs, requireSpice and behavioral simulation,timing and crosstalk analysis,and a manual review of both theschematic and layer plots. On the other

hand, a console control-panel modulemay require only crosstalk analysis, lim-ited behavioral simulation, and a manu-al review. Define the requirements foreach module, then devise a plan and ex-ecute that plan.

Your work should focus on the system-design area that has the least amount ofmargin. Thus, you must plan for a mar-gin assessment. In addition, perform asignal-to-return-ratio analysis for thepackage and the connectors.Armed witha map of the modules and the type of

analysis they require, you can plan yourengineering- and computing-resourcerequirements.

You will spend a lot of initial time ob-taining, debugging, and verifying mod-els. You should not underestimate theimportance of model verification for ac-curate system analysis and, ultimately,problem-free system operation. Towardthe back end, data management and re-vision control will consume a lot of yourtime. Use foresight to save time and ef-fort during the project. Considering and

properly implementing something assimple as a signal-naming conventioncan save time over the project designslife. Plan on one engineer for two mod-ules, depending on the modules com-plexity,and give the most complex designobject to your senior signal-integrity en-gineer. Each engineer should have a Spicelicense, and at least half of the engineersshould have behavioral-simulator licens-es. A senior-level engineer should over-see all the modules, play backup, andwork out any kinks in the process and in

the models.Make sure to document required in-

formation from each module designerand track the model-developmentprocess.Early parts lists and snapshots ofthe design database, including both theschematic and physical layout, are crucialto keep the signal-integrity analysis onthe programs design and productionschedules. You can avoid impacting theprogram schedule by performing earlysignal-integrity analysis in parallel withthe design work. Obtaining models and

creating process flows and up-front

analyses in the early design stages mini-mizes the impact of signal-integrityanalysis on the product-developmentschedule. With proper planning, appro-priate resources, and a robust CADprocess, the signal-integrity portion ofthe module-design process can take lessthan a week. This one-week time frameassumes that the up-front data is readyabout a month before the pc boardsscheduled release and that signal-in-

tegrity analysis parallels the module-de-sign work.

CREATE STANDARDS AND WIRE RULES

You must create documentation,orsignal-integrity standards, for all the en-gineers on a project to follow. These stan-dards should specify all assumptions andmethods for signal-integrity analysis anddefine module-level I/O electrical pa-rameters.Use these parameters to drive aset of simulations. Then,employ the sim-ulation results to create a set of rules for

constructing the modules (layup), forconnecting the networks (layout), andfor driving and terminating signals.

The standard should cover simulationcorners and corner-definition rules. Ul-timately, you want to perturb simulationparameters that affect hardware per-formance from their nominal values ina way that exacerbates certain extremeelectrical behaviors. These behaviors in-clude worst-case signal ringing (referredto as an FF corner) and worst-case sig-nal delay (referred to as an SS corner).

The initials FF and SS refer to the char-

acteristics of the p- and n-channel FETs,respectively. That is, for an FF I/O cellsimulation, you use an F, or fast, p-chan-nel FET and an F, n-channel FET. An SSsimulation means that both FETs areslow during the simulation. The initialsalso describe the overall simulation cor-ners. For example, an FF simulationmeans not only that you are using fast p-and n-channel FETs but also that thevoltages and temperatures during the

simulation result in the fast circuit per-formance. So, FF means fast silicon anda fast environment.

Sometimes modules contain bothCMOS and bipolar devices. It is impor-tant to characterize the bipolar modelsover temperature and characterize thesupply-voltage ranges to determine howthey compare with CMOS. You shouldput together tables of corner-definitionrules that summarize how parametersmust vary as a group for different typesof drivers.Table 1 is an example of a cor-

ner-process-parameter table.You must modify the simulation-

analysis thresholds from their typical orspecified values to account for variousac- and dc-noise sourcessuch as back-ground noisethat the simulation cantaccount for. You should add ac crosstalklimits to dc requirements to ensure ade-quate signal integrity and network per-formance.

You should run crosstalk software onevery pc board in the system to ensurethe maintenance of acceptable spacing

rules between signals. Because CMOS

DIFFERENTIAL-AMPLIFIER

OFFSET VOLTAGE-DIVIDERTOLERANCE VREFAC NOISE

1.0

0.9

0.8

0.7

0.6

0.5

0.75

CROSSTALK

CROSSTALK

VIH

VREFVREF SPEC

VIL

F igure 3

A sample ac-noise margin for high-speed transistor logic includes VREF

variations, VIH

and VILvaria-

tions, and crosstalk variations.


4/10



LVTTL voltage amplitude is significant-ly higher than HSTL voltage amplitude,you should observe careful module lay-out and verify the layout to ensure ac-ceptable ac noise margins. Using Spice,

you must obtain a simultaneous switch-ing penalty and verify that the noise mar-gin is adequate. Further, you must deter-mine a simultaneous switching penaltyfor each package type and add or subtractthis penalty to the timing margin. Theautomatic module-level timing verifica-tion of the chips I/O pin must includethis penalty. Figure 3 shows a sample ac-noise margin for HSTL.

Figure 4 shows a plot of the backwardcrosstalk coefficient Kb versus line spac-ing for a typical CMOS module layup.

Note that the crosstalk dramatically in-creases as line spacing decreases. For anominal 5-mil line with 10-mil spacing,Kb is about 11.5%. If you decrease thespacing to 5 mils, the nominal backwardcrosstalk increases to almost 19%. Thus,if you have a 3.3V signal routed at 10 milsaggressing an HSTL signal, you end upwith 3.3V0.1150.379V of noise,which represents the typical conditionsin the worst-case direction. This amountof noise is considerably more than theentire HSTL noise margin of 0.25V that

exists between VREF (0.75V) and margin-ed V

IH(1.V). (See chapter 4 ofReference

1 for more information on calculatingcrosstalk.)

MODELS, MODELS, MODELS!

Accurate models of semiconductors,passive components, and parasitics arenecessary to create accurate circuit- orsystem-level simulations.Conversely, badmodels will result in bad electrical-net-work-simulation results.For this reason,bench verification of circuit models is

crucial prior to shipping any productboards for fabrication. You should counton initially spending about half of yourtime obtaining, debugging,and verifyingsimulation models. Signal-integrity en-gineers spend half of their time as mod-eling engineers.

Start obtaining semiconductor modelsearly,so you have time to verify that yourtechnology and part selection are ade-quate for your system-design perform-ance requirements. As soon as moduledesigners know what part families the de-

sign uses, signal-integrity engineers must

obtain, debug, and verify IBIS and Spicemodels.Pay attention to the models of all

of the passive components in your sys-tem. It is important to correctly modelconnectors and packages. If your edgerates are less than 500 psec, you shouldprobably use lossy transmission-linemodels.

Do not let a module designer use com-ponents that have unavailable simulationmodels unless extenuating circumstancesexist. Unfortunately, as many engineershave discovered, collecting Spice modelsfrom third-party semiconductor vendorsis one of the most difficult tasks a signal-

integrity engineer undertakes when per-forming system-level analysis.

COMPARE MODELS WITH REAL BEHAVIOR

It is paramount to compare your mod-el with real measurements.Even with duediligence and accurate modeling tech-niques, expect some imperfections be-cause of underlying limitations in the be-havioral-modeling algorithms and spec-ifications as well as in the measurementtechniques. After you look at the modelin the lab, go back to the vendor to re-

solve any discrepancies. To remedy prob-lems with model accuracy and build con-fidence in a model, be sure to developsound methods to generate and validatethe models.Some system-design compa-nies have been doing this work them-selves for decades, but it has never beencost-effective. The Signal-Integrity (SI)Reflector is an open Internet forum inwhich engineers discuss signal-integrityissues, including model accuracy andmodel verification. This forum highlightsthe need for system vendors to create and

verify their own models. The availability

of accurate models should eventually re-duce the the engineers burden of rou-

tinely performing this work.Also, a group of engineers from vari-ous companies are working on the IBISaccuracy specification. This specificationattempts to get semiconductor ven-dorsusually the model originatorstoverify their models using a predefined setof test loads on the bench and then todocument those results in a consistentformat for their semiconductor cus-tomers. The specification should reducethe daunting task that signal-integrityengineers presently face: to ensure not

only that all of the parts in a system op-erate reliably over the life of a productbut also to make certain that the modelsactually represent the true devices (Ref-erence 2).

Some engineers advocate the use ofmodels that you derive exclusively fromone part in the lab. Unfortunately, mod-els developed from lab data cannot ac-curately represent process and tempera-ture corners. Also,adequately comparingbench waveforms to Spice requires data-acquisition software and a waveform

viewer that can overlay bench and simu-lated waveforms on the same plots. Thisprocedure eliminates time and voltage-scale differences, which would affect yourability to ascertain whether the correla-tion is acceptable.

MEASURING SEMICONDUCTOR MODELS

Ensuring first-pass design success re-quires that you spend time verifying thatthe results of your simulator using semi-conductor models match the bench-testresults. You must use appropriate tech-

niques when obtaining bench measure-

TABLE 1CORNER VALUES FOR CMOS AND BIPOLAR DEVICESParameter SS corner TT corner FF corner

VDD

(V) 3.0 3.3 3.45

VCC

(V) 4.5 5.0 5.5

VDDQ

(V) 1.4 1.5 1.6

VREF

(V) 0.70 0.75 0.80

Bipolar temperature (C) 0 27 + TJA

100

CMOS temperature (C) 100 27 + TJA

0

LVTTL impedance () 55 60 65

Bipolar, HSTL, and clock impedance () 45 50 66

Propagation delay (psec/in.) 0.200 0.175 0.160

Lengths minimum average maximum

Termination resistance, series maximum nominal minimum

Termination resistance, parallel minimum nominal maximum


5/10



ments including high-bandwidth scopesand ensure that the scopes bandwidth isadequate for the signals you are measur-ing. Assuming a Gaussian edge, a simplerelationship exists between the 10 to 90%

rise time of a signal and its frequencycontent (Reference 3):

If the aggregate bandwidth of the os-cilloscope and the probe is not highenough for the rise time in question, thetest equipment will attenuate high-fre-quency components of the waveform,and the measurement will be in error.The following equation expresses the

measured rise time as a function of thetrue rise time, the oscilloscope band-width, and the probe bandwidth (Refer-ence 3):

You can use the following simple ruleof thumb for a quick check:

For example, if your fastest edge rate is0.285 nsec, you must have an effectivebandwidth of your scope and probe of1.2 GHz or you will be missing informa-tion. Also, if you have little glitches that

are faster than your edges, you wont seethese glitches if the scope does not haveadequate effective bandwidth.

CREATE TEST VEHICLES FOR THE MODELS

Creating simple test vehicles to verifyall of your models will help you ensureaccurate modeling without wasting valu-able design resources. Although these testvehicles are important, they have a highcost of engineering manpower, capitalequipment, and scheduling.With a littlecleverness, you can integrate multipleverification tests into one test vehicle.Forexample, you should place test traces ofvarying lengths on the same module asthe connector. Use an identical layerstack-up as your system board and make

sure to include test structures to look atthe various parasitics of your networkpath, such as vias, pads, and dispersions.

For example, put two traces on yourtest board,with identical fixturing at eachend, using SMA connectors that easilymate with a high-speed scope.Then place20 vias of the designs predominant sizein one of the traces. Measure the charac-teristic impedance of the test trace andthe difference in delay between the tracewith and without vias. Using the teleg-raphers equations, Z

0L/C and

TPDLC, you can calculate the effec-tive capacitance from the impedance andthe change in the propagation delay (Ref-erence 1). Make sure to measure thepropagation delay at a representative risetime and not at the time-domain reflec-tometers (TDRs) rise time.

Divide the total capacitance by 20, orthe number of vias, to accurately meas-ure the capacitance of a single via.

Connectors are a common problem insystem design for both electrical and me-

chanical engineers.You can design a sim-ple connector test vehicle to aid in thecharacterization. You should measurecharacteristic impedance, propagationvelocity, crosstalk, and the effects of si-multaneous switching on delay. You canaccomplish this measurement by wiringequal lengths from an SMA to the con-nector. Take care to minimize, if noteliminate, module crosstalk so that youcan independently examine connectorcrosstalk.

MEASURE CONNECTOR CROSSTALK

You can use several techniques tomeasure connector crosstalk.The multi-ple-active testing technique and the sin-gle-active testing technique have excel-lent correlation. Using the multiple-active technique, you simultaneouslyswitch many lines in a connector andmeasure the impact on a victim under aspecific set of edge-rate and signal-swingconditions. Using the single-active tech-nique, you stimulate one line and meas-ure the impact on the surrounding vic-

tims.Adding up the victims voltages andusing the principal of superposition pro-vides a total crosstalk number. This ap-proach is equivalent to the multiple-ac-tive approach,in which fixturing is moredifficult to perform. Using edge ratesequal to or greater than 250 psec, theprincipal of superposition applies to con-nector crosstalk.

Table 2 shows an example of this ap-

TABLE 2CONNECTOR-CROSSTALK VALUES USING THE SINGLE-ACTIVE TECHNIQUE

Victim nodes Aggressor nodesA_1TO1A1 A_1TO1A2 A_1TO1A3 A_1TO1A4 A_1TO1C1 A_1TO1C2 A_1TO1C3 A_1TO1C4

A_1TO1A1 11.50 5.90 3.75 7.30 3.75 2.30 1.80

A_1TO1A2 11.50 10.50 5.00 4.40 4.20 2.90 2.20

A_1TO1A3 5.90 10.50 9.20 3.00 3.10 3.90 2.80

A_1TO1A4 3.75 5.00 9.20 2.10 2.10 3.10 3.90

A_1TO1C1 7.30 4.40 3.00 2.10 6.25 2.40 1.40

A_1TO1C2 3.75 4.20 3.10 2.10 6.25 5.40 2.00

A_1TO1C3 2.30 2.90 3.90 3.10 2.40 5.40 5.00

A_1TO1C4 1.80 2.20 2.80 3.90 1.40 2.00 5.00

Sum (mV) 36.30 40.70 38.40 29.15 26.85 26.80 25.00 19.10

Percent of signal swing (Kb) 18.62 20.87 19.69 14.95 13.77 13.74 12.82 9.79

Notes: Trise=250 psec.Step size=195 mV.

.F

338.0T

dB3RISE=

.F

338.0

F

338.0T

T

2

PROBEdB3

2

SCOPEdB3

2RISE

MEASURED

+

+

=

.T0.338

1

PROBE)(SCOPEBANDWIDTH

R

+

E.CAPACITANCTOTALZ

TC D ==


6/10


70 ed n | March 16 , 2000 www.ednmag.com

proach. The first row con-tains the names of the ag-gressor lines and thefirst column containsthe names of the victim

lines. You aggress one lineand record the resultant re-sponse of the victim in theappropriate entry. Makesure you implement the ap-propriate grounding pat-tern in your connector testvehicle. It is also imperativeto measure crosstalk andpropagation delay at thefastest edge rate you plan onusing in your system.

After you create and

measure the electrical pa-rameters of your connector,compare these parameterswith your requirements forsimplified connector selec-tion. Many types of shield-ed connectors require a 3-Dfield solver unless the con-nector vendor provides avalidated model near your required edgerates. Compare simulation with meas-urements to understand the accuracy ofthe model. Then, write a specification

that guarantees that your product meetscritical electrical acceptance criteria. Ifpossible, implement a quality-assuranceaudit at the vendor site to ensure that theproduct continues to meet the criteriathroughout its life. When using ASICpackages,you should also create all of themodels and test vehicles and perform theverification for connectors. Using a ver-ified, accurate vendor model can save youtime and resources.

IMPLEMENT CLOCK FORWARDING

Many design teams now use theclock-forwarding, or source-synchro-nous-clocking, technique. When usingthis technique, you simultaneouslytransmit data and clock from the samesource chip, delay the clock half of a bittime, and then receive the clock and dataat the destination.This technique has theadvantage of much higher bit rates and,consequently, higher clock frequencies.Italso enables you to traverse long wireswith a minimal system-cycle-time penal-ty. This approach can also save pins. The

key is to match the electrical and physi-

cal environment and minimize skew be-tween what the clock and data signals seewhen they traverse their wire. In ex-tremely high-speed applications, this

matching applies not only to electricallengths but also to layers,via counts,andcrossovers. Be sure to use point-to-pointconnections for all high-speed applica-tions. Using both edges of the clock alsocomplicates the design and skew budg-et. The important contributor is not thetotal latency but the variation in delayfrom the various contributors.

To calculate a clock-forwarding budg-et, such as in Table 3, you must first un-derstand all of your variables.Etch delaysnormally vary from 160 to 210 psec/inch.

You can greatly reduce this range if youadhere to strict layout rules because, inthis case, the difference between the clockand the data is relatively small.If you im-plement aggressive layout rules in aunistripline controlled-impedance envi-ronment and verify through test-vehiclemeasurement, you will obtain specifica-tions such as 1 psec/in. under certainconditions.

However, this etch-delay numbercomes at a cost. Make sure you reallyneed1 psec/in. because it is difficult to

balance etch to these tight tolerances. You

quickly get into trouble if you use worst-case analysis. When doing clock-for-warding analysis, you must tabulate thedelay-variation contributors and the de-

lay variations between clock and data sig-nals.Some of the major contributors in-clude duty-cycle variations, skewbetween local copies of a clock (onASICs), threshold mismatches, clock-versus-data delay through an output cell,simultaneous-switching effects, andpackage-trace skew (both driver and re-ceiver). Other major contributors areetch mismatch between data and clock,dc offsets between transmitter and re-ceiver, receiver-threshold variations toon-chip signal intergrity and noise, de-

lay-line tolerance, duty-cycle symmetry,mismatch across clock-and- data-receiv-er cells, and clock-loading mismatches.

OUTLINE THE PROCESS

After planning, the next phase of sig-nal-integrity analysis is to develop anddebug a robust signal-integrity process(Figure 2). You must have an automatedset of scripts and tools that allow you toverify a design without a lot of manualintervention. All designs must proceedthrough this standard process, or flow.

Some designs may require additional

F igure 4

In a typical CMOS module, crosstalk increases dramatically as line spacing decreases.

% CROSSTALK (Kb)

LINE SPACING (5-MIL LINE)

ABSOLUTE WORST CASE

MAXIMUM DIELECTRIC,

MINIMUM ETCH

MINIMUM DIELECTRIC,

MAXIMUM ETCH

NOMINAL


7/10



work. The time you spend developing astandard flow, libraries, and a revision-control system is essential and well spent.Your designs may change many times,but once you have a verified process and

accurate libraries, reverifying design ob-jects is greatly simplified. You must reactquickly when designs change, and youmust be able to go back to a previous de-sign state. You should implement a ro-bust revision-control scheme on yourdisks for software, libraries, and designobjects. This measure will enable you todetermine the root cause of an issue if de-sign object changes and unforeseenprocess problems occur.

After you determine the generalprocess flow and set up a working direc-

tory for each design object that uses aconsistent and succinct naming conven-tion, determine which tools each designrequires. Your manager can trackprogress by maintaining a spreadsheetwith the design-object revisions and toolrequirements. Most of your high-speeddesignssuch as CPUs, memories, andbackplanes or system boardsrequireSpice, behavioral, timing, clock, cross-talk, and manual checks. Other designobjects require a subset of these checks.An I/O module may have high-speed

sections that require a complete analysis.The slower speed sections, which maynot even have models, require only asubset of the complete analysis. A con-sole control panel that interfaces to theI/O should be sufficient to place series

resistors on the outputs of any criticalsignal, perform a quick crosstalk run,and then manually review the plots.

Evaluate each design object and doc-ument the analysis that each object will

undergo. When the analysis is complete,the design is ready to ship. This processmakes signal integrity more predictableand reliable.Certain designs may requirespecial analysis. For example, a PCI busmay require configuration testing. Youcan do this testing using Spice or behav-ioral simulation depending on modelavailability and design constraints. If youhave accurate behavioral models and agood simulator,then a typical design mayrequire only an hour to run through. Themost important and effective use of be-

havioral simulators is for final board ver-ification just prior to shipping etch art-work to the pc-board vendor. An ex-perienced signal-integrity engineer canturn a complete board design in hours orless. If necessary, he or she can imple-ment fixes and feed them back to layout.He or she can quickly uncover commonrouting, topology, termination and con-figuration problems and perform the op-timization. The turnaround time forrunning Spice on every net is too long.Designs often change immediately before

you release the artwork,and a quick ver-ification of the board is essential to iden-tify any problems that the change mayintroduce. If you dont analyze every net,you will likely have problems with at leastone of them. Find and fix the problems

to ensure first-pass success.The signal-integrity engineer should

understand the details of the behavioralsimulator and models and their limita-tions to make appropriate trade-offs.

Poorly designed or poorly decoupledpower and ground planes on a board canalso result in inaccurate results from be-havioral simulators and Spice. You mustfollow good signal-integrity-board de-sign practice for models to accuratelyrepresent the circuit in a system.

APPLY DECOUPLING STRATEGIES

Decoupling is an important aspect ofsignal integrity. You should use tradi-tional decoupling and bypassing tech-niques.Follow rules of thumb and meas-

urement techniques including the use ofa spectrum analyzer on the final designto avoid problems.If you can afford it, in-vest in a decoupling expert. The systemshould use several capacitive decouplingand bypassing methods to ensure cleanpower to all loads on the modules. Youcan use the following hierarchy: First, usebulk storage capacitance to provide cur-rent to the module when the converter isstarting to respond to a load change.Uselocal decoupling for both the load andthe module. These capacitors supply the

high-frequency current demands of thelocal load. You will also require medium-frequency bypass capacitance to roll offthe higher frequency switching noise thatthe switching loads generate. You can addthese capacitors on a per-unit area toeach power plane for each module. High-frequency bypass capacitance is neces-sary for closely coupled power to groundplanes and provides an intrinsic capaci-tance within a module with extremelylow equivalent series resistance (ESR)and equivalent series inductance (ESL).

It is also critical that power planes aretightly coupled to a ground plane. Oth-erwise, additional low ESL and ESR ca-pacitors may be necessary.

Careful choice of plane assignment canoptimize the decoupling. Local chargedepletion first occurs in the area betweenthe power planes that are directly underthe load because this capacitance is near-ly ideal, with minimum self-inductanceand resistance. As the charge depletioncontinues between the planes, the localdecoupling capacitors and the current

that the medium-frequency bypass ca-

TABLE 3SAMPLE CLOCK-FORWARDING SKEW BUDGETBudget item Minimum Maximum Total

Clock duty-cycle variation (inside source chip) -200 200 400

Skew between local copies of clock (on ASIC) -100 100 200

Threshold and delay mismatch of driver output cells -100 100 200

Edge-rate mismatch between clock-and-data output cells -200 200 400

Simultaneous switching effects (crosstalk, di/dt, and others) -100 100 200

Package-trace skew in driver and receiver packages -50 50 100

Etch mismatch between clock and data -50 50 100

DC offset between driver and receiver I/Os -50 50 100

Receiver-threshold mismatch between clock and data receivers -50 50 100

Receiver VREF

variation due to on-chip noise -50 50 100

Duty-cycle symmetry mismatch between clock and data receiver -200 200 400

Skew between mismatch of data and clock loading 0 700 700

Total skew range 3000

Worst-case setup 500 500

Worst-case hold 0 0

Skew range + worst-case setup 3500

Note: Minimum cycle time=(skew range + worst-case setup)2. 7000


8/10



pacitors provide begins to recharge thearea between the planes. Finally, currentfrom the bulk capacitors recharges the lo-cal decoupling capacitors.The converterrecharges the bulk capacitors. A goodsuggestion for bulk decoupling is to use

100-F tantalum capacitors evenly dis-tributed across the board. For global,high-frequency decoupling, use one0.01-F multilayer ceramic capacitor ina 1206 package every 2 in.2, evenly dis-tributed across the board.For local high-frequency decoupling underthe component, use one 0.01-F capacitor perV

SS/V

DDpin pair

and one capacitor per eightswitching outputs,with a min-imum of two per component.

As you use more advancedtechnologies with faster edgerates, maximizing intrinsicboard capacitance and mini-mizing the inductance of ca-pacitor leads and dispersionetch is critical. Figure 5 showsa differential measurement ofthe power planes on an activebackplane. This backplane hasmore than 5000 networks, 17ASICs, 20 layers over sevenunique voltages, and more

than 100 high-speed connec-tors. The bottom trace is aground base line with bothends of the differential probeshorted to ground on a largepad with a maximum devia-tion of 12 mV. The center traceis the voltage reference for theHSTL differential amplifier(V

DDQ) measured at the pins of

the ASIC; it varies by less than 14 mV.The top trace is the supply rail (V

DD); it

varies by less than 23 mV.

PERFORM MULTIBOARD ANALYSIS

Today, some tools lack the ability to dosoftware simulation across connectorboundaries. However, employ this typeof simulation if any part of your high-speed design traverses connector bound-aries. The simple addition of 1/2 in. ofetch on a dual-in-line-memory-module(DIMM) connector daisy-chained fouror eight times can cause a memory de-sign to fail if you dont properly modelthe connector. The lack of industry tools

including this capability is, in part, due

to the lack of a connector-model stan-dard within the IBIS standard. But thissituation is rapidly changing. A commit-tee in the IBIS open forum is developinga connector spec that should become astandard and give all IBIS-member sim-

ulation companies the ability to performmultiboard simulation. With the adventof upgradable memory and processors,the need for connector and packagemodel integration in the signal-integri-ty process flow is paramount.When you

can traverse connector boundaries, youcan easily and automatically performconfiguration testing.

Realize that all of the simulation toolscontain some basic assumptions. Youmust understand the underlying as-sumptions as well as the algorithms ofthe tools. One important assumption tounderstand about your designs is returncurrents particularly their effect on be-havioral simulators. If you have not ade-quately decoupled your design and havenot analyzed your tools assumptions,you may end up with large amount ofnoise induced on your signals from pow-er planes. Many passive-component sup-

pliers, particularly connector suppliers,

provide matrices for you to use in yousimulations. Field solvers create thesematrices, which contain unique algo-rithms and assumptions. Some fieldsolvers create loop inductances; otherscreate so-called partial inductances. You

should attempt to anticipate the correctanswer before you run a simulation. Ifthe results look suspicious, you need toinvestigate and determine whether youhave a tool or model problem or a net-work problem. By itself, the use of partial

inductances, such as those that connec-tor companies often provide, revealsnothing. However, using these induc-

tances to form a loop implements a com-plete network with a signal path and a re-turn path. Avoid violating any of thetools underlying assumptions, such asconnecting ground to both sides of aconnector, or the final answer may bewrong. Manually reviewing plots canverify other underlying behavioral-sim-ulator assumptions. Most behavioralsimulators analyze traces as transmissionlines using 2-D field solvers. If you routehigh-speed signals across a power orground splita void area or a lack of

copper on an adjacent reference plan that

F igure 5

Differential measurements of power and ground show that using decoupling strategies results in modest noise

levels.

mV

nSEC


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a high-speed signal can crossvoids theanalysis.Carefully check the plots for thistype of problem and other assumptionsthat invalidate the tools results.

PERFORM THE ANALYSIS

To describe signal-integrity analysis aspushing the button oversimplifies thefinal verification. Significant effort bysoftware and hardware engineers allowsyou to walk up to your workstation andtype in DO_IT to run the analysis.

Because behavioral modeling is so im-portant, final verification requires othertricks. You need to create simplified pack-age models from the fully coupled Spicemodels. Running Spice on a completemodule can take days,so your post-route

verification needs to include critical par-asitics that dont overburden your runtimes. If you automate the topology ex-traction, batch submission,and delay ex-tractions from Spice , you can set up themultiple day simulation to run in paral-lel with the behavioral simulation andthe final-artwork-check procedure.

You can achieve significant scheduleadvantages by doing some behavioralsimulation using the following simplifi-cation. Some behavioral simulators can-not deal with discrete RLC circuits. Thus

you need to model RLC circuits withtransmission lines. The trick is to selecta delay value (or T

PD) that is a small per-

centage of your overall cycle time. Then,construct a behavioral model that dupli-cates a Spice one-pin package model us-ing ideal transmission-line segments. Inthe behavioral simulation, the model be-comes a drop-in replacement.

You can again use the telegraphersequations from Reference 1 to calculateequivalent impedance for a given induc-tance/capacitance and a short delay, such

as 10 psec. For example, to create a sim-ple pie network with a 3.4-nH inductorand a 1.0-pF capacitor, you need to cal-culate transmission-line impedance Z

0as

follows:

and

Thus, in your behavioral model, youcan insert a transmission line ofZ

0340 and T

PD0.010 nsec to repli-

cate the 3.4-nH bond-wire inductance.You can also insert a transmission line

with Z010 and TPD0.010 nsec toreplicate the 1-pF capacitance of a typi-cal via.

REVIEW REPORTS, FIX PROBLEMS

Once you have the tools to run mod-ule and system-level behavioral simula-tions, you should be able to output a re-port that contains overshoot (bothnegative and positive), nonmonotonicbehavior, and wire delays. Then reviewand fix all of the violations or obtain for-mal waivers from your formal signal-

integrity pass/fail criteria. Justifyingwaivers is cumbersome and difficult, sofixing the problems is usually simpler. Byfixing the problem, you may be able todesign in additional margin that willminimize the effect of minor inaccura-cies in some of the underlying assump-tions, models, and processes. An error-free log file of overshoot,nonmonotonicbehavior, and wire delay is one of thepass/fail criteria.

Next, you can feed the wire delays intoyour static or dynamic timing verifier.

This step will enable you to uncover anytiming problems or marginality in thedesign. The timing verifier catches anymultithreshold crossings or nets with ex-cessive length. Due diligence is necessaryin examining intermediate and final logfiles to ensure that you analyze every tar-geted network in the design. Reviewclock-skew tables, multicycle paths, andignored networks with the key designerof that module. Using the necessary andsufficient criteria when performing yourback-end checks will assure you of first-

pass success. You can also look at globalslack reports, which are detailed listingsof timing margins that static-timing-ver-ification software tools automatically cre-ate.These reports determine, to some de-gree, how to speed your design formidlife kickers,or those design upgradesthat come shortly after new-product re-lease and are usually associated with aCPU speed up. Long networks withmany contributorscomponents in thepath, etch traces, connectors, and semi-conductorsmay end up near the top of

the slack-report list if modeling tech-

niques are too conservative. The sameengineer that created the models imple-mented in the process flows and mustrun the tools before he or she reviews andsigns off on the design. If you are mod-

eling packages or connectors with simplesingle-line models, you need to includea simultaneous switching penalty in thetiming-verification phase.

Ultimately, timing verification,behav-ioral simulation, and crosstalk are inter-related, and more robust tool suites thatinteract are necessary. The most chal-lenging tasks that signal-integrity engi-neers will face in the immediate futureare power and ground-plane, distribu-tion, and package modeling. You canavoid crosstalk problems with simple

spacing rules. However, you must use arobust process to analyze the design atthe end of the design cycle. Crosstalkproblems are difficult to track down inthe lab because they can depend on datapatterns. Thus, you are better served byavoiding the problem. Run a full post-route or multimodule crosstalk analysison your finished pc board. This analysisis another one of the pass/fail criteria pri-or to etch release. You can even run thisanalysis on simple slow-speed boards us-ing default logic-family edge rates and

signal swings.As timing becomes more difficult and

frequencies increase, you will need to runmore Spice.Remember that Spice is a be-havioral simulator and a mathematicalrepresentation. Still, it is the most wide-ly used circuit simulator. After you haveweeded out all of the real design flaws, itis time to attack the other violations.Youshould autoextract network topologiesfrom your board database. A few goodautoextraction tools exist. You can thenrun Spice on a subset of the entire board.

You can merge and override behavioralwire delays with Spice delays to obtain aclean timing run. It is important to cre-ate and verify timing models, but servic-es are available to accomplish this task foras little as $1000 per board.Because mostboard designs have a limited number ofclocks,Spice is an excellent way to ensureaccurate modeling of the most criticalparts of your design.

DO A MANUAL CHECK

Before you approve the design for re-

lease, perform a manual layout check.

,340nSEC0.010

nH4.3

T

LZ

D0 ===

.10pF1.0

nSEC010.0

C

TZ D0 ===


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78 | M 6 d

You need to look closely at the design toverify the tools underlying assumptions.High-speed nets should not route close-ly to or contact mechanical parts thatwould disrupt the controlled-impedance

environment. Check the box on the me-chanical drawing that requires the boardto have controlled impedance. Other-wise, run the simulations to guaranteethat controlled impedance is unneces-sary. Run 2-D field simulations and ver-ify correct layup and line widths.

At this point,you can call a formal de-sign review and sign-off meeting. Makesure everyone who is responsible for a keypiece of the design has reviewed it andapproved it. Walk through the schemat-ics and plots. Verify any schematic

changes that have occurred since theschematic-set review.Check over the me-chanical drawings including layup andline widths, unit assembly, and parts listand spend extra time reviewing hardcopies of the layer plots.Catching a high-speed trace traversing a power split or un-der a handle could save days or evenweeks in the lab. A qualified engineershould review the design for EMI/RFI is-sues, such as high-speed oscillators nearcabinet openings. Then, fill out a sheetof paper that includes the initials of those

who checked part of the design and thepart they checked. Due diligence preventsstupid mistakes.

Finally, have the signal-integrity engi-neer review his analysis and highlightany risks. You must gate the final releasewith a module check list. If any excep-tions violate the release process you haveimplemented, document the risk, andthen ensure management signs off on awaiver. Most people will not sign-off ona design unless they have verified its ac-curacy. Many will complain about this

formal sign-off procedure because ittakes time and effort, but no one willcomplain when you achieve first-passsuccess and avoid painful months in thelab debugging signal-integrity problemsthat you could have easily caught in a de-sign review.

All of the simulation you already per-formed can now aid in final design-veri-fication testing. You should compare de-lay files and timing-verifier results withactual measurements. Make sure probeparasitics and fixturing includes any

comparison between measurements andsimulations.You can also compare meas-ured waveforms with simulations. Youneed to perform dc and ac measurementsof power and ground planes. Compare

these measurements with budgets andpredictions. If possible,place your systemin a schmoo chamber to determine volt-age and temperature margins.Increasingthe clock frequency will uncover the tim-ing margin for a random sample of thedesign.V

REFschmooing is another recent

addition to design-verification testing.For this test, you place potentiometers onthe resistors that set the reference volt-age for the HSTL differential amplifiers.You then move the voltage up and downto determine your noise-margin window.

This process provides insight into whichnetwork interfaces contain the least noisemargin. Document your work. You maybe the one who benefits the most. Yourcustomer will certainly appreciate thatyouve done your homework.

References

1. Blood, W R, Mecl System DesignHandbook, Motorola Inc, Phoenix, AZ.

2. Haller, R, and G Edlund, Con-structing Accurate Models of BehavioralI/O buffers, Designcon98 proceedings,

ISSN 0886-229X, ISBN 0-933-217-47-1,1998.

3. Johnson, H, and M Graham, High-Speed Digital Design, a Handbook of BlackMagic, Prentice Hall, Upper Saddle Riv-er, NJ.

Acknowledgement

Many thanks to Barry Maskas, PeterLaFlamme, Greg Edlund, and PaulGuglielmi for their insightful suggestions.

Author biography

Robert J Haller is a seniormember of the technicalstaff in the Alpha Serverproduct-development di-vision at Compaq Com-puter Corp, where he hasworked for 19 years. Hedesigns boards, back-

planes, and custom ICs and has spent morethan 10 years developing board-level sig-nal-integrity products. He has a BSEE fromthe University of Massachusetts (Amherst,MA).

Circle 6 or visit www.ednmag.com/infoaccess.asp

the frequency and complexity

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