The Future of Devices & Chips:A Blast from the Past?

Elad Alon

Berkeley Wireless Research CenterUniversity of California, Berkeley

Collaborators: Tsu-Jae King Liu (UC Berkeley), Dejan Markovic (UCLA), Vladimir Stojanovic (MIT)

Moore’s Law and Original Issues

Design cost

What to do with all of the functionality possible

Power dissipation

22

Power Consumption…

Since ~2000 supply voltage (Vdd) stuck at ~1VLeakage stops you from lowering threshold (Vth)

Leads to very poor power scaling1kW chips?

33

400480088080

8085

8086

286386 486Pentium® proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Pow

er D

ensi

ty (

W/c

m2

)

Hot Plate

Nuclear Reactor

Rocket Nozzle

S. Borkar

Sun’s Surface

Power Density Prediction circa 2000

Parallelism to the Rescue

Parallelism allows slower, more energy-efficient unitswhile maintaining performance

Will this last forever?44

Where Parallelism Doesn’t Help

55

CMOS circuits have an absolute minimum energy/opNeed to balance leakage and active energies

Limits energy-efficiency, no matter how slowly the circuit runs

What if There Was No Leakage?

66

Supply voltage decreases energy decreases

Mechanical switches don’t leak, turn on abruptlyPotential pathway to continued scaling

Measured MEM Switch I-V CurveIdeal Switch Energy vs. VDD

[R. Nathanael et al., IEDM 2009]

77

Switch Structure & Operation

ON Switch:|Vgb| > Vpi (pull-in)

OFF Switch:|Vgb| < Vpo (pull-out)

Poly-SiGe

Tungsten

Relay Logic

Relay delay dominated by mechanical motion

So, implement logic as a single complex gateAll devices move at the same time

Improves area, device count, performance88[F. Chen et al., ICCAD 2008]

Logic Demonstration

Relays built with 1µm lithography - clearly not yet competitive with CMOS…

What does it take to get there?

99[F. Chen et al., ISSCC 2010]

Scaling and Comparing to CMOS

1010

9x

10x

Vdd: 0.9V

0.32V

Vdd: 1V 0.5V

Energy/op vs. Delay/op across Vdd

Reminder: parallelism enables high throughputEven with slower individual elements

At 90nm, simulated relay adders are:

>9x lower E/op>10x greater delay

Scaling similar to CMOS

Smaller = faster, lower voltage, lower power

[H. Kam et al., IEDM 2009], [F. Chen et al., ICCAD 2008]

Relay Reliability

Increase contact resistance to improve reliability

Delay dominated by mechanics anyways

Measured > 60 billion cycles so far1111

AFM Measurements

Never tested

Dimple

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. i.)

19nm

Dim

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(a) (b)

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0 10 20 30 40 50

0 10 20 30 40 50

Height (nm)

Height (nm)

19nm

Dim

ple

(c) (d)

FRESH CONTACT

Contact Dimple

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19nm

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0 10 20 30 40 50

0 10 20 30 40 50

Height (nm)

Height (nm)

Dim

ple

AFTER 109 cycles

Contact Dimple

3 µm

3 µm

19nm

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+0 1.E+3 1.E+6 1.E+9No. of on/off cycles

Con

tact

resi

stan

ce [Ω

]

100kΩ specification

L=25µm

Measured in ambient

[H. Kam et al., IEDM 2009]

Circuit Demonstration Test-Chip

1212

Test devicesLogic Timing ElementsMemoryI/O

[F. Chen et al., ISSCC 2010]

Relay DRAM

1313[F. Chen et al., ISSCC 2010]

Near-Term Driver: Power Gating

1414

Leakage of inactive CMOS circuits often limits embedded devices’ lifetime

Relay power gates could eliminate leakage

[Picocube, Rabaey]

Complexity

Year

101

102

104

>109

Basic Circuits

FunctionalUnits

C

ALU

2009 2010 2011

Scaling

PowerGating

>2012

CMOS Relay

?

Roadmap: Back to the Future?

1515

Final Note: Rethinking Scaling

1616

[Rabaey, UCB]

Many exciting new apps based on mobility and sensing

Innovation and cost driven by functionality – not just computing…

[Nguyen, UCB]

[Venkatraman, Carmena, UCB]