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Semiconductordiode

May 19, 2023

Advanced Laboratory for Characterization of Semiconductor Devices - 31820

Department of Electrical & Electronic Engineering ORT Braude College

Dr. Radu Florescu Dr. Vladislav Shteeman

Department of Electrical and Electronic Engineering ORT Braude College of Engineering

Advanced Laboratory for Characterization of Devices – 31820

The goal.

The goal of this experiment is to measure the Current-Voltage (I-V) and Capacitance-Voltage (C-V)

characteristics of semiconductor diode (at room temperature and under heating conditions) and

extract from the measurements basic physical parameters / characteristics of the device. You will

use Keithley SCS 4200 measurement system and Agilent 4284A C-R-L analyzer.

The following parameters will be acquired from the I-V measurements:

Saturation current I sat

Parasitic series resistance R series

Parasitic shunt resistance R shunt

The following parameters will be acquired from the C-V measurements:

Built-in voltage of pn-junction,V 0

Doping densities N A and N D

Depletion layer width W and depletion layer widths x p ,xn on the p- and n-sides of the junction

Electric charges (per unit area) on the p- and n-sides of the junction, Q+¿¿ unit ¿area ¿

¿¿andQ− ¿¿unit ¿area ¿

¿¿.

Dr. Radu Florescu Dr. Vladislav Shteeman 2



Short theoretical background.Diode[] is a two-terminal electronic component that conducts electric current in one direction (from positive (p) to negative (n) terminal) and blocks it the opposite direction.

Semiconductor diodes (represented physically by a p-n junction) are most common type of contemporary diodes. They are widely used as a rectifiers, stabilitrons, voltage-dependent capacitors etc. Special modifications of semiconductor diodes are used as solar cells, photodiodes, light emitting diodes (LEDs) and laser diodes.

p-n junction consists of two regions (in a single semiconductor crystal) with opposite doping type

(Figure 1). The region on the left is p-type with an acceptor densityN A , while the region on the

right is n-type with a donor densityN D . The electrons (holes) density in the n-type (p-type) region

is approximately equal to the donor (acceptor) density (i.e. p0≈N A , n0≈N D ).

Figure 1. Sketch of p-n junction (after [12]).

I. Electrostatics of pn – junction.

1. pn – junction at zero-bias (applied voltage VD = 0) (after [ 5 ])

To reach the thermal equilibrium, electrons/holes close to the pn-junction diffuse across the junction into the p-type/n-type region where hardly any electrons/holes are present. This process leaves the ionized donors (acceptors) behind, creating a region around the junction, which is

depleted of mobile carriers. This region is called depletion region, extending from x=−x p 0 tox=xn 0 . The charge due to the ionized donors and acceptors creates built–in difference in

potentials between the two sides of the pn-junction, qV 0 (where V 0 is a built-in voltage). This built-

in potential qV 0 is also expressed by the existence of the built-in electric field, which in turn causes




a drift of carriers in the opposite directions. The diffusion of carriers continues until the drift current balances the diffusion current, thereby reaching thermal equilibrium (zero total current) as indicated by a constant Fermi energy. This situation is shown on Figure 2 and Figure 3:

Figure 2. Concentration of carriers, electric charge density, electric field and electric potential distribution in pn-junction at zero bias (after []).




Figure 3. Energy band diagram of a p-n junction at zero bias (after []).

The built-in voltage V 0 can be expressed in terms of concentrations of donorsN D , acceptorsN A

and intrinsic concentration ni :

V 0=kTqln

N A N D

ni2 |¿¿ at room temperature ¿T=300K ¿¿=0 .0256⋅ln

N A N D

ni2 [ V ]¿

(1)

(where k=8 .61733×10−5 [eV / K ] is Boltzmann constant, T [ K ] is a temperature and

q=1 .6×10−19 [C ] is an electron charge)

Typical value of V 0 for a standard Si diode (for N D≈1015 [cm−3] andN A≈1018 [cm−3 ] ): V 0≈0 .7 [ V ] .

Capacitance of a pn–junction at zero bias, C j 0 , originates mainly from the stationary ions

in the depletion region (i.e. from so-called junction capacitance C j at V D=0 ). It is expressed via

the total width of the depletion layer, W 0 , and the relative dielectric constant of the

semiconductor, ε r , as follows:




C j 0=ε0ε r

W 0⋅A

(2)

(where A is a cross-section area of the pn-junction and ε 0 is the vacuum permittivity)

2. Biased pn-junction (applied voltage VD ≠ 0).

Depending on the applied external voltage, V D , there are two modes of diode biasing: forward biased conducting mode and reverse biased non-conducting mode. Band diagrams of reverse- and forward- biased pn-junction are shown on Figure 4 and Figure 5.

Figure 4. Band diagram of a p-n junction under reverse bias (after [4]).




Figure 5. Band diagram of a p-n junction under reverse bias (after [4]).

Depletion layer width W. The total width of the depletion layer W =|x p|+|xn| for biased pn-junction is voltage-dependent.

Figure 6. Depletion layer in biased pn-junction.




W ={√ 2 εr ε0 (V 0−V D )q ( 1N D

+ 1N A ) (V D≥0)

√ 2 εr ε0 (V 0+|V D|)q ( 1N D

+1

N A ) (V D<0 )(3)

The width of the depletion layers on the p- and n- sides of the junction, x p and xn :

xn=W

1+N D

N A

, x p=W

1+N A

N D (4)

Capacitance of ideal biased pn – junction. A total capacitance of biased pn-junction is a sum of 2 different capacitances, connected in parallel, namely:

1. C j (junction capacitance) - capacitance of stationary ions in the depletion layer (negatively charged acceptor ions at the p-side vs positively charged donor ions at the n-side). This capacitance is dominant at the reverse

bias (V D<0 ) .

2. CS (stored or diffusion capacitance) - capacitance of mobile carriers (electrons at the p-side vs holes at the n-side), stored (as the result of diffusion) outside the depletion layer. This capacitance is dominant at the

forward bias (V D>0 )and not exists at the

reverse bias (V D<0 ) (since for V D<0 , there is no excess carriers outside the depletion layer).




Thus a total capacitance of diode is

C j for reverse bias (V D<0 )

C j+CS for forward bias (V D>0 )

For reverse bias, C j (and therefore a total capacitance of a diode) depends on V D as follows:

C j=A2 √( 2qεr ε0

(V 0−V D )N A N D

N A+N D )=ε r ε 0AW

(5)

(where A is a junction’ cross-section area)

At the forward bias, a total capacitance of diode is C j+CS , not C j , and therefore (with

increasing V D ) it rises faster than √1 (V 0−V D ) , as expected from Eq. (5). For this reason,

measured 1

C2(V D ) characteristics of a real diode experience drastic decrease for V D>0 (see ).

Figure 7. Measured total capacitance C (V D ) and C−2 (V D ) of 1N4007 diode.




Calculation of built-in voltage,V 0 from C-V measurements. From Eq. (5), 1/C j2is a linear

function of V D :

1C j2=

2qε 0ε semiconductor A2

N A+N D

N A N D(V 0−V D )

(6)

Figure 8. Sketch of a total capacitance C (V D ) and C−2 (V D ) for an ideal pn – junction (after [4]).

From the latter equation, for V D=V 0

1C j2→0

(i.e.C j→∞ ). This allows one to find the built-

in voltage V 0 from the C-V measurements, as shown on Figure 8. V 0 is obtained at the intersection

of the 1/C j2curve and V D axis.

Calculation of dopant concentrations N A andN D from C-V measurements. N A and

N D can be obtained from the slope of the graph 1/C j2 vs (V D ) (see e.g. Figure 8) and Eq. (1). The

slope

d (C j−2 (V D ))dV D is given by:




d (C j−2 (V D ))dV D

= 2qε 0εr A2

N A+N D

N A N D (7)

Therefore,

qε0 εr A2

2 ( d (C j−2 (V D ) )dV D

)=N A+ND

N A N D (8)

From Eq. (1), at the room temperature (i.e. kT /q=0 . 0256 [ V ] ), for the V 0 and intrinsic

concentration ni known, we get another expression for N A and N D :

ni2⋅exp( V 0

0 .0256 [ V ] )=N A⋅N D(9)

From Eq. (8) and Eq. (9) one can find the 2 unknowns, N A and N D .

Electric charge over the junction for reverse bias. The total electric charge over the junction (for reverse biase) is given by:

Figure 9. Sketch of a biased pn-junction and a static charge distribution over it.

|Q+|underbracealignl n− side ¿⏟charge ¿

=|qAxn N D|=|Q−|underbracealignl p−side ¿⏟charge ¿

¿=|−qAx p N A|¿(10)




where A is a junction’ cross-section area.

Electric charges per unit area on both sides of the junction are:

|Q+¿¿ unit ¿area ¿¿|underbracealignl n−side ¿⏟

charge ¿

=|qxn N D|=|Q−¿¿ unit ¿area ¿¿|underbracealignl p− side ¿⏟

charge ¿

¿=|−qx p N A|¿(11)

II. I-V characteristics of diode.

1. I-V characteristics of an ideal pn – junction.

Current via an ideal pn-junction obeys Shockley equation:

I D=I sat(e

V D

kTq−1)

(12)

where I sat is a saturation current, q=1 .6×10−19 [C ] is an electron charge, k is Boltzmann constant and T is temperature. Figure 10 shows a sketch of I-V characteristics of an ideal diode.




Figure 10: I-V characteristics of an ideal diode (after [6]).

Asymptotic behavior of Shockley equation.

Note that eα−1≈eα

for α≥5 and eα≈0 for α≤−5 . In our case, the condition α≥5

corresponds (at the room temperature, for kT

q≈0 . 026 [ V ]

) to the external voltageV D≥0 .13 [V ] ,

while α≤−5 corresponds to the V D≤−0.13 [ V ] . Therefore, for the forward biased junction withV D≥0 .13 [V ] ,

I D≈ I sat eV D

kT /q (V D ¿0 .13 [V ]) (13)

while for the reverse biased junction withV D≤−0.13 [V ]

I D≈−I sat (V D≤−0 .13 [V ]) (14)

In other words, for reverse biased ideal pn-junction, current I D quickly reaches its saturation value −I sat and remains constant for all the range of voltages V D≤−0.13 [ V ] . As opposite to the former, the forward bias, current increases exponentially all along; there is no current saturation.




Typical values of the saturation current are:

I sat=10

−9 [ A ] for silicon diodes

I sat=10

−6 [ A ] for germanium diodes.

2. Deviations of real diodes from Shockley model.

Deviations under forward bias. Parasitic series resistance R series .

When (at forward bias) V D reaches V 0 (i.e. V D=V 0 ), the potential barrier between p- and n- sides

of diode disappears: q (V 0−V D )=0 . Thus, I D cannot continue rise exponentially, as before (as in

Eq. (13)). In order to describe a slower rising of I D for V D≥V 0 , a model of parasitic series

resistance R series is introduced. (This is so-called “second-order” I-V analysis of diode, extending

ideal Shockley model to the case, where it is actually inapplicable (i.e. to V D≥V 0 ).) According to

the model, for V D≥V 0 a diode should suffer from a parasitic series resistanceR series (see Figure 11).

This resistance reduces the voltage drop over the junction from V D to V D−ID R series . Thus, Eq. (13) should be re-written as:

I D=I sat eV D− I D R series

kT /q(15)

Figure 11. Sketch of I-V characteristics of "ideal" and "real" pn – junction (after [7]).

Transformation of this equation gives:




lnI D

I sat=

V D

kT /q−

I D R series

kT /q(16)

This allows us to express R series as follows:

R series=− 1I D

( kTqln

ID

I sat−V D)

(17)

Thus, R series (according to the model) should be a linear function of V D .

Typical values of R series for Si diode are: R series≈5 − 50 [Ω ] .

Deviations under reverse bias. Parasitic shunt resistance R shunt .

Experimentally, at reverse bias, for V D<−0 . 13 [V ] , I D does not saturate to −I sat but rather continues to increase (in abs value, see Figure 12).

Figure 12. I-V characteristics of reverse-biased 1N4148 diode.




This increase is due to the generation current (drift current)I gen=

qAWni

2 τ g

(eqV D

2 kT −1) ,

originating from thermal generation of electron-hole pairs in the volume of depletion layer (where

A and W are cross-section of width of depletion layer of pn-junction, ni is intrinsic concentration

and τ g is a lifetime of electron-hole pair from thermal generation to recombination). In a good

approximation, |ID| increases linearly with V D (see e.g. I D (V D ) graph on Figure 12 for

−1<V D<0 .3 ).

One can modify Shockley model to account for I gen by introducing a parasitic shunt resistance

R shunt , connected in parallel to the ideal diode and assuming I gen=V D / Rshunt (see Figure 13).

For V D<−10 kT /q=−0 .26 [V ] , Shockley equation should be replaced with:

ID=−I sat−I gen=−I sat−qAWni

2 τ g=−I sat−|

V D

R shunt|

(18)

Figure 13. Explanation to the model of parasitic shunt resistance R shunt and saturation current I sat for reverse biased diode.

Note that R shunt is a single value, independent on V D .




Typical values of R shunt for a Si diode are: R shunt≈102−103 [ M Ω ] .

One can compute both the R shunt and I sat of a diode using trendline of the I D (V D ) curve in the

“deep” reverse bias region (say, in the range −1<V D<0 .3 ). Rshunt=

1slope of this trendline,

while I sat=| free term| (see Figure 13).

3. Diode response vs. temperature.

Diode performance is strongly affected by the temperature factor. Consider again the Shockley

model, I sat in Eq. (12) has a form:

I sat=qA ( D e( p)

L e( p) N A

+Dhole

(n)

Lhole(n) N D

)ni2

(19)

where: q is an electron charge, De(p )

and Dhole(n )

are the diffusion coefficients of the electrons on

the p-side and the holes on the n-side, Le(p )

and Lhole(n )

are the diffusion lengths of the electrons on

the p-side and the holes on the n-side, A is the pn-junction cross-section area, N A , N D are the

donors and acceptors concentrations and ni is the intrinsic concentration of Si.

For simplicity, assume, that De(p )

,Dhole(n )

, Le(p )

and Lhole(n )

are temperature independent. Nevertheless,

the current I sat in Eq. (19) does depend on the temperature, since ni is strongly dependent on the

temperature. It is possible to show, that I sat increases approximately for 7% for each temperature degree. Thus, for two different temperatures T1 and T2 holds:

I sat (T 2)≈I sat (T 1)×1.07T2−T1

(20)




Since 1 .0710=2 , there is a mnemonic rule, which says, that I sat doubles itself each 10 degrees:

I sat (T 2)=I sat (T 1)×2T2−T110

(21)

The higher the temperature, the faster grows the forward branch of the I-V characteristics and the larger the absolute value of the breakdown voltage at the reverse bias. Figure 14 illustrates the aforesaid.

Figure 14. Diode response vs. temperature.




Assignments and analysis.Part I. Room temperature measurements.

1. Acquire I-V measurements of diode using Keithley measurement system. (See Appendix 2 for details about pin connections and Keithley program parameters.)

2. Acquire C-V measurements of diode using Agilent R-C-L meter and Keithley measurement system. (See Appendix 3 for details about pin connections and Keithley program parameters.)

Note: after executing the measurements and before processing the acquired data, save this Excel template on your computer (double click on the Excel icon File Save as … ). Then close the Excel template and open the Excel file, saved recently. Copy the results of the measurements (located in the measurements folder of Keithley in the subdirectory “tests/data”) to the Excel template, saved on your computer.

Evaluation of physical parameters of diode from I-V measurements.

1. Shunt resistance R shunt : I-V characteristics of diode in the “deep”

reverse bias (e.g.0 . 5 [V ]<V D<2 [ V ] ) in a good approximation is a

straight line.

1slope of the trendline of section is R shunt :

R shunt=1

slope

2. Saturation current I sat : I D=−I sat−I gen=−I sat−|

V D

Rshunt|

Free term of the trendline of the section above is I sat :

I sat=| free term |




3. Series resistance R series : for forward bias region V D≥0 .2 [V ] , from the

graph ln (|I D

I sat|) vs V D

and Eq. (17), it is possible to find the range of V D , corresponding to the ideal diode (red line) and another range, corresponding to the diode with series resistance (blue line). It is also

possible to find the R series itself. To do this:

in Excel, fill in the column ln (|ID

I sat|)

make a graph ln (|I D

I sat|) vs V D

; on the graph, find (visually) the sections, corresponding to the red and to the blue lines.

add to the graph plot ln (|I D

I sat|) vs V D

for the “blue” range only. add to the graph trend line for the “blue” range points (with “show equation” and “show R

square” boxes marked) to get the linear equation coefficients. (Note that in our case

ln (|I D

I sat|)

is the “y” axis and V D is the “x” axis).

fill in a column, “R series ”, in the datasheet using Eq. (17)

make 2 additional plots: R series vs V D and R series vs I D .

Evaluation of physical parameters of the diode from C-V measurements.

Note: the items below refer to the model of uniformly doped pn-junction. Nevertheless, usually, this is not the case for real diodes. For one-sided hyperabrupt junction (e.g. p+n junction), see reference 8,

p.196 (double click to open ).

4. Built-in junction potential, V 0 . This potential should be obtained at

the intersection of the C j−2

curve and the horizontal axis (V D

voltage).

In order to get V 0 :

in Excel, build the graph C j−2 vs V D .

add to the graph trend line with the option “show equation” marked.




from the trend line equation, find V 0 (note that in our case 1/C j

2is the “y” axis andV D is the “x”

axis).

5. Dopants’ concentration N A andN D . If the slope

d (C j−2)

dV D , the built-in voltage V 0 , the intrinsic

carriers’ concentration ni and the cross section area of the pn- junction A are known ( see List

of symbols in Appendix 1 and Appendix 3 for details)) – one can find N A and N D by solving Eq. (8) and Eq. (9):

{qε0 εr A2

2 (|d (C j−2 )

dV D|)=N A+N D

N A ND¿¿¿¿

the built-in voltage V 0 and the slope

d (C j−2)

dV D were found on the previous step.

ε r and ni for the specific diode could be found elsewhere (see e.g. Appendix 1).

pn-junction’ cross-section area, A : for the 1N4148 Si diode, assume A=1mm2=0 .01cm2.

6. Depletion layer width W vs V D for the reverse bias (V D<0 ) . in Excel, compute (fill in the corresponding columns) depletion layer width W and depletion

layers width at the p- and n- sides (x p and xn ) for the reverse bias V D<0 (see Eq. (3) and Eq. (4) ).

in Excel, make on a single graph 3 plots: W vs V D , x p vs V D and xn vs V D .

7. Electric charge (per unit area) over the junction for the reverse bias (V D<0 ) . in Excel, compute (fill in the corresponding columns), using Eq. (11), electric charges per unit

area on both sides of the junction Q+¿¿ unit ¿area ¿

¿¿ and Q− ¿¿ unit ¿area ¿

¿¿ for reverse bias (V D<0 ) .

in Excel, make on a single graph 2 plots: Q+¿ ¿ unit ¿area ¿

¿ vs V D ¿ and Q− ¿¿ unit ¿area ¿

¿ vs V D ¿ .




Part II. Diode measurements under heating conditions.

For a room temperature and 4-5 other temperatures in a range of 40∘C−70∘C , acquire the I-V

measurements of the diode using the Keithley measurement system. (See Appendix 2 for details about the pin connections and the Keithley program parameters.)

Important: execute the 1st measurement (under room temperature) using the green button , and all the rest of the measurements (under heating conditions, for 4-6 different temperatures)

using the yellow-greed button (“append”). DO NOT use the green button for the measurements under heating conditions: it will override all your previous measurements.) After each measurement save the data in the Keithley program.

After finishing the measurements, you can automatically process the data using Matlab program. To do this:

1. Double-click on the zip-file “Diode heating processing.zip”. In the newly opened window, folder “Diode heating processing” will appear.

2. Drag this folder to the Desktop of your computer.

3. In the Keithley measurements folder (subfolder tests/data) find the files

connect_pin_agilent#[email protected] (C (V D ) ∧ C−2 (V D ) data), IU_forward#[email protected] (I D (V D )

measurements – forward bias data) & IU_backward#[email protected] ( I D (V D ) measurements – reverse bias data)




4. Copy the files connect_pin_agilent#[email protected], IU_forward#[email protected] & IU_backward#[email protected] to the folder “Diode heating processing.zip”:

5. Double-click on the file processed_data_DIODE_sf2.m in the directory “Diode heating processing”. This will start Matlab. Wait for 1-2 minutes to allow Matlab start.




6. Go to the Matlab Editor window and run the file processed_data_DIODE_sf2.m (press F5 or Debug Run on the Editor menu bar)

7. The program will ask you to input the temperatures, at which you measured the diode. Input the temperatures in the square parentheses with the spaces between the different values, e.g. [25 35 45 55 65]. Press Enter to continue.

8. Wait for approximately 1 minute, until the program will finish the processing of the measured data.

9. The results of the computations (Excel file processed_data.xls, Matlab files and figures) are located in the subfolder Results.




Final Report content.

Final Report must include the following diode parameters and graphs with explanations :

Part I – room temperature measurements:

[1] I−V characteristics of diode (2 graphs: I D (V D ) for forward and for reverse bias)

[2] C−V characteristics of diode (a single graph, includingC (V D ) ∧ C−2 (V D ) curves)

[3] ln ( I D/ I sat ) vs V D graph

[4] Shunt resistance R shunt (a single value)

[5] Saturation current I sat (a single value)

[6] Series resistance R series (2 graphs: R series vs V D and R series vs I D )

[7] Built-in voltage V 0 (a single value)

[8] Dopant concentrations N A and N D (two single values)

[9] Depletion layer width W and depletion layers widths at the n- and p-sides x p , xn

(a single graph)

[10] Electric charge per unit area Q± ¿¿ unit ¿area ¿

¿ vs V D ¿(a single value)

Part II – measurements under heating conditions:

[1] I−V characteristics of the diode (forward bias) for all the temperatures (on a single plot).

[2] I−V characteristics of the diode (reverse bias) for all the temperatures (on a single plot).




[3] The graph of the saturation current I sat as a function of temperature T, I sat (T ) .

[4] The graph of the parasitic shunt resistance Rshunt (T ) as a function of

temperature, Rshunt (T ) .

[5] The graph of the relative variation of the anode current versus anode voltage

(forward bias) ΔI = 100%×

I (T )−I (T room )I (T room ) for all the temperatures.

[6] The graph of the relative variation of the anode current versus anode voltage

(reverse bias) ΔI = 100%×

I (T )−I (T room )I (T room ) for all the temperatures.

[7] The graph of the total width of the depletion layer W 0 at zero bias as a function of temperature. (The

total width of the depletion layer W 0 can be evaluated from Eq. (2).)




Experimental set-up and samples to be studiedThe experimental setup includes Keithley matrix and Agilent L-C-R analyzer (Figure 17).

(a) For the room temperature measurements, you will use Test fixture probe station (Figure 15) (with dual

in-line package (18 pins) for diodes on Teaching chip No 3, or two-pins connection table for standard

stand-alone diodes), connected by the triax cables No 9,10,11,12 to the Keithley switching matrix.

(b) For the measurements under the heating conditions, you will use the temperature controlling oven

(Figure 16) connected by the triax cables No 5,6,7,8 to the Keithley switching matrix.

Table 1. Diode samples for available for study.

Test chip No 3 1N4148 diode 1N4001 diode

Appendix 3

datasheet


Keithley 708A Switching Matrix

Monitor

Figure 17. Keithley and Agilent L-C-R measurement setup.

Figure 15. Test fixture probe station.

Figure 16. Temperature controlling oven.

Agilent 4284A LCR meter

Keithley SCS

4200 I-V AND Param

eter analyz

er



AcknowledgementElectrical Engineering Department of Braude College would thank to Alexander Goldenberg, Vadim Goyhman, Adi Atias and Moran Efrony for their extensive help in preparation of this laboratory work.

Several parts of this guide were adapted from the pn-junction manual of the Advanced Semiconductor Devices Lab (83-435) of School of Engineering of Bar-Ilan University. We would like to thank Dr. Abraham Chelly for the granted manual.




Appendix 1 : List of symbols and definitions. List of symbols.

A - pn-junction’ cross-section area [cm2] (See Appendix 3 for the details about the cross-section area of different diodes on the Teaching chip No 3). For the 1N4148 Si diode assume A=1mm2=0 .01cm2

.

V 0 - built-in voltage [ V ] . ni - intrinsic carriers concentration [cm−3] . The following table presents ni

for the basic semiconductors at the room temperature (T = 300 K):

Si Ge GaAsni [cm− 3] 1 .5×1010 2 .4×1013 1 .79×106

p0 , n0 - holes (electrons) concentration in the quasi-neutral regions of p- and n- sides of pn-

junction [cm−3] .

N A , N D - acceptors (donors) concentration at the p- and n- sides of pn-junction [cm− 3] . R series - parasitic serial resistance [Ω ]; a voltage V D - controlled variable; usually ~5−50 [Ω ] .

R shunt - parasitic serial resistance [Ω ]; a voltage V D -independent constant; usually ~1 [ M Ω ] . ε r - relative dielectric constant of a semiconductor [dimensionless]. The following table

presents relative dielectric constants of the basic semiconductors: Si Ge GaAs

ε semiconductor 11.9 16 13.1

ε 0 - permittivity of vacuum. ε 0=8 .85×10

−14 [Fcm]=8 .85×10−12[F m]

C j - pn-junction capacitance, originating from the stationary ion charges in the depletion region [ F ]

C j 0 - C j at zero bias (V D=0 ) [ F ]

De(p )

and Dhole(n )

- diffusion coefficients of the electrons on the p-side and the holes on the n-side of the pn-junction.

I D - diode current [ A ] .

I gen - generation current [ A ] . Originates from thermal generation of electron-hole pairs in the

volume of depletion layer: I gen=

qAWni

τ g

I sat - saturation current [ A ] .




Le(p )

and Lhole(n )

- diffusion lengths of the electrons on the p-side and the holes on the n-side of

the pn-junction [ cm ] .

V D - voltage applied to pn-junction [ V ] . W - total depletion layer width [ cm ] .

W 0 - total depletion layer width at zero bias (V D=0 ) [ cm ] .

x p ,xn - depletion layers width in the p- and n- regions [ cm ] . W =|x p|+|xn|.

k=1.38×10−23 [Joule

deg .K ]=8 .617×10−5 [eVdeg .K ] - Boltzmann constant

T - temperature [deg. K]

q=1 .6×10−19 [C ] - electron charge.

EF , E i - Fermi and intrinsic Fermi level in semiconductor .

EF , p , EF , n - Fermi level on the p- (n-) side of the pn-junction.

EC ,EV - energy of the bottom of the conduction band and at the top of the valence band .

Q+ , Q− - electric charge (originating from the stationary ions in the depletion region) on the p-

and n- sides of the pn-junction [ C ] ; voltageV D -dependent.

Q+¿¿ unit ¿area ¿

¿ , Q−¿¿ unit ¿area ¿

¿¿ - total electric charge per unit area and electric charges per unit area on the p- and

n- sides of the pn- junction [C /cm2 ]

τ g - generation time. An average time between thermal generation and recombination of an electron-hole pair in the depletion layer.

List of definitions

n+ - high doping density of n-type (N D>1019 [cm−3 ] ).

p+ - high doping density of p-type (N A>1019 [cm−3] ).

Inversion - change of carrier type in a semiconductor obtained by applying an external voltage.

Inversion layer - the layer of free carriers of opposite type at the semiconductor interface (layer of electrons in p-type semiconductor and layer of holes in n-type semiconductor).




Appendix 2 : Kite settings for I-V and C-V measurements.

1.pin connection scheme:

2. I-V Keithley settings

Connect pins


SMU 1 (cable 9) SMU 2 (cable 10)I-V

measurements

LoPin (cable 12) HiPin (cable 11)C-V

measurements



Forward bias settings

Expected results – forward bias




Reverse bias settings

Expected results – reverse bias




3.C-V Keithley settings

Expected results – C-V measurements (10 kHz)


frequency 1kHz



Appendix 3 : Teaching chip No 3 diodes specifications Diodes’ details and pins Chip appearance




Bibliography.

1 Diode at wikipedia: http://en.wikipedia.org/wiki/Diode.

2 B. Streetman, S. Banerjee, “Solid state electronic devices” (6th edition), Prentice Hall, 2005.

3 К.В. Шалимова, «Физика полупроводников» (3е издание), Энергоатомиздат, 1985.

4 B. Van Zeghbroeck, “Principles of semiconductor devices”, Lectures – Colorado University, 2004.

5 A. Chelly, “pn-junction”, Lab manual - Advanced Semiconductor Devices Lab (83-435), School of Engineering of Bar-Ilan University.

6 J. Singh, “Semiconductor devices: basic principles”, Whiley, 2001.

7 A. del Alamo. “pn diode characterization” – project in the framework of course “Microelectronic Devices and Circuits” (6.012), MIT, 2003.

8 D. Neamen, “Semiconductor Physics and Devices: Basic Principles” (3rd edition), McGraw Hill, 2003.

9 S. Kasap, “pn-junction: the Shockley model”. An e-booklet (2001).

10 pn-junction Simulation using Java Applet: http://jas.eng.buffalo.edu/education/pn/iv/index.html

11 pn-junction properties calculator: http://www.ee.byu.edu/cleanroom/pn_junction.phtml

12 http://en.wikipedia.org/wiki/P%E2%80%93n_junction


2 mm

Silicon chip with PN junction

http://www.ee.byu.edu/cleanroom/pn_junction.phtml

http://jas.eng.buffalo.edu/education/pn/iv/index.html

http://en.wikipedia.org/wiki/Diode



Preparatory Questions1. Explain (in short) the principle of diode operation 2. Plot the qualitative graph of diode I-V characteristics3. Plot the qualitative graph of diode C-V characteristics4. How can you find from the I-V characteristics:

a. saturation current I sat

b. series resistance R series

5. How can you find from the C-V characteristics:

a. built-in voltage of the pn-junctionV 0

b. doping densities and

c. total depletion layer width W and depletion layer width x p ,xn on each side of the junction


AN DN

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