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The Implication of Synchronous Rectifiersto the Design of Isolated, Single-Ended

Forward ConvertersBy Christopher Bridge

ABSTRACT

Synchronous rectification is a commonly used technique to improve the efficiency of DC/DC converterswith low (<=5V) output voltages and high output currents. Control of the synchronous rectifiers inforward converters has been accomplished in many different ways, from self-driven to complexlycontrolled techniques. Most existing control techniques allow the synchronous rectifier’s body diode toconduct for some small time interval, thus degrading efficiency. The focus of this design review is a newcontrol technique that virtually eliminates body diode conduction in synchronous rectifiers.Measurement results from a 30W resonant reset forward converter will complement the paper.

I. INTRODUCTION

Forward converters have traditionally beenused for low output voltage DC/DC converters,particularly for the telecom input voltage rangeof 36 to 75V. The reasons behind this topologychoice are many and varied. The forwardconverter has only a single primary side switch,which is ground referenced, and severaltransformer reset methods are available. Thecontrol loop dynamics are well understood byextending the control models of standard buckconverters. Although the forward topology hasbeen quite popular, it has limitations. As theoutput voltage is decreased, the efficiency of theforward topology becomes limited by the outputrectifier’s loss. The rectifier loss, which isessentially the forward drop of the rectifier timesthe output load current, becomes the dominantloss in the converter in high current, low voltageapplications. Although there have been goodimprovements in Schottky diode technology,synchronous rectification is needed to realizehigher efficiency.

Manufacturers of power MOSFETs haveresponded by marketing very low on resistance,low voltage devices in compact packages.MOSFETs suitable for synchronous rectificationwith less than 3mΩ on resistance have been

reported[2]. As a result, the only major decisionthe designer is left with is how to control thesynchronous rectifiers.

II. FORWARD CONVERTER WITH DIODERECTIFICATION

A. Transformer Reset OptionsBefore discussing synchronous rectification,

it would be beneficial to look at the forwardconverter using conventional diode rectification.The basic power stage of a forward converterwith diode rectification is shown in Fig. 1.

RESET

+

VIN

+

VOUT

+VDSQ1

Q1

DR

DF

Fig. 1. Forward converter with diode rectification.

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(a) RESONANT RESET

(b) R-C-D CLAMP

(c) THIRD WINDING

Fig. 2. Possible reset mechanisms.There are several possible reset mechanisms,

as shown in Fig. 2. These are (a) Resonant Reset,(b) R-C-D Clamp, and (c) Third Winding.

While all of these techniques allow forresetting the transformer magnetizing currentduring the off time of the main switch Q1, themethod and the amplitude to which magnetizingcurrent is reset is different for each topology. Inthe Resonant Reset technique, the magnetizingcurrent is reset to negative amplitude through theresonant capacitance, which is primarily equal tothe COSS of Q1 added to the junction capacitanceof DF

[1]. This negative value is equal to one-halfthe peak-to-peak magnetizing current. The R-C-D clamp is very similar, except that it is theclamp voltage that drives the transformermagnetizing current negative.

Therefore, in the R-C-D clamp, themagnetizing current will cycle between negativeand positive peak values, which are notnecessarily equal to one half of the peak-to-peakmagnetizing current. In the traditional ThirdWinding Reset technique, the magnetizingcurrent is first reset to zero by the third winding,but resonance between the magnetizinginductance and the COSS of Q1 will drive themagnetizing current negative. This negativemagnetizing current will play an important rolewhen synchronous rectification is applied to theforward converter.

Waveforms that show the primary MOSFETQ1 drain-to-source voltage and the transformermagnetizing current for an R-C-D Clampforward converter are shown in Fig. 3.

VDRAIN

IM

Impk

Imng

t0 t1 t2 t3 t4 t5 t0

VI

0

0

VC

IMC

L

Fig. 3. Primary MOSFET Q1 drain-to-sourcevoltage and the transformer magnetizing currentfor an R-C-D clamp forward converter.

Two time intervals are of particular interest.First is the interval from t1 to t2, where thetransformer leakage inductance resonates withthe primary side capacitances and second, thedwell interval from t5 to t0.

At t1, the drain voltage on the primary sideMOSFET reaches the input voltage. At this time,the current on the secondary side is flowingthrough the forward diode DF and thetransformer has zero volts across both theprimary and secondary windings. Right after t1,the freewheeling diode DR starts to conduct somecurrent and the current in DF starts decreasing sothat the total current flowing in the two diodes is

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equal to the inductor current. As soon as DRbegins to conduct current, the transformersecondary is shorted by the conduction of bothdiodes. With the transformer secondary shorted,the magnetizing current is constant while thetotal transformer leakage inductance resonateswith the primary side capacitances. During thisresonance, the transformer primary currentdecreases from a peak value of the peakmagnetizing current plus the reflected inductorcurrent to the peak magnetizing current. Thesecondary current changes from the peakinductor current to basically zero current. Sincethe primary and secondary currents changeduring the resonance seen on the primary side,the current transfer from DF to DR is completeafter a half-resonant cycle is seen on the primaryside MOSFET drain voltage. At t2, the voltageacross DF starts to resonate, as DF is reversebiased. Put another way, the transfer of currentbetween the rectifiers is controlled by the totaltransformer leakage inductance and the primaryside capacitances. As seen by the secondary side,this adds a delay between the primary side gatedrive signal and the voltage across DFresonating.

The dwell time interval from t5 to t0 will bevery important when synchronous rectification isused in the forward converter topology. Asdescribed earlier, the transformer has negativemagnetizing current at this time, i.e. current isflowing out of the dotted terminal in Fig. 1.Recognizing that this current cannot flow on theprimary side, the magnetizing current must flowon the secondary side through DF. At t5, theprimary side switch drain voltage has resonateddown to the input line voltage, and is clamped bythe forward diode conducting the magnetizingcurrent. The forward diode conducts themagnetizing current throughout the dwell timeinterval, until the primary side MOSFET isswitched on at t0.

Experimental waveforms from[1] for theprimary side MOSFET drain voltage and thetransformer magnetizing current are shown inFig. 4. Fig. 5 shows both the transformer’sprimary and secondary currents as well as thedrain-to-source voltage of the primary sideMOSFET.

VDRAIN50V/div

ILM200mA/div

VI=48VIO=1.0A

200ns/div

Fig. 4. Primary MOSFET Q1 drain-to-sourcevoltage and transformer magnetizing current.

VDRAIN50V/div

IPRIMARY500mA/div

VI=30VIO=0.5A

200ns/div

ISECONDARY500mA/div

Fig. 5. Primary MOSFET Q1 drain-to-sourcevoltage and transformer primary and secondarycurrents.

B. Rectifier Reverse Recovery and ConductionLosses

Prior to Q1 being switched on, the inductorcurrent is flowing mostly through DR, which hasstored junction charge. Because this chargecannot be removed instantaneously, the anode-to-cathode voltage will remain constant as Q1 isswitched on. The input voltage is then placedacross the transformer leakage inductance andthe current in DR decreases at a rate determinedby the input voltage and leakage inductance.The input voltage magnitude and the transformer

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leakage inductance determine the dI/dt in DR andtherefore also determine the reverse recovery ofDR. After the stored charge is removed from DR,the transformer leakage inductance resonateswith the junction capacitance of DR.

The forward diode also experiences reverserecovery. This occurs at t2 in Fig. 3, immediatelyafter the current is commutated from DF to DR.As discussed earlier, the dI/dt in both DF and DRis set by the resonance between the transformerleakage inductance and the primary side resonantcapacitance. As the current is decaying to zero inthe forward diode DF, the dI/dt is decreasing inmagnitude, which makes the reverse recovery ofDF less severe than the reverse recovery of DR.Schottky diodes naturally have excellent reverserecovery characteristics, and when these are usedfor DF, the reverse recovery will be barelynoticeable; however, when MOSFETs are usedin place of DR and DF, the poor reverse recoverycharacteristics of the body diodes will becomeapparent.

III. SELF-DRIVEN SYNCHRONOUSRECTIFICATION

The self-driven drive scheme is the simplestsynchronous rectifier drive scheme and ispictured in Fig. 6.

The two diodes DF and DR are replaced withMOSFETs QF and QR. In the self-driventechnique, the voltage across the transformersecondary is used to drive the gates of thesynchronous rectifiers QR and QF. Although notshown in Fig. 6, separate windings on thesecondary side of the transformer can be used todrive the forward synchronous rectifier QF and/or the freewheeling synchronous rectifier QR

[3,4].This is usually done to allow a different turnsratio from the primary winding to the gate drivewinding(s), allowing synchronous rectification tobe used for higher or lower output voltages.

RESET

+

VIN

+

VOUT

+VDSQ1

Q1

QR

QF

Fig. 6. Forward converter with self-driven synchronous rectifiers.

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A. Implications and Trade-Offs of Self-DrivenSynchronous Rectification for Resonant ResetForward Converters.

Fig. 7 displays the waveforms for a resonantreset forward converter with self-drivensynchronous rectifiers operating in continuousconduction mode. Shown are the drain-to-sourcevoltages of QF and QR, as well as the primaryside MOSFET Q1 drain-to-source voltage.

0 V

0 V

0 V

VDSQ1

VDSQF = VGSQR

DWELLTIME

INTERVAL

0.7 V

0.7 V

VDSQR = VGSQF

Fig. 7. Typical waveforms for self-drivensynchronous forward converters with resonantreset.

The first problem with self-drivensynchronous rectification is the conductionintervals for the body diodes of QF and QR. In anoptimum converter, the resonant reset will occurduring the entire off-time of the primary sideMOSFET Q1, meaning that at low input line, theQ1 drain voltage will just return to the inputvoltage before Q1 is turned on again. At low line,the converter will be operating at the maximumsteady state duty cycle, DMAX, for the converter.Assuming that the converter is to be designedover a 2:1 input range, and that the duty cyclewill be inversely proportional to the input linevoltage, the steady state operating duty cycle athigh line will be 0.5 ·DMAX. In resonant resetconverters, the reset time interval does not

change over line variations, meaning that thedwell time interval will be 0.5 ·DMAX. It becomesclear then, even for converters operating at amaximum of 50% duty cycle that the dwell timeinterval will be as high as 25% of the entireswitching cycle.

Looking again at Fig. 7, during the dwelltime interval, the body diodes of both QF and QRare conducting. The forward MOSFET isconducting the reflected negative magnetizingcurrent, while the freewheeling MOSFET carriesthe difference of the inductor and the forwardMOSFET currents. Conduction of the QR bodydiode for this long time interval is veryundesirable as the losses will be high. Also, sincethe body diode is carrying a large current, thereverse recovery will be severe when the primaryside MOSFET Q1 is turned on. The forwardMOSFET will also experience conduction lossesduring the dwell time interval due to theconduction of the magnetizing current throughthe body diode. However, since the magnetizingcurrent is usually much smaller than the loadcurrent, this loss isn’t as high as in thefreewheeling switch.

A second problem with self-drivensynchronous rectification is the RDS(on) variationover the line voltage range. Low voltageMOSFETs suitable for self-driven synchronousrectification typically have an RDS(on) rated atVGS = 4.5V, and an absolute maximum VGS of±20V. The gate of the forward synchronousrectifier QF is driven with a voltage proportionalto the line voltage, while the freewheelingMOSFET gate is driven by a constant voltageduring the reset of the power transformer. Thedesigner must select a turns ratio NP/NS for themain power transformer low enough for theforward synchronous rectifier to be driven intoits ohmic region at low line. The design tradeoffoccurs at high line, where it is possible to exceedthe maximum gate-to-source rating of theforward synchronous rectifier MOSFET. For thestandard telecom input rage of 36 to 75V, areasonable choice for the turns ratio NP/NS isapproximately 6:1. At low line, this will giveapproximately 6V VGS on the forwardsynchronous rectifier that will increase toapproximately 12.5V at high line. A close

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examination of the MOSFET datasheet shows asignificant RDS(on) change over this VGS range.For some MOSFETs this change can be as highas 10%. If the transformer turns ratio NP/NS ishigher than 6:1, the RDS(on) variation will also behigher because the RDS(on) increase significantlyat gate-to-source voltages less than 6V.

In self-driven synchronous rectification, thegates of the synchronous rectifiers are drivendirectly from the transformer. The current to turnthe rectifiers on and off comes efficiently fromthe input line. The average current to drive theforward synchronous rectifier will varyproportionally to the switching frequency andproportionally to the gate-to-source voltage.

Therefore, over a 2:1 line voltage change, theaverage current required to drive the forwardsynchronous rectifiers will also change 2:1.Since the freewheeling synchronous rectifier isdriven with a constant gate-to-source voltage, thecharge and average current required is constantover the line voltage.

Another drawback of using self-drivensynchronous rectifiers in place of dioderectification is the loading of the resonant resetcircuit. Fig. 8a shows the capacitances of theresonant circuit, and Fig. 8b shows theequivalent resonant capacitances and inductancesreflected to the primary side.

+

VIN

+

VOUT

+

COSSQ1

COSSQF

LM

CGSQR

QRCXMFR

VDSQF

(a)

COSSQF

N2

CGSQR

N2 CXMFR

LM

LLK

Q1

NP/NS

COSS

+

VDSQ1

(b)

RP

Fig. 8. Capacitances of the resonant circuit (a) and equivalent resonant capacitances and inductancereflected to the primary side (b).

7-7

During the reset time interval, the VDS of QFhas a resonant half-sine wave voltage on it. It canbe seen that the gate-to-source capacitance of QRand the COSS of QF will load the resonant resetcircuit. The net effect of this loading is to extendthe time duration of the reset time interval,assuming the transformer magnetizinginductance is kept constant. If the duty cycleneeds to be kept constant after adding the self-driven synchronous rectifiers, the magnetizinginductance may have to be decreased, which willresult in a shorter reset time, and a higher peakreset voltage. Decreasing the magnetizinginductance will also increase the circulatinglosses, as more energy will be stored in thetransformer.

IV. CONTROL-DRIVEN SYNCHRONOUSRECTIFICATION

After examining the self-driven technique,attention turns to control-driven synchronousrectification. Control-driven techniques aregenerally more complex than self-driven;however, control-driven techniques canovercome all the limitations of self-driventechniques. Body diode conduction can beeliminated and using precise timing circuitry canminimize reverse recovery losses. Furthermore,the gate drive voltage can be set to an optimumlevel to minimize RDS(on) while minimizing thegate charge required. The gate drive voltage canbe regulated independent of the line voltage. Allof these benefits come with the cost of addedcontrol complexity.

Knowing the limitations of self-drivensynchronous rectification, begin by drawing thedesired waveforms for the synchronous rectifiergates with respect to the available controlsignals. Fig. 9 shows the two synchronousrectifier gate-to-source voltages, drain-to-sourcevoltages, as well as the primary side drain-to-source voltage and PWM CONTROL signals.

Note that the PWM CONTROL signal couldbe either primary or secondary side referenced, itmakes no difference to the waveforms in Fig. 9.

PWMCONTROL

Q1 VGS

VGS QR

VGS QF

VDS QF

VDS QR

Fig. 9. Control-driven synchronous rectificationwaveforms.

Why not drive the forward synchronousrectifier QF with the PWM CONTROL signal,and the freewheeling synchronous rectifier QRwith an inverted PWM CONTROL signal? Theanswer lies first in the time delay between thePWM CONTROL signal and changes in thepower stage voltages and currents. When thePWM CONTROL signal originates on thesecondary side, it is too far time advanced fromchanges in the power stage voltage and currents.However, if the PWM CONTROL signal isprimary side referenced, it must be broughtacross the isolation boundary. Depending onhow the PWM CONTROL is transmitted fromthe primary to the secondary side, the resultingsignal on the secondary side may be too far timeadvanced or time retarded. Also, as describedpreviously, it would be desirable to allow bothsynchronous rectifier channels to conduct duringthe dwell time interval. Unfortunately thisrequires overlapping gate drive signals. The timeinterval when both rectifiers are conducting willvary with line voltage and any changes inparasitic capacitances and inductances. Possiblythe optimal solution then, is to use power stageinformation to determine when the forwardsynchronous rectifier should be turned on.Examining Fig. 9 closely, QF should be turnedon exactly when its drain-to-source voltagereaches zero volts. This would allow the

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magnetizing current to be conducted by thechannel instead of the body diode, eliminatingthe conduction loss of the body diode. If QF isturned on at this time, it will remain on when theprimary side MOSFET Q1 is turned on, and theturn off of QF will need to be synchronized to theturn off of Q1.

Control of QR needs to be synchronized tothe rectified transformer voltage. As soon as thetransformer voltage that is rectified by QF falls tozero volts, QR needs to be turned on. Ideally, thegate-to-source voltage of QR would beapproaching its threshold voltage as the drain-to-source voltage of QR is falling to zero. Thiswould allow for minimum body diodeconduction of QR during this time interval. Theturn off of QR is a very different situation. In theself-driven technique, the channel of QR is turnedoff as the resonant voltage across the drain-to-source of QF falls below the threshold voltage ofQR. The current that was flowing through thechannel of QR now must flow through the bodydiode, and when Q1 is turned on, a high lossreverse recovery will take place. With control-driven synchronous rectification, the goal is tominimize this body diode conduction by activelycontrolling the turn off of QR.

V. CONTROL-DRIVEN IMPLEMENTATION

To minimize conduction and reverserecovery losses, the synchronous rectifiersrequire precise timing circuitry. Although thereare several ways to generate these controlsignals, a feedback system to actively control thetiming of the gate drive signals will be used. Thekey advantages are that the circuit will adjust forcomponent variation, particularly theuncontrolled capacitances in the synchronousrectifier MOSFETs, and timing delays and thetemperature dependence of MOSFET thresholdsare also corrected for by this feedback loop.

To control the gate timing, the programmabledelay block pictured in Fig. 10 will be used. Thisdelay block is comprised of three main elements;a delay line, a multiplexer (MUX), and a logicAND gate. An input signal to the delay line isdelayed several nanoseconds for each delayelement. In order to generate a controlled turn-ondelay, the MUX selects which delay element to

take the output signal from. Finally, the ANDgate ensures that the delay is applied to the turn-on (rising) edge only. Control of the delay fromIN to OUT is performed by the digital controlbus applied to the MUX address input. If thecontrol bus is set to all ones, a maximum delay isseen from IN to OUT. Conversely, if the controlbus is set to all zeros, there is practically nodelay from IN to OUT. Several different delayblocks can be constructed, giving either a turn-ondelay only, a turn-off delay only or symmetricturn-on and turn-off delays. Not shown in Fig. 10is a voltage sensing circuit and digital controller.For different implementations of the delay cell,different voltage sensing circuits and digitalcontrollers will be used.

IN

DELAY LINE WITH 2n ELEMENTS

OUTDELAY BUS

2n

MUX2n

n

CONTROL BUS

IN

OUTtDELAY

Fig. 10. Delay block.

A. Control-Driven QR ImplementationThe control-driven circuit design starts with

the freewheeling MOSFET QR, which should beturned on as soon as its drain-to-source voltagefalls to zero. One simple way to accomplish thiswould be to use a comparator to sense when thedrain-to-source voltage of QR crosses zero volts.The problem with this method arises when thedelay through the comparator, logic, and gatedriver are considered. Even with very fastcircuitry, this delay can amount to 50ns or more,during which the body diode is conducting andincurring high conduction losses. One logicalanswer to the inherent time delay from sensingthe falling drain-to-source voltage to when theMOSFET is turned on is to use information fromthe last switching cycle to predict when to turnon the MOSFET. In this anticipatory way, the

7-9

MOSFET gate voltage can start increasingbefore the drain-to-source voltage has fallen. Bytiming the gate voltage to rise to the MOSFETthreshold voltage when the drain-to-sourcevoltage is falling to zero volts, the body diodeshould never conduct.

Fig. 11 shows the control circuitry to turn QRon and off. It uses two multiplexers, twocounters, one delay line and glue logic to controlthe turn-on and turn-off so that body diodeconduction is minimized. The circuit descriptionwill begin with the turn-on delay portion. ThePWM CONTROL signal drives the primary sideMOSFET Q1 and is also fed into the delay line.When the power supply is first started, theLOAD input to the counters is high which setsthe turn-on delay counter to all ones, and sets theturn-off delay counter to all zeros. With thecounters initialized in this state, the output fromthe control circuit to the gate driver results in

maximum turn-on delay and minimum turn-offdelay. With the delays set to these values, thebody diode of QR will conduct, and the feedbackloops will start to adjust the delays to minimizeits conduction. Fig. 12 (a) and (b) shows thegate-to-source and drain-to-source voltages ofQR during the turn-on of QR. Fig. 12 (a) showsthe circuit operation when the turn-on of QR isdelayed too long, and Fig. 12 (b) shows optimaltiming delay.

To adjust the turn-on delay, a NOR gate withan approximate input threshold of 2V is used todetect when the gate-to-source voltage and drain-to-source voltage of QR are both simultaneouslylow. A high output from the NOR gate indicatesto the controller that the delay was too long, andthe controller will decrease the delay for the nextswitching cycle.

PWM CONTROL

PWM CONTROL

INPUTFROMCONTROL

VGS_QR

VDS_QR

GND

2V THRESHOLD

DFF

D Q

QCLKR

S

SET1

DFF

D Q

QCLKR

S

SET1

INPUTSFROMPOWERSTAGE

VDS_QR

+

–300 mVGND

BODY DIODECOMPARATOR

UP/ DN

CLK

LOAD SETS Q = 1

Q [3:0]

Q [15:0]

IN

DELAY LINE

TURN-OFFDELAY MUX

TURN-ON COUNTER

LOAD

PWM CONTROL

UP/ DN

CLK

LOAD SETS Q = 0

Q [3:0]

TURN-OFF COUNTER

LOAD

PWM CONTROL

PWM CONTROL

TURN-ONDELAY MUX

QR_CONT

TO GATEDRIVER

PWM CONTROL

Fig. 11. QR control circuitry.

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0 V

2 V

(a) NON-OPTIMAL

0 V

2 V

(b) OPTIMAL

VDSQR

NOR GATE OUTPUT

VGSQR

V

V

t

t

Fig. 12. QR turn-on waveforms.The NOR gate output is latched, inverted,

and is fed into the turn-on delay counter’sUP/DOWN input. This signal tells the counter toeither count up or count down. If the NOR gate’soutput was high, then the counter will countdown, decreasing the delay, while a low NORoutput will result in the counter counting up,increasing the delay. The counter effectivelyholds this delay information for the next cycle.The feedback loop will then adjust the turn-ondelay to be shorter until the NOR gate no longerhas an output pulse. When the converter isoperating at a constant load and line, the turn-ondelay for the next cycle will be slightly too long,the NOR gate will give a high output pulse, andthe delay will be shortened. In this way, thecircuit dithers the delay between two values, onetoo long, and one very close to optimum.

The turn-off controller operates in a verysimilar manner to the turn-on controller. Thedifferences reside in the voltage sensing circuitand the direction that the counter counts. A highspeed comparator is used to sense when the bodydiode is conducting. For improved accuracy, acomparator is used to detect body diodeconduction instead of the NOR gate. During theturn-on interval, current is commutating from theforward synchronous rectifier to thefreewheeling synchronous rectifier. The dI/dt of

this current is quite high, and ringing is usuallyseen on the drain-to-source voltage of QR. If acomparator is used for detecting the body diodeconduction during the turn-on of QR, there couldbe false triggering due to the ringing drain-to-source voltage. During the turn-off of QR, thecurrent is constant through the QR MOSFETdevice, as the current is flowing through eitherthe channel or the body diode. There is very littleringing during the turn-off, and a comparator isused for improved accuracy. The threshold of thecomparator must be slightly negative to preventfalse triggering of the comparator when theMOSFET channel is conducting.

The drain-to-source voltage during channelconduction is approximately equal to-ILOAD·RDS(on), and allotting for noise, thecomparator threshold is set to approximately-300mV. The comparator compares the drain-to-source voltage of QR to this fixed threshold and ahigh output from the comparator indicates to thecontroller that the body diode is conducting andthe delay needs to be increased. This is exactlyopposite from the turn-on scenario, because theturn-off delay counter is set to all zeros at start-up. Fig. 13 (a) and (b) show the turn-offwaveforms for QR and the comparator output.

VDSQR

COMPARATOR OUTPUT

VGSQR

(a) NON-OPTIMAL

(b) OPTIMAL

0 V

-0.3V

V

V

t

t

Fig. 13. QR turn-off waveforms.Fig. 13 (a) shows the circuit operation when

the delay is set too short, and Fig. 13 (b) shows

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optimal timing delay. As in the turn-on of QR,the delay for the turn-off dithers between a valuethat is too long and an optimum value.

The question arises: can the turn-on or turn-off delays be set too short, causing cross-conduction? The answer lies in a careful study ofthe comparator performance and the delay perelement of the delay line. Comparators can onlyrespond to differential input voltages that arepresent for a sufficient amount of time to slewinternal nodes. Suppose the comparator candetect body diode conduction for 5ns. During thenext cycle, the delay is adjusted to reduce thediode conduction by one bit on the delay line. Ofcourse, the comparator will not respond to thenext-cycle body-diode conduction because it willbe approximately 5ns minus the delay time perelement on the delay line. The key to avoidingcross conduction is to set the delay per elementless than the minimum detectable pulse width ofthe comparator.

B. Control-Driven QF ImplementationControl of the forward synchronous rectifier

QF is quite different than the freewheelingsynchronous rectifier QR. One main difference isthat the goal is to turn on QF after thetransformer is reset, which is independent ofeither the rising or falling edge of the PWMCONTROL signal. This is unlike thefreewheeling synchronous rectifier, where thegoal was to simply adjust the timing of both therising and falling edges of the PWM CONTROLsignal as needed to minimize body diodeconduction in QR

With the understanding that the goal is toturn on QF after the transformer is reset, a goodstarting point is the circuitry required to turn onQF as shown in Fig. 14.

First, a high-speed body diode comparator isused to detect when the body diode of QF startsto conduct, which signals the end of thetransformer reset time interval. Unfortunately, asshown in Fig. 15, this comparator will also detectbody diode conduction right after the primaryside MOSFET Q1 is turned off.

PWM_CONTROL

PWM_CONTROL

INPUTFROMCONTROL

VGS_QF

VDS_QR

GND

DFF

D Q

QCLKR

S

LOAD

PWM_CONTROL

SET1

DFF

D Q

QCLKR

SSET1

+

INPUTSFROMPOWERSTAGE

VDS_QF

2.5 V

GND

PRE-CONDITION LATCH

LOAD

+

300 mVGND

HIGH-SPEED BODY DIODECOMPARATOR

LOW SPEEDCOMPARATOR

DFF

D Q

QCLKR

SSET0

LOAD

LOAD

QF_CONT

TO GATEDRIVER

UP/ DN

CLK

LOAD SETS Q = 0

Q [3:0]

Q [15:0]

IN

DELAY LINE

TURN-OFF DELAY MUX

MUX_OUTPUTTURN-OFF COUNTER

LOAD

PWM_CONTROL

QF CONTROL LATCH

2V THRESHOLDS

MUX_OUTPUT

Fig. 14. QF control circuitry.

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VDS QF

2.5 VCOMP OUTPUT

HIGH SPEEDBODY DIODE

COMP OUTPUT

PRECONDITIONLATCH Q

Fig. 15. QF pre-condition latch waveforms.Using the comparator alone would turn on QF

for the entire off time of Q1, and the transformerwould never be allowed to reset. To avoid this, alow speed comparator is used to detect when thedrain-to-source voltage of QF has risen above2.5V. When the drain-to-source voltage of QFhas risen above 2.5V, a pre-condition latch is set,which then enables the output of the high-speedbody diode comparator. As soon as the drain-to-source voltage of QF falls past the –300mVthreshold of the body diode comparator, QF isturned on by setting the QF control latch. Assoon as the high-speed comparator output goeshigh, the pre-conditioning latch is reset, and theturn-on circuitry is in the proper state for the nextturn-on event. During the inherent delay from thebody diode comparator detecting the conductionof the body diode, to the channel of QF turningon, the body diode conducts the magnetizingcurrent of the transformer. Although during thistime interval there is conduction loss in the QFbody diode, this is minimal compared to the lossincurred if QF was held off for the entire dwelltime period. To eliminate this loss completely,one would have to use the same predictivecontrol that was used for the turn-on of QR.Although this is possible in theory, it is quitedifficult because there is no PWM CONTROLedge present when the transformer hascompletely reset.

The control for the turn-off of QF is quitesimilar to the turn-on of QR. The turn-off circuituses the predictive control technique, using adelay line, multiplexer and a counter as thecontroller. The differences between the controlof the turn-off of QF and the turn-on of QR startwith the type of logic gate used for the feedbackloop. As shown in Fig. 14, the gate-to-sourcevoltage of QF is inverted and fed into a 2-inputAND gate. The other input to the AND gate isconnected to the drain-to-source voltage of QR.Both the inverter and the AND gate haveapproximately 2V input thresholds. This ANDgate will synchronize the falling edge of QF’sgate-to-source voltage with the falling edge ofQR’s drain-to-source voltage.

VDSQR

AND OUTPUT

VGSQF

(a)

2 V

2 V

VDSQR

AND OUTPUT

VGSQF

0 V

0 V

(b)

2 V

2 V

0 V

0 V

V

V

t

t

Fig. 16. QF turn-off waveforms.

7-13

A counter that has its output initially set toall zeros controls the turn-off circuit. With thecounter’s output set to all zeros, virtually zerodelay is set between the falling edge of the PWMCONTROL signal and the gate-to-source voltageof QF. The resulting gate-to-source voltage ofQF, drain-to-source voltage of QR and the ANDgate output are shown in Fig. 16 (a).

The AND gate in the QF turn-off circuit actsmuch like the NOR gate did in the QR turn-oncontrol circuit, giving a command to the counterthat directs the counter to count up or down. Inthe case of the QF turn-off circuit, a high outputfrom the AND gate directs the counter to countup at the next clock cycle. When the counterincrements up one count value for the next cycle,the delay between falling edge of the PWMCONTROL and the gate-to-source voltage of QFis increased, and the output pulse from the ANDgate will be narrower. This feedback effect willcontinue until the gate-to-source of QF and thedrain-to-source of QR are synchronized. Whenthe delay is optimum, the waveforms are asshown in Fig. 16 (b).

As described in the QR controlimplementation, the circuit will dither betweentwo delay values, one that is optimum and oneslightly longer than optimum.

VI. PROTOTYPE CIRCUIT

A prototype converter was constructed toverify the theoretical predictions. The testedconverter operates from a 36V to 75V input lineand converts this input to a 2.5V output at up to12A. The converter’s block diagram is shown inFig. 17.

The operating frequency is fixed at 500kHzby a secondary side voltage mode controller. TheResonant Reset method is used to reset thepower transformer. The breadboard is designedso that both self-driven synchronous rectificationand the control-driven techniques can beinvestigated.

A block diagram of the secondary sidecontrol circuitry is shown in Fig. 18.

The signals from the power stage are shownon the left; these are level shifted down to 0V to3.3V signals for the logic. The power stagesignals are input into Altera MAX7000Aelectrically programmable logic devices (EPLD),which contain all the control logic for thesynchronous rectifiers. This allows for maximumflexibility when developing the logic to processthe power stage signals and to output the desiredgate drive signals. To level shift between the 0 to3.3V logic signals and the 8V gate drive rail,high-speed 4 transistor level shifters are used.TPS2812 8-pin IC gate drivers were used withboth drivers in each package paralleled forhigher output current drive.

+

VIN

PRIMARYCONTROL

SECONDARY SIDE CONTROL

3300 pF 1.6

3300 pF

1.6

1.2 H

2.5 V12 A

VDSQF VGSQF VGSQR VGSQR

PULSE P8205T PAYTON 9225

QR2xFDS6670A

Q1IRF630S

16

2xFDS6680

+

PULSEPA0115

Fig. 17. Simplified prototype schematic.

7-14

DELAY LINE ANDLOGIC FOR QF

(FIGURE 14)

DELAY LINE ANDLOGIC FOR QR

(FIGURE 11)

3.3 V TO 8 VLEVEL SHIFTER

TPS2812DRIVER

3.3 V TO 8 VLEVEL SHIFTER

TPS2812DRIVER

VGSQF

PWMCONTROL

VDSQF

VGSQR

LOAD

VDSQR

Fig. 18. Secondary side control block diagram.

To minimize the RDS(on) of the synchronousrectifiers, while reducing the gate chargerequired, an 8V power rail is used for the gatedrivers. The outputs of the gate drivers were alsolevel shifted down and input back into the logicdevices. No gate drive resistors were used foreither synchronous rectifier.

The three counters required for both the QRand QF control circuits are 4 bits wide, whichresults in a delay line with 16 elements. Thesedelay lines are implemented with 16 bit busdrivers, part number 74AHC16244, with allsixteen drivers connected in series. The outputsfrom the 16 drivers are fed into the EPLDs thatcontain the multiplexers and all other logic.Since the delay lines are CMOS integratedcircuits, the delay per element of the delay linecan be adjusted by simply changing the supplyvoltage. For this circuit, setting the supplyvoltage to the delay line IC to approximately2.7V set the delay per element to approximately4ns. Using 4ns per delay line element is atradeoff between dynamic range, meaning themaximum delay that can be commanded, theclosed loop accuracy of the feedback loop, andthe incremental power loss.

VII. MEASUREMENT RESULTS

A. WaveformsFig. 19 shows the primary MOSFET drain-

to-source voltage and the PWM CONTROLsignal. The control signal is taken before theprimary side gate driver. Note the inherent delaybetween the rising edge of the PWM CONTROL

signal and the falling edge of the drain-to sourcevoltage of Q1. Likewise, the delay for the turn-off of Q1 is significant and not the same as theturn-on delay.

500 ns / div

VDSQ1 20 V / div

PWM CONTROL 5 V / div

Fig. 19. Resonant reset waveforms.Waveforms for self-driven synchronous

rectification are shown in Fig. 20. Thesewaveforms were taken at an input voltage of 48Vand a load current of 3A. Note the delay from thePWM CONTROL signal to the drain-to-sourcevoltages of QF and QR. During the dwell timeinterval, the body diode conduction of QF and QRis clearly visible. Since these waveforms weretaken at 48V, the dwell time interval is a small

7-15

portion of the PWM period. At high line of 75V,the dwell time extends considerably, increasingthe losses in both QR and QF.

The waveforms for control-driven synch-ronous rectification are shown in Fig. 21. Fromthe top to the bottom are the drain-to-source ofQR, drain-to-source of QF, gate-to-source of QF,and gate-to-source of QR. Both gates arecontrolled with the predictive delay circuitrydescribed in this paper. A couple of interestingpoints can be observed. First, the gate-to-sourcevoltage of QF has a resonant voltage presentduring the off time of QF. This is due to theresonant drain-to-source voltage on QF couplingthrough the gate-to-drain capacitance of QF.Theresulting voltage seen on the gate is due to theresonant current through the driver’s pull downresistance. The gate drive waveforms have thenecessary overlap to minimize the loss when QFconducts the transformer magnetizing currentduring the dwell period.

VDSQF 5 V / div

PWM CONTROL 5 V / div

VDSQR 5 V / div

500 ns / div

Fig. 20. Self-driven synchronous rectificationwaveforms.

VDSQR 5 V / div

VGSQR 10 V / div

VDSQF 5 V / div

VGSQF 10 V / div500 ns / div

Fig. 21. Control-driven synchronousrectification waveforms.

VDSQR 5 V / div

VGSQF 2 V / div

VGSQR 2 V / div

20 ns / div

Fig. 22.QR turn-on waveforms.

7-16

Notice the magnified waveforms at eachsynchronous rectifier turn-on and turn-offtransition, starting with QR. In Fig. 22, the drain-to-source voltage of QR as well as the gate-to-source voltage of both QR and QF is shown. Asthe drain-to-source voltage of QR falls, QF isbeing turned off, and QR is being turned on. Thetiming for the turn-on of QR and the turn-off ofQF is being actively controlled by the feedbackloops. Note that minimal body diode conductionexists on the drain-to-source voltage of QR.

The turn-off waveforms for QR are shown inFig. 23. During the turn-off of QR, the high-speed comparator senses body diode conductionand the feedback loop adjusts the gate timing toeliminate this conduction. The drain-to-sourcevoltage waveform shows virtually no body diodeconduction whatsoever. This waveform shows anoptimum turn-off of QR.

The turn-on waveforms for QF are shown inFig. 24. The turn-on of QF is controlled withoutusing the predictive delay circuit, so body diodeconduction is expected due to propagationdelays. A high-speed comparator detects QF’sbody diode conduction and turns on the gate.The resulting body diode conduction interval isseen to be approximately 50ns.

VDSQR 5 V / div

VGSQR 2 V / div

20 ns / div

Fig. 23. QR turn-off waveforms.

VGSQF 2 V / div

VDSQF 5 V / div

50 ns / div

Fig. 24. QF turn-on waveforms.

VGSQF 2 V / div

VDSQF 2 V / div

VGSQR 5 V / div

20 ns / div

Fig. 25. QF turn-off waveforms.

7-17

The turn-off waveforms for QF are shown inFig. 25. The predictive delay circuit shown inFig. 14 controls the turn-off of QF to minimizethe body diode conduction. Note that there isminimal body diode conduction seen on thedrain-to-source voltage of QF.

B. EfficiencyA major goal of this topic is to compare the

efficiency of the two control methods, self-driven and control-driven. It becomes clear thatthere is a third possibility, where control-driventechniques are used for QR, and the self-driventechnique is used for QF. This “hybrid” controlscheme has merits of simpler control whichwould use less circuitry, as well as the gatecharge for QF would be recycled to the loadinstead of dissipated in the driver. Thedrawbacks to this hybrid control technique arethe body diode conduction loss of QF during thedwell period, which in some applications may beoffset by the recycled gate charge of QF. Theefficiency of all three control techniques will beexplored over line and load variation.

First, the setup for measuring efficiency iscritical to drawing conclusions from theefficiency data. For the purposes of this paper,the principal concern is power stage efficiency,including the synchronous rectifier gate drivepower. For this reason, the primary bias and gatedrive current are ignored and not included in theefficiency calculations. Therefore, for the self-driven technique, the efficiency is measured byonly including the power stage input current,while for both the hybrid and control-driventechnique the 8V synchronous rectifier gate-drive bias current was included. Of course, the8V bias current for the hybrid control is lowerthan the control-driven technique since only thefreewheeling MOSFETs are driven. For theseefficiency measurements, a lab power supply isused for the synchronous rectifier gate drivepower supply. It is assumed that a suitable biassupply can be derived off the output choke ormain power transformer in most applications.

Fig. 26 shows the measured efficiency over a2A to 12A load range for the three controltechniques, all at the nominal 48V input.

2 4 6 8 10

78

1274

82

90

86

CONTROL-DRIVENHYBRIDSELF-DRIVEN

EF

FIC

IEN

CY

(%

)

LOAD (A)

Fig. 26. Efficiency vs. load current.As might be predicted, the highest to lowest

efficiency tracks the most sophisticated to leastsophisticated control technique respectively. Thecontrol-driven technique has the highestefficiency, which peaks at 88.8% at 10A loadcurrent and at full load is measured at arespectable 88.3%. The hybrid control techniquealso has excellent efficiency, measured at 88.5%at 10A load decreasing to 88.0% at 12A load.The efficiency difference is due to the bodydiode conduction of QF during the dwell period.The change in dissipated power between thecontrol-driven and hybrid techniques is 400mWat full load. It needs to be recognized that themajority of this power is dissipated in the QFMOSFET, which only serves to increase thetemperature rise and adversely affects reliability.

Interestingly, the self-driven efficiency atlight load is measured to be higher than either thecontrol-driven or hybrid techniques. This can beexplained by two effects, the recycling of gatecharge to the output and to the resonant tankcircuit. The synchronous rectifier gate chargepower is roughly independent of line and load,which adversely affects efficiency at light loads.Since the self-driven technique recycles thischarge, the light load efficiency is higher thanthe control-driven and hybrid techniques.

7-18

Secondly, the forward body diode drop in thesynchronous rectifiers is lower at light loadcurrents, resulting in lower conduction losses.Clearly, the recycled gate charge is offsetting theadditional body diode loss at these light loads.

Efficiency over a 2:1 line voltage changewith a fixed output current of 10A is shown inFig. 27.

36 42 48 54 60 66

82

7280

86

84

90

88

CONTROL-DRIVENHYBRIDSELF-DRIVEN

EF

FIC

IEN

CY

(%

)

LINE (V)

Fig. 27. Efficiency vs. input line voltage.It is important to realize that the dwell time

interval is critical to the efficiency as the linevoltage is changed. The losses in the self-driventechnique will increase significantly as the linevoltage is increased, as the body diode of QR willconduct for a longer time period every switchingcycle. As the line voltage is increased with thehybrid control technique, the body diode of QRwill not conduct, but the body diode of QF willconduct for a longer time period every switchingperiod during the dwell period. For the control-driven technique, no change in losses due tobody diode conduction over line voltagevariation is expected. All of these predictions aresupported with the data. We can see that theefficiency is highest at low line for all threetechniques. Switching losses, which increase asthe line voltage is increased, are the dominantreason the efficiency decreases as the linevoltage is increased. The hybrid efficiency isalmost identical to the control-driven efficiencyat low line, but the efficiency dropsapproximately 0.8% at high line due to the

conduction of the QF body diode. This efficiencychange represents a loss of 500mW at 72V lineand 10A load current. As stated previously, thisadditional power loss is concentrated in the QFMOSFET.

VIII. CONCLUSIONS

The control-driven synchronous rectificationtechnique can deliver the highest efficiency ofthe three techniques considered in this paper.However, to obtain this efficiency, precise gatetiming is required for the synchronous rectifiers.A unique predictive control technique thatautomatically adjusts the gate timing for thesynchronous rectifiers was developed andpresented. This new control circuitry maximizesthe efficiency of the forward converter withcontrol-driven synchronous rectification. TexasInstruments has filed for patent protection for theentire content of this topic, including the controltechniques for both synchronous rectifiers. Twoproducts are in development that use thetechniques described in this topic. An 8 pinsynchronous buck driver IC for high currentDC/DC applications is under development withthe part number UCC37222. The UCC37223, asecondary side synchronous rectifier driver IC isalso in development.

REFERENCES

[1] Christopher D. Bridge, “Clamp VoltageAnalysis for RCD Forward Converters”,APEC 2000.

[2] STMicroelectronics Datasheet Part No.STV160NF03L.

[3] Philips Technical Note “25 Watt DC/DCConverter Using Integrated PlanerMagnetics”.

[4] Ionel Dan Jitaru, “High-EfficiencyRectification Techniques for Low OutputVoltage and High Output VoltageApplications”, APEC Professional Seminar,1999.

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