the intel microprocessors chapter 1

7/25/2019 The Intel Microprocessors Chapter 1

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Chapter 1: Introduction to the

Microprocessor and Computer


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Copyright 2009 by Pearson Education, Inc.pper !add"e #i$er, %e& 'ersey 0()*+ -"" rights reser$ed.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition

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Introduction /$er$ie& o Inte" microprocessors.

iscussion o history o computers.

unction o the microprocessor.

3erms and 4argon 5computer).


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Chapter 1 Introduction to the

Microprocessor and Computer

161 - 7istorica" ac8ground 162 3he Microprocessor6ased Persona"

Computer !ystem

16 %umber !ystems

16) Computer ata ormats

16* !ummary

16 ;uestions and Prob"ems


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Chapter Objectives

Con$erse by using appropriate computertermino"ogysuch as bit, byte, data, rea"

memory system, protected mode memory

system,


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Chapter Objectives

ra& the b"oc8 diagram o a computer systemand e?p"ain the purpose o each b"oc8.

escribe the unction o the microprocessor

and detai" its basic operation. eine the contents o the memory system in

the persona" computer.

Upon completion of this chapter, you will be able to:

5cont(@


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Chapter Objectives

Con$ert bet&een binary, decima", andhe?adecima" numbers.

ierentiate and represent numeric and

a"phabetic inormation as integers, "oating6point, C, and -!CII data.

Upon completion of this chapter, you will be able to:

5cont(@


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The Intel Microprocessors:8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions

%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition

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11 ! "I#$O%IC!& '!C(%OU*+ E$ents "eading to de$e"opment o

the microprocessor.

+0>+, Pentium, Pentium Pro, Pentium III,

Pentium ), and Core2microprocessors.


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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions


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$he echanical !-e Idea o computing system not ne&.

Ca"cu"ating &ith a machine dates to *00 C.

-ncient peop"e in$ented the abacus.

A irst mechanica" ca"cu"ator

A strings o beads perorm ca"cu"ations

sed by ancient priests to 8eep trac8 o

storehouses o grain.

A sti"" in use today


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In 1)2 mathematician "aise Pasca"

in$ented a ca"cu"ator constructed o gears

and &hee"s.A each gear contained 10 teeth


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irst practica" geared mechanica" machines

to compute inormation date to ear"y 1+00s.

A humans dreamed o mechanica" machines thatcou"d compute &ith a program

/ne ear"y pioneer o mechanica" computing

machinery &as Char"es abbage.A aided by -da yron, Countess o Bo$e"ace

Commissioned in 1+2 by #oya" -stronomica"

!ociety to bui"d programmab"e ca"cu"atingmachine.

A to generate #oya" %a$y na$igationa" tab"es


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7e began to create his !nalytical n-ine.

!team6po&ered mechanica" computer.

A stored a thousand 206digit decima" numbers ariab"e program cou"d modiy unction o the

machine to perorm $arious ca"cu"ating tas8s.

A input through punched cards, much as computersin the 19*0s and 190s used punched cards

It is assumed idea o punched cardsis rom

'oseph 'acDuard, a renchman.A used punched cards as input to a &ea$ing

machine he in$ented in 1+01


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)ac*uard+s loom used punched cards to se"ect

intricate &ea$ing patterns in c"oth it produced.

A punched cards programmed the "oom -ter many years o &or8 abbages dream

began to ade.

A machinists o his day unab"e to create the partsneeded to comp"ete his &or8

-na"ytica" EnginereDuired more than *0,000

machined parts.

A they cou"d not be made &ith enough precision to

a""o& his engine to unction re"iab"y


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$he lectrical !-e 1+00s sa& ad$ent o the e"ectric motor.

A concei$ed by Michae" araday

-"so a mu"titude o e"ectrica""y motor6dri$en

adding machines based on the Pasca"

mechanica" ca"cu"ator.A common oice eDuipment unti" 19(0s

Introduced by omar Corporation the 'omar

'rain, &as a handhe"d e"ectronic ca"cu"ator.A irst appeared in ear"y 19(0s


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Monroe a"so pioneer o e"ectronic ca"cu"ators,

ma8ing des8top mode"s.

A our6unctionF siGe o cash registers In 1++9, 7erman 7o""erith de$e"oped the

punched card or storing data.

A apparent"y a"so borro&ed 'acDuard ideas -"so de$e"oped mechanica" machine that

counted, sorted, and co""ated inormation

stored on punched cards.A dri$en by one o the ne& e"ectric motors


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Ca"cu"ating by machine intrigued ! go$t.

A 7o""erith commissioned to use system to store

and tabu"ate 1+90 census inormation In 1+9 7o""erith ormed 3abu"ating Machine

Company.

A de$e"oped "ine o machines using punched cardsor tabu"ation

-ter a number o mergers, 3abu"ating

Machine Co. &as ormed into Internationa"

usiness Machines Corporation.

A reerred to more common"y as IM, Inc.


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Punched cards used in ear"y computer

systems oten ca""ed "ollerith cards.

A in honor o 7erman 7o""erith 126bit code used on a punched card is ca""ed

the "ollerith code.


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Mechanica"6e"ectric machines dominated

inormation processing &or"d unti" 19)1.

A construction o irst e"ectronic ca"cu"ating machine Herman in$entor onrad Juse, in$ented the

irst modern e"ectromechanica" computer.

7is J ca"cu"ating computer probab"yin$ented or aircrat and missi"e design.

A during


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/i-ure 11 3he J computer de$e"oped by onrad Juse uses a *. hertG c"oc8ing

reDuency. 5Photo courtesy o 7orst Juse, the son o onrad.@


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7ad Juse been gi$en adeDuate unding,"i8e"y &ou"d ha$e de$e"oped a much more

po&eru" computer system. In 19 Juse constructed a mechanica"$ersion o his system.

In 199 constructed irst e"ectromechanica"computer system, ca""ed the J2.

A Juse today recei$ing be"ated honors orpioneering &or8 in the area o digita" e"ectronics


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irst e"ectronic computer p"aced in operationto brea8 secret Herman mi"itary codes.

recent"y disco$ered through dec"assiicationo mi"itary documents o 19).

!ystem in$ented by -"an 3uring.

A used $acuum tubes,

3uring ca""ed his machine Colossus 0hu-estatue).

A probab"y because o its siGe


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-"though design a""o&ed it to brea8 secretHerman mi"itary codes generated by themechanica"

ni-ma machine, it cou"d not

so"$e other prob"ems.

Co"ossus not programmab"e

- i?ed6program computer system

A today oten ca""ed a specialpurpose computer

irst genera"6purpose, programmab"ee"ectronic computer system de$e"oped 19).

A at ni$ersity o Pennsy"$ania


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lectronic *umerical Inte-rator andCalculator5*I!C), a huge machine.

A o$er 1(,000 $acuum tubesF *00 mi"es o &iresA &eighed o$er 0 tons

A about 100,000 operations per second

Programmed by re&iring its circuits.

A process too8 many &or8ers se$era" days

A &or8ers changed e"ectrica" connections on p"ug6boards "i8e ear"y te"ephone s&itchboards

#eDuired reDuent maintenance.A $acuum tube ser$ice "ie a prob"em


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ecember 2, 19)(, 'ohn ardeen,


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Inte" engineers ederico aggin, 3ed 7o,and !tan MaGor de$e"oped the )00)microprocessor.

.!. Patent ,+21,(1*.

e$ice started the microprocessor re$o"utioncontinued today at an e$er6acce"erating pace.


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2ro-rammin- !dvancements

/nce programmab"e machinesde$e"oped,

programs and programming "anguages began toappear.

-s ear"y practice o re&iring circuits pro$ed too

cumbersome, computer "anguages began toappear in order to contro" the computer.

3he irst, machine lan-ua-e, &as constructed o

ones and Geros using binary codes.

A stored in the computer memory system as groups o

instructions ca""ed a program


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The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,



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More eicient than re&iring a machine to

program it.

A sti"" time6consuming to de$e"op a program dueto sheer number o program codes reDuired

Mathematician 'ohn $on %eumann irst

modern person to de$e"op a system to acceptinstructions and store them in memory.

Computers are oten ca""ed von *eumann

machinesin his honor.

A reca"" that abbage a"so had de$e"oped the

concept "ong beore $on %eumann


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/nce systems such as %I-C became

a$ai"ab"e in ear"y 19*0s, assembly lan-ua-e

&as used to simp"iy entering binary code. -ssemb"er a""o&s programmer to use

mnemonic codesK

A such as-or addition In p"ace o a binary number.

A such as 0100 0111

-ssemb"y "anguage an aidto programming.


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Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 ith 64!"it #$tensions%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Edition

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19*(Hrace 7opper de$e"oped irst high6"e$e"

programming "anguageca""ed /&O3!$IC.

A computers became easier to program In same year, IM de$e"oped /#3#-%

/O%mula $%!*slator@ or its systems.

A-""o&ed programmers to de$e"op programs thatused ormu"as to so"$e mathematica" prob"ems.

/#3#-% is sti"" used by some scientistsor

computer programming.A !imi"ar "anguage, -BH/B 5!&Orithmic&an-ua-e@ introduced about a year "ater


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irst successu", &idespread programming

"anguage or business app"ications&as

C//B 5COmputer 'usiness Oriented&an-ua-e@.

C//B usage diminished in recent years.

A sti"" a p"ayer in some "arge business andgo$ernment systems

-nother once6popu"ar business "anguage is

#PH 5%eport 2ro-ram enerator@.

A a""o&s programming by speciying orm o the

input, output, and ca"cu"ations


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!ince ear"y days o programming, additiona"

"anguages ha$e appeared.

!ome common modern programming"anguages are -!IC, CL, C=C, 'a$a,

P-!C-B, and --.

A -!IC and P-!C-B "anguages both designed asteaching "anguages, but escaped the c"assroom.

-!IC used in many computer systems.

Aamong most common "anguages today

A probab"y easiest o a"" to "earn


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Estimates indicate -!IC used or +0No

programs &ritten by persona" computer users.

isua" -!IC, has made programming in the


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!cientiic community uses primari"y C=C.

A occasiona""y P-!C-B and /#3#-%

#ecent sur$ey o embedded systemde$e"opers sho&ed C&as used by 0N.

A 0Nused assemb"y "anguage

A remainder used -!IC and '-- 3hese "anguages a""o& programmer a"most

comp"ete contro" o$er the programming

en$ironment and computer system.A especia""y C=C


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C=C rep"acing some "o&6"e$e" machine

contro" sot&are or dri$ers norma""y reser$ed

or assemb"y "anguage. -ssemb"y "anguage sti"" p"ays important ro"e.

A many $ideo games &ritten a"most e?c"usi$e"y

in assemb"y "anguage -ssemb"y a"so interspersed &ith C=C to

perorm machine contro" unctions eicient"y.

Asome ne&er para""e" instructions ound onPentium and Core2 microprocessors on"y

programmab"e in assemb"y "anguage


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-- used hea$i"y by epartment o eense.

3he -- "anguage &as named in honor o

-ugusta -da yron, Countess o Bo$e"ace. 3he Countess &or8ed &ith Char"es abbage

in the ear"y 1+00s.

A de$e"opment o sot&are or -na"ytica" Engine


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$he icroprocessor !-e


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abricated &ith then6current state6o6the6art

P6channe" M/!E3 techno"ogy.

E?ecuted instructions at *0 IPs 54iloinstructions per second@.

A s"o& compared to 100,000 instructions per

second by 06ton E%I-C computer in 19) ierence &as that )00) &eighed "ess than

an ounce.

)6bit microprocessor debuted in ear"y gamesystemsand sma"" contro" systems.

A ear"y shu"eboard game produced by ai"ey


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Main prob"ems &ith ear"y microprocessor &ere

speed, &ord &idth, and memory siGe.

E$o"ution o )6bit microprocessor ended &henInte" re"eased the )0)0, an updated )00).

A operated at a higher speedF "ac8ed impro$ements

in &ord &idth and memory siGe

3e?as Instruments and others a"so produced )6

bit microprocessors.

A sti"" sur$i$es in "o&6end app"ications such as

micro&a$e o$ens and sma"" contro" systems

A Ca"cu"ators sti"" based on )6bit C 5binarycoded

decimal@ codes


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!ome&hat sma"" memory siGe, s"o& speed,

and instruction set "imited +00+ useu"ness.

Inte" introduced +0+0 microprocessor in 19(.A irst o the modem +6bit microprocessors

Motoro"a Corporation introduced MC+00

microprocessor about si? months "ater. +0+0Oand, to a "esser degree, the MC+00

Oushered in the age o the microprocessor.

A other companies soon introduced their o&n$ersions o the +6bit microprocessor

$able 11 Ear"y +6bit microprocessors


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$able 1 1 Ear"y + bit microprocessors


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/n"y Inte" and Motoro"a continue to createne&, impro$ed microprocessors.

A IM a"so produces Motoro"a6sty"emicroprocessors

Motoro"a so"d its microprocessor di$ision.

A no& ca""ed reesca"e !emiconductors, Inc.

Ji"og sti"" manuactures microprocessors.

A microcontro""ers and embedded contro""ersinstead o genera"6purpose microprocessors

Wh t W S i l b t th 8080?


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What Was Special about the 8080?

+0+0 addressed our times more memory.

A ) bytes $s " bytes or +00+

E?ecuted additiona" instructionsF 10? aster.

A addition ta8ing 20 s on an +00+6based system

reDuired on"y 2.0 s on an +0+06based system

33B 5transistor6transistor "ogic@ compatib"e.

A the +00+ &as not direct"y compatib"e

Interacing made easier and "ess e?pensi$e.


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3he MI3! -"tair ++00, &as re"eased in 19().

A number ++00 probab"y chosen to a$oid copyright

$io"ations &ith Inte" -!IC "anguage interpreter or the -"tair ++00

computer de$e"oped in 19(*.

Ai"" Hates and Pau" -""en, ounders o MicrosotCorporation

3he assemb"er program or the -"tair ++00

&as &ritten by igita" #esearch Corporation.

A once produced #6/! or the persona"

computer

Th 8085 Mi


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The 8085 Microprocessor

In 19(( Inte" Corporation introduced an

updated $ersion o the +0+0Othe +0+*. Bast +6bit, genera"6purpose microprocessor

de$e"oped by Inte".

!"ight"y more ad$anced than +0+0F e?ecutedsot&are at an e$en higher speed.

A (9,20 instructions per second $s *00,000 per

second on the +0+0@.


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Main ad$antages o +0+* &ere its interna"

c"oc8 generator and system contro""er, and

higher c"oc8 reDuency.A higher "e$e" o component integration reducedthe +0+*s cost and increased its useu"ness

Inte" has so"d o$er 100 mi""iono the +0+*.

A its most successu" +6bit, genera"6purpose

microprocessor.

A a"so manuactured by many other companies,

meaning o$er 200 mi""ion in e?istence -pp"ications that contain the +0+* &i"" "i8e"y

continue to be popu"ar.


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Ji"og Corporation so"d *00 mi""ion o their

+6bit J+0microprocessors.

3he J6+0 is machine "anguageAcompatib"e&ith the +0+*.

/$er (00 mi""ion microprocessors e?ecute

+0+*=J6+0 compatib"e code.

$he odern icroprocessor


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$he odern icroprocessor

In 19(+ Inte" re"eased the +0+F a year or so "ater,

it re"eased the +0++. oth de$ices are 16bitmicroprocessors.

A e?ecuted instructions in as "itt"e as )00 ns52.*

millions of instructions per second@

A ma4or impro$ement o$er e?ecution speed o +0+*

+0+ Q +0++ addressed 1M byte o memory.

A 1 times more memory than the +0+*

A 1byte memorycontains 102) byte6siGed memory

"ocations or 1,0)+,*( bytes

7i h d d " i "" d


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7igher speedand "arger memory siGea""o&ed

+0+ Q +0++ to rep"acesma""er

minicomputers in many app"ications. -nother eature &as a )6or 6byte instruction

cacheor Dueuethat preetchedinstructions

beore they &ere e?ecuted.A Dueue sped operation o many seDuences oinstruction

A basis or the much "arger instruction caches

ound in modem microprocessors.

I d i d dditi "


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Increased memory siGe and additiona"

instructions in +0+=+0++ "ed to many

sophisticated app"ications. Impro$ements to the instruction set inc"uded

mu"tip"y and di$ide instructions.

A missing on ear"ier microprocessors %umber o instructions increased.

A rom )* on the )00), to 2)on the +0+*

A o$er 20,000$ariationson the +0+ Q +0++

3h i "" d CI!C


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3hese microprocessors are ca""ed CI!C

5comple5 instruction set computers@.

A additiona" instructions eased tas8 o de$e"opingeicient and sophisticated app"ications

16bit microprocessor a"so pro$ided more

interna" register storage space.

A additiona" registers a""o&ed sot&are to be

&ritten more eicient"y

A e$o"$ed to meetneed or "arger memory systems

P " it I t " d i 19+1 h IM


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Popu"arity o Inte" ensured in 19+1 &hen IM

chose the +0++ in its persona" computer.

!preadsheets, &ord processors, spe""ingchec8ers, and computer6based thesauruses

&ere memory6intensi$e.

A reDuired more than ) bytes o memory oundin +6bit microprocessors to e?ecute eicient"y

A 3he 16bit +0+ and +0++ pro$ided 1M byte o

memory or these app"ications



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E$en the 1M6byte memory system pro$ed "imiting

or databases and other app"ications.A Inte" introduced the +02+ in 19+

A an updated +0+

-"most identica" to the +0+=+0++.A addressed 1M6byte memory system instead

o a 1M6byte system

Instruction set a"most identica" e?cept or a e&

additiona" instructions.A managed the e?tra 1*M bytes o memory

+02+ " 8 d i d i + 0 Mh


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+02+ c"oc8 speed increased in +.0 MhG

$ersion.

A e?ecuted some instructions in as "itt"e as 2*0 ns5).0 MIPs@

!ome changes to interna" e?ecution o

instructions "ed to eighto"dincrease in speed

or many instructions.

The 32 Bit Microprocessor


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The 32-Bit Microprocessor

-pp"ications demanded aster microprocessor

speeds, more memory, and &ider data paths. Bed to the +0+in 19+by Inte".

A ma4or o$erhau" o 16bit +0+A+02+ architecture

Inte"s irst practica" microprocessor to containa 26bit data busand 26bit memory address.

A Inte" produced an ear"ier, unsuccessu" 26bit

microprocessor ca""ed iap?6)2

3h h 2 bit b +0+ dd d


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3hrough 26bit buses, +0+ addressed up

to )H bytes o memory.

A 1memory R 102)M, or 1,0(,()1,+2) "ocationsA 1,000,000 type&ritten, doub"e6spaced pages o

-!CII te?t data

+0+!>addressed 1M bytes o memory

through a 16bit dataand 2)6bit address bus.

+0+!B=+0+!BC addressed 2M bytes

memory $ia 16bit data, 2*6bit address bus.

+0+!BC contained an interna" cache to

process data at e$en higher rates.

I t " " d +0+E> i 199*


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Inte" re"eased +0+E>in 199*.

Ca""ed an embedded 2C.

A contains a"" components o the -3 c"asscomputer on a sing"e integrated circuit

2) "ines or input=output data.

26bit address busF 16bit data bus. #-M reresh contro""er.

Programmab"e chip se"ection "ogic

-pp"ications needing higher speeds and "arge


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-pp"ications needing higher speeds and "arge

memory systems inc"ude sot&are systems

that use a HI, or -raphical user interface Modern graphica" disp"ays contain 2*,000

or more picture e"ements 5pi?e"s, or pe"s@.

H- 5variable -raphics array@ reso"ution is)0 pi?e"sper scanning "ine by )+0 "ines.

A reso"ution used to disp"ay computer boot screen

3o disp"ay one screen o inormation, eachpicture e"ement must be changed.

A reDuires a high6speed microprocessor

HI pac8ages reDuire high microprocessor


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HI pac8ages reDuire high microprocessor

speeds and acce"erated $ideo adapters or

Duic8 and eicient manipu"ation o $ideo te?tand graphica" data.

A the most stri8ing system is Microsot


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26bit microprocessor needed due to siGe o

its data bus.

A transers rea" 5sing"e6precision "oating6point@numbers that reDuire 26bit6&ide memory

3o process 26bit rea" numbers, the

microprocessor must eicient"y pass them

bet&een itse" and memory.

A &ith +6bit data bus, ta8es our read or &rite cyc"es

A on"y one read or &rite cyc"e is reDuired or 2 bit

!igniicant"y increases speedo any program

that manipu"ates rea" numbers.

7igh "e$e" "anguages spreadsheets and


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7igh6"e$e" "anguages, spreadsheets, and

database management systems use rea"

numbers or data storage.A a"so used in graphica" design pac8ages that use$ectors to p"ot images on the $ideo screen

A C- 5computeraided draftin-6desi-n@

systems as -3/C-, /#C-

+0+ had higher c"oc8ing speeds and

inc"uded a memory management unit.

A a""o&ed memory resources to be a""ocatedand managed by the operating system

+0+ inc"uded hard&are circuitry or memory


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+0+ inc"uded hard&are circuitry or memory

managementand assignment.

A impro$ed eiciency, reduced sot&are o$erheadA ear"ier microprocessors "et memory

management comp"ete"y to the sot&are

Instruction set, memory management up&ard6

compatib"e&ith +0+, +0++, and +02+.

A additiona" instructions reerenced 26bit registers

and managed the memory system

eatures a""o&ed o"der, 16bit sot&are tooperate on the +0+ microprocessor.



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In 19+9 Inte" re"eased the +0)+.

7igh"y integrated pac8age.

1. +0+6"i8e microprocessor.

2. +0+(6"i8e numeric coprocessor.

. +6byte cache memory system.

Interna" structure o +0)+ modiied so about


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Interna" structure o +0)+ modiied so about

ha" o its instructions e?ecuted in one c"oc8

instead o t&o c"oc8s.A in a *0 M7G $ersion, about ha" o instructionse?ecuted in 2* ns 5*0 MIPs@

A *0N o$er +0+ operated at same c"oc8 speed

oub"e6c"oc8ed +0)+>2 e?ecuted

instructions at M7G, &ith memory transers

at M7G.

A ca""ed a doub"e6c"oc8ed microprocessor

- trip"e c"oc8ed $ersion impro$ed speed to


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- trip"e6c"oc8ed $ersion impro$ed speed to

100 M7G&ith memory transers at M7G.

A about the same speed as 0 M7G Pentium. E?panded 16byte cache.

A in p"ace o standard +6byte cache

-d$anced Micro e$ices 5-M@ produced atrip"e6c"oc8ed $ersion &ith a bus speed o )0

M7G and a c"oc8 speed o 120 M7G.

3he uture promises rates 10 H7Gor higher.

/ther $ersions ca""ed /$erri$e processors


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arry . rey

/ther $ersions ca""ed /$erri$eprocessors.

A a doub"e6c"oc8ed+0)+> that rep"aced an

+0)+!> or s"o&er6speed +0)+>

A unctioned as a doub"ed6c"oc8ed $ersion o the

microprocessor

The Pentium Microprocessor


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arry . rey

The Pentium Microprocessor

Introduced 199, Pentium &as simi"ar to

+0+ and +0)+ microprocessors. /rigina""y "abe"ed the P* or +0*+.

A Inte" decided not to use a number because it

appeared to be impossib"e to copyright a number Introductory $ersions operated &ith a c"oc8ing

reDuency o 0 M7G Q M7G, and a speed

o 110 MIPs.

oub"e6c"oc8ed Pentium at 120 M7G and 1


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arry . rey

oub"e6c"oc8ed Pentium at 120 M7G and 1

M7G, a"so a$ai"ab"e.

A astest $ersion produced 2 M7G Pentiuma three and one6ha" c"oc8ed $ersion

Cache siGe &as increased to 1 bytes rom

the + cache ound in +0)+.

+6byte instruction cache and data cache.

Memory system up to )H bytes.

ata bus&idth increased to a u"" ) bits. ata bus transer speed 0 M7G or M7G.

A depending on the $ersion o the Pentium


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#ecent Pentium $ersions a"so inc"uded

additiona" instructions.

A mu"timedia e?tensions, or MM>instructions Inte" hoped MM> &ou"d be &ide"y used

A e& sot&are companies ha$e used

A no high6"e$e" "anguage support or instructions /$erri$e 5P2)3@ or o"der +0)+ systems.

M7G $ersion upgrades +0)+>2 *0 M7G

systemsF + M7G upgrades M7G systems.A system perorms some&here bet&een a M7G

Pentium and a (* M7G Pentium

Pentium /$erri$e represents idea" upgrade


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arry . rey

Pentium /$erri$e represents idea" upgrade

path rom the +0)+ to the Pentium.

A e?ecutes t&o instructionsnot dependent on eachother, simu"taneous"y per c"oc8ing period

A dua" integer processors most ingenious eature

A contains t&o independentinterna" integer

processors ca""ed supersca"er techno"ogy

'ump predictionspeeds e?ecution o program

"oopsF interna" "oating6point coprocessor

hand"es "oating6point data. 3hese portend continued success or Inte".

Inte" may a""o& Pentium to rep"ace some


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arry . rey

Inte" may a""o& Pentium to rep"ace some

#I!C5reduced instruction set computer@

machines. !ome ne&er #I!C processors e?ecute more

than one instruction per c"oc8.

A through supersca"er techno"ogy

Motoro"a, -pp"e, and IM produce Po&erPC,

a #I!C &ith t&o integer units and a "oating6

point unit.

A boosts Macintosh perormance, but s"o& to

eicient"y emu"ate Inte" microprocessors

Current"y mi""ion -pp"e Macintosh systems


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arry . rey

Current"y mi""ion-pp"e Macintosh systems

20 mi""ion persona" computers based on Inte"

microprocessors. 199+ reports sho&ed 9No a"" PCs shipped

&ith the


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arry . rey

3o compare speeds o microprocessors, Inte"

de$ised the iC/MP6 rating inde?.

A composite o !PEC92, J ench, Po&er Meter 3he iC/MP1 rating inde?is used to rate the

speed o a"" Inte" microprocessors through the

Pentium.

igure 1A2 sho&s re"ati$e speeds o the

+0+> 2* M7G $ersion through the

Pentium 2 M7G $ersion.

/i-ure 17 3he Inte" iC/MP6rating inde?.


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arry . rey

!ince re"ease o Pentium Pro and Pentium II,


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arry . rey

!ince re"ease o Pentium Pro and Pentium II,Inte" has s&itchedto the iC/MP26 rating.

A sca"ed by a actor o 10rom the iC/MP1 inde?

igure 1A sho&s iC/MP2inde? "isting thePentium III at speeds up to 1000 M7G.

igure 1A) sho&s !S!mar8 2002 or the

Pentium III and Pentium ).

Inte" has not re"eased benchmar8sthatcompare $ersions o the microprocessor

since the !S!mar8 2002.A ne&er a$ai"ab"e do not compare $ersions

/i-ure 18 3he Inte" iC/MP26rating inde?.


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arry . rey

/i-ure 19 Inte" microprocessor perormance using !S!mar8

2002


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arry . rey

2002.

Pentium Pro Processor


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arry . rey

- recent entry, ormer"y named the P.

21 mi""ion transistors, integer units, "oating6point unit, c"oc8 reDuency 1*0 and 1 M7G

Interna" 1 "e$e"6one 5B1@ cache.

A + data, + or instructionsA Pentium Pro contains 2* "e$e"6t&o 5B2@ cache

Pentium Pro uses three e?ecution engines, to

e?ecute up to three instructions at a time.A can con"ict and sti"" e?ecute in para""e"

Pentium Pro optimiGed to eicient"y e?ecute


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arry . rey

Pentium Pro optimiGed to eicient"y e?ecute

26bit code.

Aoten bund"ed &ith


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Microprocessors

Pentium II, re"eased 199(, represents ne&

direction or Inte".

Inte" has p"aced Pentium II on a sma"" circuit

board, instead o being an integrated circuit.A B2 cacheon main circuit board o not ast

enough to unction proper"y &ith Pentium II

Microprocessor on the Pentium II modu"eactua""y Pentium Pro &ith MM> e?tensions.

In 199+ Inte" changed Pentium II bus speed.


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arry . rey

In 199+ Inte" changed Pentium II bus speed.

A ne&er Pentium II uses a 100 M7G bus speed

7igher speed memory bus reDuires + ns!#-M.

A rep"aces 10 ns !#-M &ith M7G bus speed

Inte" announced >eon in mid6199+.


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arry . rey

A speciica""y designed or high6end &or8station

and ser$er app"ications

>eon a$ai"ab"e &ith 2 B1 cacheand B2

cache siGe o *12, 1M, or 2M bytes.

>eon unctions &ith the ))0H> chip set.

-"so designed to unction &ith our >eons in

the same system, simi"ar to Pentium Pro.

%e&er product represents strategy change.A Inte" produces a proessiona" and home=business

$ersion o the Pentium II

Pentium Microprocessor


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p

aster core than Pentium IIF sti"" a P or

Pentium Pro processor. -$ai"ab"e in s"ot 1 $ersion mounted on a

p"astic cartridge.

-"so soc8et (0 $ersion ca""ed a "ip6chip&hich "oo8s "i8e o"der Pentium pac8age.

Pentium III a$ai"ab"e &ith c"oc8 reDuencies

up to 1 H7G.

!"ot 1 $ersion contains a *12 cacheF "ip6


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%rchitecture, Pro&rammin&, and Inter'acin&, Eighth Editionarry . rey

F p

chip $ersion contains 2* cache.

"ip6chip $ersion runs at c"oc8 speedF !"ot 1cache $ersion runs at one6ha" c"oc8 speed.

oth $ersions use 100 M7G memory bus.

A Ce"eron memory bus c"oc8 speed M7G ront side bus connection, microprocessor to

memory contro""er, PCI contro""er, and -HP

contro""er, no& either 100 or 1 M7G.A this change has impro$ed perormance

A memory sti"" runs at 100 M7G

Pentium 4 an! #ore2


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Microprocessors

Pentium ) irst made a$ai"ab"e in "ate 2000.

A most recent $ersion o Pentium ca""ed Core2

A uses Inte" P architecture

Pentium ) a$ai"ab"e to .2 H7Gand aster.

A supporting chip sets use #-M! or #

memory in p"ace o !#-M techno"ogy

Core2is a$ai"ab"e at speeds o up to H7G.A impro$ement in interna" integration, at present

the 0.0)* micron or )* nmtechno"ogy

- "i8e"y change is a shit rom a"uminumto


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y g

copperinterconnections inside the

microprocessor.

Copper is a better conductor.

A shou"d a""o& increased c"oc8reDuencies

A especia""y true no& that a method or using

copper has suraced at IM

-nother e$ent to "oo8 or is a change in the

speed o the ront side bus.

A increase beyond current ma?imum 10 M7G

Pentium 4 an! #ore2$ 64-bit an!


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Multiple #ore Microprocessors

#ecent modiications to Pentium ) and Core2inc"ude a )6bit coreand mu"tip"e cores.

)6bit modiication a""o&s address o o$er )H 5109@

bytes o memory through a )6bit address.A )0 address pinsin these ne&er $ersions a""o&

up to 13 5terabytes: 1000H@o memory to be accessed

-"so a""o&s )6bit integer arithmetic.

A "ess important than abi"ity to address more memory

iggest ad$ancement is inc"usion o mu"tip"e


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Copyright 2009 by Pearson Education, Inc.

pper !add"e #i$er, %e& 'ersey 0()*+ -"" rights reser$ed.



gg pcores.A each core e?ecutes a separate tas8 in a program

Increases speed o e?ecution i program is&ritten to ta8e ad$antage o mu"tip"e cores.A ca""ed multithreadedapp"ications 5-

mu"tithreaded process &ith t&o threads e?ecutingin time c"ear"y sho&ing that the threads e?ecuteseparate"y and e?ecute mutua""y e?c"usi$e"y intime.@

Inte" manuactures dua"and Duad core$ersionsF number o cores &i"" "i8e"y increaseto eightor e$en si?teen.

Mu"tip"e cores are current so"ution to


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p

pro$iding aster microprocessors.

Inte" recent"y demonstrated Core2 containing+0 cores, using )* nmabrication techno"ogy.

Inte" e?pects to re"ease an +06core $ersion

some time in the ne?t * years. abrication techno"ogy &i"" become s"ight"y

sma""er &ith * nmand possib"y 2* nm

techno"ogy.

The %uture o& Microprocessors


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%o one can ma8e accurate predictions.

!uccess o Inte" shou"d continue. Change to #I!C techno"ogy may occurF more "i8e"y

impro$ements to ne& hyper6threadingtechno"ogy.57yper63hreading 3echno"ogy uses processor resources more eicient"y, enab"ing mu"tip"e threads to run on each

core.


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y

communicate direct"y &ith each other.

A a""o&s para""e" processing &ithout any change

to the instruction set or program

Current supersca"ertechno"ogy uses many

microprocessorsF a"" share same register set.

A ne& techno"ogy contains many microprocessors

A each contains its o&n register set "in8ed &ith the

other microprocessors registers

/ers true para""e" processing &ithout &ritingany specia" program.

In 2002, Inte" re"eased a ne& architecture )


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bits in &idth &ith a 12+6bit data bus.

%amed ItaniumF 4oint $enture ca""ed EPIC5E?p"icit"y Para""e" Instruction Computing@ o

Inte" and 7e&"ett6Pac8ard.

3he Itanium architecture a""o&s greaterpara""e"ismthan traditiona" architectures.

12+ genera"6purpose integer and 12+ "oating6

point registersF ) predicate registers.

Many e?ecution units to ensure enough

hard&are resources or sot&are.

/i-ure 1a Conceptua" $ie&s o the +0)+, Pentium Pro, Pentium II, Pentium III,

Pentium ), and Core2 microprocessors.


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/i-ure 1b Conceptua" $ie&s o the +0)+, Pentium Pro, Pentium II, Pentium III,

Pentium ), and Core2 microprocessors.


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C"oc8 reDuencies seemed to ha$e pea8ed.


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!urge to mu"tip"e cores has begun.

Memory speed a consideration.A speed o dynamic #-M memory has notchanged or many years.

Push to static #-M memory&i"" e$entua""y.

increase the perormance o the PC.A main prob"em &ith "arge static #-M is heat

A static #-M operates *0 times aster than dynamic

#-M

!peed o mass storage another prob"em.


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A transer speed o hard dis8 dri$es has changed"itt"ein past e& years

A ne& techno"ogy needed or mass storage

"ash memory cou"d be so"ution.

A &rite speed comparab"e to hard dis8 memory

"ash memory cou"d store the operatingsystem or common app"ications.

A &ou"d a""o& operating system to "oad in a second

or t&o instead o many seconds no& reDuired

17 $" IC%O2%OC##O%


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'!#+ 2%#O*!& CO2U$%

#;#$ Computers ha$e undergone many changes

recent"y.

Machines that once i""ed "arge areas reducedto sma"" des8top computersystems because

o the microprocessor.

A a"though compact, they possess computing po&eron"y dreamedo a e& years ago

igure 1A sho&s b"oc8 diagram o the


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persona" computer.

-pp"ies to any computer system, rom ear"ymainrame computers to the "atest systems.

iagram composed o three b"oc8s

interconnectedby buses.A a busis the set o common connectionsthat carry the same type o inormation

/i-ure 1< 3he b"oc8 diagram o a microprocessor6based computer system.


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/i-ure 1= 3he memory map o a persona" computer.


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Main memory system di$ided into three parts:


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A 3P-5transient program area@

A system area

A >M!5e?tended memory system@

3ype o microprocessor present determines&hether an e?tended memory system e?ists.

irst 1M byte o memory oten ca""ed the rea"or con$entiona" memory system.

A Inte" microprocessors designed to unction

in this area using rea" mode operation

+02+ through the Core2 contain the 3P-5)0 b t @ d t 5+) b t @


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5)0 bytes@ and system area 5+) bytes@.

A a"so contain e?tended memory

A oten ca""ed-3 c"ass machines

3he P!=" and P!=2 by IM are other $ersionso the same basic memory design.

-"so reerred to as I!- 5industry standardarchitecture@ or EI!- 5e?tended I!-@.

3he P!=2 reerred to as a micro6channe"

architecture or I!- system.A depending on the mode" number

Pentium and -3> c"ass machines eaturedditi th PCI 5 i h l t


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addition o the PCI 5peripheral componentinterconnect@ bus.

A no& used in a"" Pentium through Core2 systems

E?tended memory up to 1*M bytes in the+02+ and +0+!>F )09*M bytes in +0)+

+0+>, Pentium microprocessors. 3he Pentium Pro through Core2 computer

systems ha$e up to 1M "ess than )H52bit

address@or 1 M "ess than)H 5 itaddress@o e?tended memory.

!er$ers tend to use the "arger memory map.

Many +0)+ systems use >#!"oca", B busto interace dis8 and ideo to the


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to interace dis8 and $ideo to themicroprocessor at the "oca" bus "e$e".

A a""o&s 26bit interacesto unction at samec"oc8ing speed as the microprocessor

A recent modiication supporting )6bit data bushas generated "itt"e interest

I!-=EI!- standards unction at + M7G.

PCI bus is a 26or )6bit bus.

A speciica""y designed to unction &ith the Pentiumthrough Core2 at a bus speed o M7G.

3hree ne&er buses ha$e appeared.


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! 5universal serial bus@.

A intended to connect periphera" de$ices to themicroprocessor through a seria" data path anda t&isted pair o &ires

ata transer rates are 10 Mbps or !1.

Increase to )+0 Mbpsin !2. Increase to )+0>10 Mbpsin !.

-HP 5advanced -raphics port@ or $ideocards


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cards.

3he port transers data bet&een $ideo cardand microprocessor at higher speeds.

A M7G, &ith )6bit data path

Batest -HP speed +> or 2H bytes=second.

A $ideo subsystem change made to accommodatene& p"ayers or the PC.

Batest ne& buses are seria" -3- interace5#!$!: #erial !dvanced $echnolo-y


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5#!$!: #erial !dvanced $echnolo-y!ttachment@ or hard dis8 dri$esF PCI

E?press bus 5Periphera" ComponentInterace@ or the $ideo card.

3he !-3- bus transers data rom PC to harddis8 at rates o 1*0M bytes per secondF 00M

bytes or !-3-62.A seria" -3- standard &i"" e$entua""y reach speeds

o )*0M bytes per second

PCI E?press bus $ideo cards operate at 1>speeds today.

!-3-


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#erial !$!5#!$!or #erial !dvanced $echnolo-y!ttachment@ is a computer businterace orconnecting host bus adapterstomass storage de$icessuch as hard dis8 dri$esandoptica" dri$es. !eria" -3- &as designed to rep"ace

the o"der-3- 5-3 -ttachment@standard 5a"so 8no&nas EIE@, oering se$era" ad$antages o$er the o"derpara""e" -3-5P-3-@ interace: reduced cab"e6bu"8and cost 5( conductors $ersus )0@, nati$e

hot s&apping, aster data transerthrough highersigna""ing rates, and more eicient transer throughan 5optiona"@ I=/ Dueuing protoco".

The TP'
http://en.wikipedia.org/wiki/Computer_bushttp://en.wikipedia.org/wiki/Host_adapterhttp://en.wikipedia.org/wiki/Mass_storage_devicehttp://en.wikipedia.org/wiki/Hard_disk_drivehttp://en.wikipedia.org/wiki/Optical_drivehttp://en.wikipedia.org/wiki/AT_Attachmenthttp://en.wikipedia.org/wiki/EIDEhttp://en.wikipedia.org/wiki/Parallel_ATAhttp://en.wikipedia.org/wiki/Hot_swappinghttp://en.wikipedia.org/wiki/Data_transferhttp://en.wikipedia.org/wiki/Data_transferhttp://en.wikipedia.org/wiki/Hot_swappinghttp://en.wikipedia.org/wiki/Parallel_ATAhttp://en.wikipedia.org/wiki/EIDEhttp://en.wikipedia.org/wiki/AT_Attachmenthttp://en.wikipedia.org/wiki/Optical_drivehttp://en.wikipedia.org/wiki/Hard_disk_drivehttp://en.wikipedia.org/wiki/Mass_storage_devicehttp://en.wikipedia.org/wiki/Host_adapterhttp://en.wikipedia.org/wiki/Computer_bus


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3he transient program area 53P-@ ho"ds the

/! 5dis4 operatin- system@ operatingsystemF other programs that contro" the

computer system.

Athe 3P- is a /! concept and not rea""yapp"icab"e in


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/! memory map sho&s

ho& areas o 3P-are usedor system programs, data

and dri$ers.

A a"so sho&s a "arge area o

memory a$ai"ab"e or

app"ication programs

A he?adecima" number to "et o

each area represents thememory addresses that begin

and end each data area

7e?adecima" memory addresses number

h b t th t


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each byte o the memory system.

A a he?adecima" number is a number represented

in radi? 1 or base 1

A each digit represents a $a"ue rom 0 to 9 and

rom - to

/ten a he?adecima" number ends &ith an7 to indicate it is a he?adecima" $a"ue.

A 12)7is 12) he?adecima"

A a"so represent he?adecima" data as 0?"2) ora 12) he?adecima"

Interrupt $ectors access /!, I/! 5basic

I=/ s stem@ and app"ications


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I=/ system@, and app"ications.

-reas contain transient data to access I=/de$ices and interna" eatures o the system.

A these are stored in the 3P-so they can be

changed as /!operates

3he I/.!S! "oadsinto the 3P- rom the dis8

&hene$er an M!/! system is started


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The Intel Microprocessors: 8086

the intel microprocessors chapter 1

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