the inverter - static properties

8/22/2019 The inverter - static properties

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3. The inverter - static

properties

In this chapter the basic properties of the inverter will be considered. While

not being a very exciting device per se, the inverter has some very basic

properties to which the properties of any logic gate, or analog amplifier

circuit for that matter, can be related. Both the static and the dynamic

properties of the inverter will be considered. The static properties concern

the logic function of the inverter, while the dynamic properties concerns the

transient switching of the output from one logical state to the other as a

result of a switching input.

Fig. 3.1. The inverter as a symbol for a Boolean truth table.

In essence, the inverter is a symbol representing a very simple Boolean truth

table as illustrated in Fig. 3.1, where a logical zero input produces a logical

one at the output and vice versa. In this model nothing is said about the

propagation delay between the switching of the input and the switching of

the input. To account for this dynamic property of the electronic

implementation of an inverter, a delay model could be added as shown in

Fig. 3.2. Delay models range from very simple models for hand calculations

to rather complicated models for timing analysis using electronic design

automation (EDA) tools. The most simple delay model only considers a

constant delay, while a more complicated delay model considers both the

size of the inverter and the output load as well as the input switching speed.

One value for the propagation delay that is often referred to is the fanout-

of-four delay, the FO4 delay, see Fig. 3.3 which shows the delay of an

inverter loaded by four identical inverters

VIN

VIN VOUT

0 1

1 0

VOUT


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Fig. 3.2. An inverter with a delay model.

Fig. 3.3. An inverter with a fanout-of- four (FO4) delay.

3.1 Static properties

The aim of this section is to describe the static properties of a CMOS

inverter in rather simple terms.

The simplest electronic implementation of an inverter requires an

electronic switch such as the N-switch described in chapter 1, and a load

resistor as shown in Fig. 3.4. Here, a logical one is represented by the supply

voltage VDD, while a logical zero is represented by zero voltage VSS, or

ground. For this inverter to be robust the voltage transfer characteristic

(VTC) should be centered on VDD/2 so that the input voltage when theinverter flips between logical states is VDD/2. The low output voltage when

the MOSFET is ON is given by resistive voltage division by

.ONOL DD

ON L

RV V

R R

(3.1)

For this output voltage to go low the MOSFET ON resistance should be

much smaller than the load resistance, i.e.RON


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switch is turned on at its threshold voltage VTN and the on-resistance RONis

voltage dependent is indicated by the dashed line.

In CMOS technology the resistor could be implemented by using a pseudo-

NMOS load in form of a p-channel MOSFET as shown in Fig. 3.5. When

used as an amplifier in an analog design, the p-channel load device is usually

biased through a current mirror designed so that current IB, or fractions of

this current, also flows through the inverter.

Fig. 3.5. The pseudo-NMOS-inverter.

A more power-efficient implementation of an inverter uses two

complementary switches as shown in Fig. 3.6. For a high input VIH, the N-

switch turns ON and the P-switch turns OFF making the output go low, VOL.

For a low input VIL the N-switch turns OFF and the P-switch turns ON

making the output go high, VOH. Since one of the two switches is always

vIN

vOUT

VDD

VB

vIN

vOUT

VDD

VB

VDD

IB

Fig. 3.4. The basic inverter function illustrated with an N-switch and a load

resistance RL and its voltage transfer characteristic (VTC).

VOUT

VIN

VDD

VDD

VDD/2

VDD/2

VOL

VOH

VSS

ROFF RONVIH

VOL

VIL

VOH

VDD VDD

VSSVSS

RL

VIN

VOUT

VDD

VSS

RL RL


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OFF, there is no static power dissipation in any of the two logic states, a fact

that is the main advantage of the CMOS technology.

In this CMOS implementation of an inverter there is a full output voltageswing between the supply rails VDD and VSS, independent of the ON

resistances of the switches. The switching voltage of the CMOS inverter is

given by the input voltage for which both MOSFET devices deliver the same

saturation current. For a robust design with a switching voltage equal to

VDD/2 both MOSFETs should have the same driving capability.

In more detail, the accepted output voltage range for a logical one is

given by VOH,min


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Fig. 3.8. Illustration of the level-restoring properties of the inverter.

In summary, the basic properties of a CMOS inverter are

Full voltage swing from rail to rail

No static power dissipation

Robustness

Noise margins

Level-restoring.

V1 V2VIN

Fig. 3.7. Definition of noise margins using a simplified piecewise-linear

voltage transfer curve (VTC).

VDDVOH,min

VOL,maxVSS

VSS VIL,maxVIH,min VDD

VOUT

NMH

NML

VIH,min

VIL,max

VIN

VDD

VSS


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3.2 The voltage transfer curve (VTC) in detail

When calculating the inverter voltage transfer characteristic, we use a simple

circuit model where the MOSFET is represented by its ON resistance in the

linear region and by its saturation currentIDSATin the saturation region.

Exercise 3.1: Derive the equations describing the MOS-inverter voltagetransfer characteristic in Fig. 3.9.

Solution. The load line of the resistor is given by

.DD OUT

L

V VI

R

(3.2)

The n-channel switch is either saturated or acting as a resistor: in the green

region where the MOSFET is saturated equal currents through the load

resistor and the MOSFET yield

RON

VOUTVOUT

VDD

VSS

RL

IDSAT

VSS

VDD

RL

SUBTHRESHOLD

REGION

VSS

VIN

VOUT

VDD

RL

Fig. 3.9. The basic inverter with a load resistance RL and its voltage transfer

characteristic.


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2

.2

DD OUTDSAT IN TN

L

V VkI V V

R

(3.3)

Solving forVOUT yields the following equation describing a parabola for the

transfer characteristic in the green region

2

.2

LOUT DD IN TN

kR

V V V V (3.4)

Using the same condition of current identity in the blue region where the

MOSFET behaves like a nonlinear resistor, we obtain

2

21 1.DD

OUT IN TN IN TN

L L L

VV V V V V

kR kR kR

(3.5)

When kRL, this expression simplifies to

,ONDDOUT

L IN TN L

RVV

kR V V R

which is nothing but plain simple voltage division between resistors RONand

RL.

The basic parameter of this VTC is given by kRL; the higher the value of this

parameter, the better the inverter characteristic and the higher the voltage

amplification in the switching region. Large values ofkRL means thatRL >>

RON, i. e. the MOSFET must be designed for high driving capability with

respect to the load resistance. This is why this logic style is named ratioed

logic. This VTC is again illustrated in the right-hand diagram of Fig. 3.10

while the left-hand diagram shows the resistor load line and MOSFET IV-

characteristic for two different input gate voltages.

.1 The CMOS inverter

The voltage transfer characteristic of the CMOS inverter can be derived

similarly. However, it is just a little bit more complicated since we must

keep track of the operation regions of both the nMOS transistor and the

pMOS load transistor. As shown in Fig. 3.11, we have to keep track of the

following regions and MOSFET bias conditions:


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Fig. 3.10. Load curves for the n-channel MOSFET for two different input

voltages plotted together with the resistor load line (left), and the inverter

voltage transfer characteristic (right).

Fig. 3.11. Regions of MOSFET operation for the CMOS inverter.

A:n

subthreshold

region

VUT

VDDVINVTN

VDD

VDD+VTP

BothMOSFETssaturated

D:nMOS resistive

B:pMOS resistive

RegionA,B

VOUT

VDD

RON,P

IDSAT,N

VOUT

VDD

IDSAT,N

VDD

RON,N

IDSAT,P

RegionC

VOUT

IDSAT,P

RegionD,E

RegionC:

E:p

subthreshold

region


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both n-channel and p-channel MOSFETs are saturated (region C) n-channel MOSFET is saturated (or OFF) and p-channel MOSFET

is linear (regions A and B)

p-channel MOSFET is saturated (or OFF) and n-channel MOSFETis linear (regions C and D)

The circuit element representation of the MOSFETs in the CMOS inverter is

shown at the top of Fig. 3.11. In Fig. 3.12 we can see the current/voltage

characteristics of the two MOSFETs for three different input voltages (left)

and the resulting bias points on the VTC on the right. Most easily recognized

is the illustration of region C marked VIN=VSW. In the left-hand diagram we

can see that for this input voltage both MOSFETs deliver the same saturation

currents resulting in a region of infinite voltage amplification in the right-

hand VTC. This is the input voltage VSW for which the inverter flips. It can

be derived from the following equation of equal saturation currents:

2 2 where and .2 2

pnGSTN SGTP GSTN IN TN SGTP DD IN TP

kkV V V V V V V V V (3.6)

The resulting switching voltage is then given by

1

DD TP TNin sw

V V xV V V

x

, wherex=kN/ kP. (3.7)

ForVTN=-VTP and x=1 the switching voltage is VDD/2. For strong n-channel

devices,x >1, Vsw < VDD/2 and for strong p-channel devices, Vsw> VDD/2,

Fig.3.12. Finding bias points on the CMOS inverter VTC.


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In region B, where the p-channel device is resistive, the VTC curve can be

derived from the following equal current condition:

22 2

n DD OUT GSTN p SGTP DD OUT

k V VV k V V V

, (3.8)

yielding

2 2

.NOUT IN TP DD IN TP IN TN P

kV V V V V V V V

k

(3.9)

Similarly for region D, where the n-channel device is resistive, we obtain the

following equal current condition

2

,2

UT

N IN TN UT P DD IN TP

Vk V V V k V V V

(3.10)

yielding

2 2

.POUT IN TN IN TN DD IN TP N

kV V V V V V V V k

(3.11)

3.3 Process corners

Due to process variations kn/kp varies across the wafer and between wafers.

This results in a spread of inverter switching voltages as shown in Fig. 3.13.

The process corners of the MOSFET driving capabilities are also illustrated.

Fig. 3.13. MOSFET driving capability process window (right) and resultingspread of inverter switching voltages (left).

kP

HI,HI

kN

LO,HI

HI,LO

LO,LO


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3.4 The inverter as an analog amplifier

The inverter is of course a digital device, but the circuit implementation of

the inverter also works as an amplifier of small analog signals. This is

illustrated in Fig. 3.14. The figure shows how a MOSFET with a load

resistor has been biased in the saturation region where the MOSFET acts as a

voltage-controlled current source. A small sinusoidal input signal, on top of

the bias voltage, results in an amplified sinusoidal at the output. The voltage

amplification can be calculated from the small signal model,Av=-gmRL.

Fig. 3.14. Basic amplifier circuit.

vOUT

VSS

IDSAT

RL

VSS

vIN

vOUT

VDD

RL

vout= gmRLvin

VSS

gmvin

RL

largesignalmodel smallsignalmodel

SUBTHRESHO

LD

REGION


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The design methodology assumed by the analog designer is to use nonlinear

large-signal analysis for calculating the bias point and the linear region of

operation of the amplifier, and to use linear small-signal analysis for

calculating the voltage amplification. The output voltage range of the

amplifier is limited by distortion due to the nonlinear transfer characteristic.The linearized small-signal transfer curve with slope Av is shown dashed (in

red). The small-signal amplification is given by

.OUT OUT OUT v L mIN OUT IN

v v iA R g

v i v

(3.12)

The nonlinearity of the transfer curve that is an advantage in digital designs,

giving the inverter its level restoring properties, is a disadvantage in analog

designs due to distortion and creation of overtones.

3.4.1 The pseudo-NMOS amplifierThe most common analog integrated circuit CMOS amplifier is the pseudo-

NMOS-inverter amplifier shown in Fig. 3.15. In this design, the load resistor

is implemented by use of a pMOS device since area-efficient resistors are

not available in CMOS integrated circuit technology. The pMOS load

transistor has a fixed bias voltage VB indirectly set by the current mirror M2-

M3. The reference current IB, or multiples thereof, is mirrored from a

reference stage to the amplifier stage. The same current will flow through

M2 and M3 since they have the same gate to source voltage provided they

are designed for equal driving capabilities. The amplifier large-signal and

small-signal models are also shown in the figure.

Fig. 3.15. The pseudo-NMOS amplifier and its circuit models.

M2M3

M1vIN

vOUT

VDD

VB

VDD

IB

IB

vOUT

IDSAT

IB

gmnvin

gdp

largesignalmodel smallsignalmodel

gdn

mn IN OUT

dn dp

g vv

g g


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The designer determines the amplifier current level to provide the n-channel

MOSFET with a certain transconductance at a certain gate bias,

,,

/ 2

DSAT N Bmn

GS GSTN

i Ig

v V

(3.13)

where typically the gate bias VGSTN

=VIN

-VTN

is in the100-200 mV range. The

nMOS-transistor is sized to sink the given current IB at this given bias

voltage, i.e.

2.

2B IN TN

kI V V (3.14)

The amplifier transfer curve is shown in Fig. 3.16. Its region of linear

operation is determined by the saturation condition for the two MOSFETs

nMOS.

pMOS

IN TN OUT

DD B TP DD OUT OUT B TP

V V V

V V V V V V V V

(3.15)

Hence, the region of operation is given by

,IN TN OUT B TP

V V V V V (3.16)

as shown in Fig. 3.16. The smaller the gate voltage overdrive, the larger the

region of linear amplifier operation. In essence, the gate voltage overdrives

chosen determines how close to the rails the amplifier will work.

Fig. 3.16. The amplifier and its linear region of operation.

SUBTHRESHOLD

REGIO

N


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For this amplifier circuit, the small-signal model must be more detailed than

before in that the MOSFET output conductance must be carefully

considered. From the small-signal model of the amplifier circuit, the

following small signal amplification can be derived

.OUT mnvIN dn dp

v gAv g g

(3.17)

Example3.2. Calculate the circuit voltage amplification at a current level of200 A if the MOSFETs are biased with gate voltage overdrives of 200 mV.

The Early voltages of the devices are assumed to be 5 V.

Solution: The transconductance is given by

200 [A]2 mA/V.

/ 2 100 [mV]

Bmn

GSTN

Ig

V

The output conductance is approximately given by

200 [A]40 A/V.

5 [V]

Bd

A

Ig

V

The voltage amplification is then

225.

0.04 0.04

mnv

dn dp

gA

g g

It is interesting to note that, in the case of equal Early voltages, the voltage

amplification can be written

525.

0,2

Av

GST

VA

V

Example3.3. Is it reasonable to neglect velocity saturation for a MOSFETbiased at VGST=100 mV if the velocity saturation voltage is VC=2 V?

Solution: With VC=2 the drain current saturation voltage is given by

0.20.095 V.

2.1

GST C

DSAT

GST C

V VV

V V

The error is only 5%, resulting in a 5% error in the calculation of the

saturation current. However, forVGST=200 mV and VC=1 V, the error is 20%.

For calculating the maximum saturation current available at say VGST=0.9 V,

great care must be taken to use the saturation voltages. For the two cases ofVC=1 V and VC=2 V, the correct saturation voltages are 0.47 V and 0.31 V.


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Using VDSAT=0.9 V, instead of the correct values, for calculating the

saturation current would result in an overestimation of the saturation current

by a factor of two and three, respectively.

3.4.2 The CMOS inverter as an amplifier

The same type of analysis can be applied to calculate the small-signalproperties of the CMOS inverter. Its large-signal and small-signal equivalent

circuits are shown in Fig. 3.17.

The region of amplifier operation can be derived from large-signal

analysis using the saturation conditions

nMOS.

pMOS

IN TN OUT

DD IN TP DD OUT OUT IN TP

V V V

V V V V V V V V

(3.18)

Hence, the region of amplifier operation is given by

,BIAS TN OUT BIAS TPV V V V V (3.19)

where VIN=VBIAS is the input bias voltage. The bias point and the (green)

region of amplifier operation around the bias point are indicated in Fig. 3.18.

The Norton and Thevenin equivalent circuits resulting from the inverter

small-signal equivalent circuit in Fig. 3.17 is shown in Fig. 3.19. As

indicated by the figure, the CMOS inverter can be equivalently regarded as a

current source or a voltage source, both with an internal source resistance

determined by the sum of the output conductances.

Fig. 3.17. The CMOS-inverter, its large- and small-signal equivalent circuits

VIN VOUT

VDD

VSS

VOUT

VDD

IDSAT,N

IDSAT,P

largesignal

model small

signal

model

vout

gmnvin

gmpvin gdp

gdp


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Fig. 3.18. The CMOS-inverter and its voltage transfer characteristic.

Obviously, the voltage amplification of the CMOS inverter as an amplifier is

given by

.mn mpOUT

v

IN dn dp

g gvA

v g g

(3.20-)

Due to several reasons the CMOS inverter amplifier is not commonly used.

First, the input voltage range of the CMOS amplifier is often very narrow as

is apparent from the figure; secondly, it also receives poor marks on other

amplifier properties such as supply noise rejection [Rabaey et al., p 190].

Example 3.4: Compare the voltage amplification of the CMOS inverter to

that of the pseudo-NMOS amplifier in Example 3.2.

Solution: Providedgmp=gmn, the voltage amplification is given by

2 250.

0.04 0.04

mn mp

v

dn dp

g gA

g g

Twice!

Fig. 3.19. Norton and Thevenin equivalent circuits of the CMOS amplifier.

vout

+

gdn+gdp

mn mp

in

dn dp

g gv

g g

Thevenincircuit

vout

(gmn+gmp)vin

Nortoncircuit

gdn+gdp

nsubthreshold

region

psubthres

hold

region


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3.5 Summary

In this chapter we have investigated the functionality and the static

properties of the CMOS inverter. First, the digital properties of the inverter

were studied and its voltage transfer characteristic was derived and analyzed.

Three different inverter implementations were analyzed; with resistive load,

with pseudo nMOS load and with active pull-up pMOS load. The inverter

switching voltage and its noise margins were defined. Variations across the

wafer and between wafers due to process variations were mentioned.

Finally, the small-signal properties of the inverter as an analog amplifier

were discussed.

the inverter - static properties

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