The investigation on the Germanium-On-Insulator (GeOI) manufactured by a low temperature Smart-cut process

Xuan Xiong Zhanga, b, Qing Miaoc, Yi OUa, Fan Yanga, Xingsen Gaoc, Song Lin Zhuangb aInstitute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China bShanghai Key Laboratory of Modern Optical System

University of Shanghai for Science and Technology, Shanghai 200093, China cInstitute for Advanced Materials, South China Normal University, Guangzhou 510006, China

The heterogeneous integration of Si and Ge is attracting more attentions in the fields of microelectronics and optoelectronics because

Ge with higher carrier mobility of electrons and holes can be used as the transistor channel (1) or detector (2) for future CMOS and

OEIC. Nevertheless, Ge has to integrate with silicon in order to sufficiently make use of the platform from the perfect silicon CMOS

technology. On the other hand, Ge can play an important in the combination of silicon and III-V compound semiconductor owing to

the matched lattice parameter between Ge and III-V for III-V integration into silicon CMOS (3). However, ~4% lattice parameter

difference between Ge and silicon results in high defect density during Ge epitaxy on silicon (4). Moreover, Ge-on-insulator (GeOI),

such as silicon-on-insulator (SOI) structure, should be employed to suppress the current leakage caused by narrow bandgap (0.66eV)

as Ge is used as a transistor channel material.

Smart-cut process (5) is an enabling technology to achieve heterogeneous integration due to match-free requirement of lattice pattern.

However, the process of the heterogeneous wafer bonding has to be carried out under the low temperature thanks to the difference of

thermal expansion coefficient between both materials. There are a high defect density on the germanium layer of the GeOI

manufactured by well-known smart-cut process although the GeOI wafer with 200mm diameter was formed (6).

In this report, we show the method to manufacture the GeOI by actuating the most defects located at the rim of the transferred

germanium layer via a low temperature and longtime annealing and obtained an alleviated or defect-free germanium film layer at the

center of the GeOI wafer. Fig. 1 shows the optical microscope pictures from the center and rim of the GeOI. The cross-section TEM

image of the GeOI which was thinned to ~100nm is shown in Fig. 2. The amorphous germanium caused by H-implanted Ge wafer can

be removed through etching and the roughness of the transferred Ge layer is not only deteriorated, but also improved if the proper

control by means of wet etching conditions. Fig. 3a and 3b show AFM images from before and after the transferred germanium layer

etched by a mixture solution of H2O2, ammonia and de-ion water, respectively. As we see in Fig. 3, the etching can prune the

micro-peaks generated by Smart-cut process and result in the raw germanium film planar. We are sure that the roughness will be

further improved by the optimizing the wet etching conditions. The investigation is under way.

Fig.1. the micro-defects in the

fabricated GeOI by our low

temperature Smart-cut process. (a)

central and (b) edge of the GeOI

wafer.

In conclusion, the defect density on the transferred Ge layer located at the center of the GeOI can be effectively lowered by a longtime

annealing. The surface roughness on the raw transferred Ge film can be pronouncedly improved by a wet etching method.

 Author to whom corresponding should be address. E-mail: xxzhang@ime.ac.cn and xuanxiongzhang@yahoo.com.cn Tel: 86-10-82995590; Fax: 86-10-62021601; postal address: No. 3, Bei-Tu-Cheng West Road, Beijing 100029, China.

(a) (b)

Fig. 2. X-TEM image of the etched GeOI to remove

the amorphous germanium layer caused by

H-implanted germanium wafer.

Fig. 3. AFM images (a) the raw transferred germanium surface and (b) the surface after a wet etching.

This work was supported by National Natural Science Foundation of China Grant No. 61274105, Shanghai Municipal Education

Commission Grant No. 06ZZ31 and One Hundred Person Project (29Y0YB024001) of Chinese Academy of Sciences.

References

1. D. Lin, G. Brammertz, S. Sioncke, C. Fleischmann, A. Delabie, K. Martens, H. Bender, T. Conard, W. H. Tseng, J. C. Lin, W. E.

Wang, K. Temst, A. Vatomme, J. Mitard, M. Caymax, M. Meuris, M. Heyns and T. Hoffmann, 2009 IEEE International Electron

Devices Meeting, 300 (2009).

2. T. Pinguet, S. Gloeckner, G. Masini and A. Mekis, Top Appl Phys, 119, 187 (2011).

3. W. K. Liu, D. Lubyshev, J. M. Fastenau, Y. Wu, M. T. Bulsara, E. A. Fitzgerald, M. Urteaga, W. Ha, J. Bergman, B. Brar, W. E.

Hoke, J. R. LaRoche, K. J. Herrick, T. E. Kazior, D. Clark, D. Smith, R. F. Thompson, C. Drazek and N. Daval, J Cryst Growth,

311, 1979 (2009).

4. V. A. Shah, A. Dobbie, M. Myronov and D. R. Leadley, Solid State Electron, 62, 189 (2011).

5. M. Bruel, Electron Lett, 31, 1201 (1995).

6. T. Akatsu, C. Deguet, L. Snachez, F. Allibert, D. Rouchon, T. Signamarcheix, C. Richtarch, A. Boussagol, V. Loup, F. Mazen, J. M.

Hartmann, Y. Campidelli, L. Clavelier, F. Letertre, N. Kernevez and C. Mazure, Mat Sci Semicon Proc, 9, 444 (2006).