the junctionless transistor - george j. ferko v

MAT355 Junctionless Transistor - GJ Ferko 1

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The Junctionless Transistor By George J. Ferko V* 05/10/10 1. Summary The operation of the modern conventional bulk transistor is dependent on the junctions that exist between the source electrode, channel region, and drain electrode. These junctions are formed as a result of the channel being doped to have an opposite polarity in comparison to the source and the drain. The channel itself is actually formed by a bias that is the result of a gate electrode. If you ask any materials scientist or electrical engineer they will tell you that the modern transistor is on its way out. As the size of the transistor is shrinking so is the channel region. As a result the channel region demands a higher doping concentration to avoid short-channel effects. Unfortunately this concentration is too high for the devices to properly operate. An immense amount of research into the successor of the current transistor design has been going on for nearly 30 years out of a necessity to fill the void the modern bulk transistor is about to leave behind. The focus of this body of work is to discuss the junctionless silicon nanowire transistor and to explain why it may be the most feasible option for the next generation of transistors. This report will touch upon some of the history that has led today’s researchers to the junctionless transistor as well as the theory, processing, operation, and future work that is involved with said transistor. 2. History The concept of the junctionless transistor is far from new to the world of solid-state electronics. In fact the notion of a junctionless transistor of uniform doping between the gate, channel, and drain precedes that of the point-contact and the bipolar junction transistor of Bell Telephone Laboratories from the late 1940’s [1]. In 1928 Julius Edgar Lilienfeld filed a patent in the United States entitled “Device for Controlling Electric Current.” Lilienfeld recognized the limitations of electron transport through evacuated spaces as the driving force behind the rapidly expanding electronics industry. He proposed what would later be recognized as the field-effect transistor as a solution. The Lilienfeld transistor, pictured in figure 1, is very similar to modern metal-oxide-semiconductor field effect transistor (MOSFET) [2,3]. In this device a thin semiconductor film is deposited over a thin insulating layer which itself is deposited over the metal electrodes. Lilienfeld theorized that when a gate voltage was applied to the thin semiconductor region between the electrodes the charge carriers would become completely depleted allowing for modulation of the current through the device. This device is actually a resistor in which the current through the resistor is controlled by applying a gate voltage that essentially drives the resistance to infinity [4]. Lilienfeld knew that the semiconductor layer had to be extremely thin; in his patent he stated that for the transistor to work “this layer is extremely thin [then] the field is permitted to penetrate the entire volume thereof and thus will change the conductivity throughout the entire cross-section….” He even recognized a need for what could be considered nanotechnology by choosing the method of depositing a colloidal copper suspension and then sulphurizing it to produce the thin semiconductor layer [2]. Unfortunately


for Lilienfeld the ability to produce a layer thin enough for his device was beyond the technology of the time and he was never able to produce a working transistor. Lilienfelds concept went fairly unnoticed until William Shockley attempted to file a patent in the 1940’s that named the field-effect concept as the basis for controlling current in his solid-state amplifier. Much to Shockley’s dismay the patent was shot down when it was discovered that the concept had previously been patented by Lilienfeld [1]. Today Lilienfelds contribution to solid-state electronics has been recognized. In an address to the American Institute of Physics

in 1988 John Bardeen, one of Shockley’s coworkers at Bell Telephone Labs during the creation of the first solid-state transistors, acknowledged Lilienfeld for his contributions to the semiconductor field. He said, “Lilienfeld had the basic concept of controlling the flow of current in a semiconductor to make an amplifying device. It took many years of theory development and material technology to make his dream a reality [1].” Although Bardeen may have spoken to soon because it wasn’t until 20 years after this address that Lilienfelds junctionless concept was actually realized [4]. The research that has been done on silicon-on-insulator transistor technology has also played a large role in the development of the junctionless transistor. In 1984 T. Sekigawa and Y. Hayashi published the first paper on a multi-gate transistor. They discovered that the short-channel effects being caused by the decreasing size of transistor channels could be minimized by adding an additional gate electrode thus producing more electrostatic control. They named the transistor type XMOS because when it was cross sectioned it had the appearance of the Greek letter Ξ (Xi) [5,6,7]. Their discovery came long before short-channel effects actually became a problem in commercially available transistors, however, it paved the way for future discoveries that helped to develop the multi-gate transistor as a solution to the approaching end-of-the-road for CMOS devices. From then on the Silicon-on-insulator (SOI) MOSFET became a major competitor among the transistor designs that were studied to extend Moore’s Law for years to come. A multitude of other designs and research followed. Some of these designs are shown in figure 2 and further descriptions of them are available in the literature [5,8]. The schematics shown to the right in the figure are the orientations that have been studied in recent years in order to bring the CMOS device down to the nanometer scale. This year (2010) a team lead by Jean-Pierre Colinge at the Ireland based Tyndall National Institute announced the first working junctionless nanowire transistor [7]. By building on the idea of the multi-gate SOI MOSFET this team was able to produce a heavily doped short-channel device that comes close to full free carrier depletion in the channel. They have made this transistor on a silicon nanowire that has equal dopant concentrations between the channel

Figure 1: Diagram of the Lilienfeld concept for a solid-state transistor [2].


and the source and drain extensions [4,9,10]. In the literature the team at Tyndall often mentions the scientists from history who’s contributions to electronics have made their work possible [4,6,5]. Despite this modesty, it is clear from the number of news articles and attention of many peer review journals that the junctionless transistor is building up steam [4,9,21]. 3. Theory The motivation for the concept of the junctionless transistor was to find a way to inexpensively produce a practical transistor that doesn’t face some of the problems that the conventional inversion-mode devices do. The design of the silicon nanowire, or nano ribbon, junctionless transistor is shown in figure 3 [4]. The junctionless transistor is an accumulation-mode device. The literature suggests that on the nano scale accumulation-mode devices have some advantage over the inversion-mode devices. Larger scale accumulation-mode devices have given accumulation-mode the reputation of facing many process variability issues, however; in short-channel construction the inversion-mode has been found to have bigger issues then the accumulation-mode devices. As inversion-mode devices shrink it becomes difficult to maintain suitable current drive at a reasonable threshold voltage because of the necessity of reducing doping concentration when the transistor is made on the nanometer scale. The accumulation-mode devices have been found to perform better with these issues [11]. The junctionless nanowire transistor is basically an accumulation-mode device with equal doping between the channel and the source and drain. As mentioned above, conventional short-channel devices require that large dopant concentration gradients occur over a distance of a few nanometers. The super-sharp source and drain junctions are not stable as diffusion may occur during operation of the device. Even

Figure 2: Different multi-gate FET configurations for the SOI transistor meant to aid in the continuously decreasing size of the transistor [5,8].


forming such devices requires extremely costly thermal processing in device fabrication [4,10,12]. The junctionless transistor clearly solves this short-channel issue because no dopant concentration gradient exists. The dopant concentration in the nanowire used does require a very high doping concentration, which in turn requires that the cross-section of the wire be very small to ensure that it can be fully depleted of free carriers. Another problem with the conventional transistor is its low theoretical subthreshold slope limit of 60 mV/decade at room temperature. The subthreshold slope is

a measure of the switching capability of the MOSFET over time. It is assumed that with any FET the switching ability will decrease over time. Subthreshold slope is taken as the slope of the drain current-gate voltage curve in subthreshold operation (below the threshold voltage). This value of 60 mV/decade is no longer sufficient, especially when we consider the ever decreasing supply voltages that the semiconductor industry is demanding. The literature suggests that the junctionless transistor can obtain sub-60 mV/decade subthreshold slopes with a drain voltage as low as 1.75 V, which is about half the value needed for standard inversion mode devices [13]. This is just a speculation, however, which was based on an experiment involving the comparison of impact ionization between junctionless and junctioned transistors. When the impact ionization occurs over a larger section of the drain extension the drain voltage necessary to produce a low subthreshold slope is less. As the MOSFET is scaled down so is the effective oxide thickness of the gate insulator. This has caused a problem with the vertical electric field in the conventional MOSFET because as the effective oxide thickness decreases the vertical electric field in the channel increases. This causes an increase in free carrier scattering, which has led to a decrease in mobility thus lowering the current drive of the transistor. It has been found that the junctionless accumulation-mode transistor poses yet another advantage to the inversion-mode junctioned transistor. The inversion-mode junctioned transistor’s peak electron concentration occurs in the part of the channel that has the highest electric field. The opposite is true in the junctionless transistor. The peak electron concentration in the junctionless transistor occurs in the region with the lowest electric field. As a result, the current drive in the junctionless transistor will be much better then in junctioned inversion-mode transistors as transistors reach the nanoscale [14]. The quantum-mechanical confinement that causes this down turn in electron concentration for inversion-mode transistors is discussed further in the literature [15]. An interesting result of this study is that inversion-mode transistors did not exhibit the same reduction in electron concentration when they had the gate all around structure, shown in figure 2. This would lead many to think that the gate all around structure shows more promise than other multigate structures, however; it seems that the same quantum confinement issue does not apply to a junctionless transistor and other multi-gate structures are being used with high functionality.

The current drive in the junctionless transistor has the upper hand on the inversion-mode transistor for yet another reason. In inversion-mode transistors the electrons are confined to a

Figure 3: Diagram of the concept for the silicon nano ribbon junctionless transistor [4].


surface channel. This is not so in the junctionless transistor. The junctionless transistor allows the drain current to flow through the entire cross-section of the nanoribbon. This means that the conduction path is primarily located in the middle of the nanoribbon which reduces the scattering effects that occur near interfaces and would be experienced by normal transistors. This can be seen in figure 4 which shows the electron concentration in an n-type junctionless transistor at gate voltages ranging from pinch-off voltage to flat-band conditions [4].

The silicon nanowire has faced other competitors for nanowire transistors, most notably the carbon nano tube. In past research it was found that the quantum confinement to the center of the silicon nanowire resulted in a necessary increase in the gate voltage needed to switch the transistor. However, the silicon nanowire compensates for this effect by not facing a reduction in its density of states. In contrast, the carbon nanotube does see a reduction in density of states and its electrons are confined to the surface of the channel. In one particular study by A. Marchi, et al. the carbon nano tube was found to outperform the silicon nanowire because of the lower gate voltage required to switch transistors where electrons are confined to the surface of a channel. It should be noted that this study was performed on wires ranging from 45 nm to 65 nm in diameter [16]. When the silicon nano ribbon has a thickness of 10 nm the negative effect of quantum confinement in the center of the channel is lost and the silicon nanowire outperforms the carbon nano tube [17,18]. Even before the junctionless transistor was successfully made these effects were predicted. A. Afzalian, et al. have used non-equilibrium Green’s function (NEGF) modeling to predict how the junctionless transistor will work. The specifics of this type

Figure 4: Plots that were formed as the result of a simulation carried out to reveal the electron concentration in the junctionless transistor [4].


of modeling are far beyond the scope of this paper, and the understanding of the author writing this paper, but in depth description of the NEGF are available in the literature [17,19]. 4. Fabrication

The silicon nanowires, or nano-

ribbons are produced from conventional SOI wafers using electron-beam lithography. At Tyndall a JEOL 6000FS lithography tool is used to define nanowires about 30 nm wide and 10 nm thick. In e-beam lithography an electron beam of very small spot size is used to damage the surface of a material and create very small structures. This method is already widely used in the semiconductor and nanotechnology industries. The system is located in a 100 class clean room [20]. After growing a gate oxide of 10 nm the nanowires are uniformly doped by ion implantation. The n-type devices are doped with arsenic and the p-type devices are doped with BF2. The process is controlled to yield uniform doping concentrations ranging from 2 × 1019 to 5 × 1019 atoms per centimeter cubed. The high doping is required to create a large current drive and good source drain contact resistance. The gate is formed by depositing a 50 nm

thick layer of amorphous silicon using low pressure chemical vapor deposition at a temperature of 550 ⁰C. To obtain reasonable values for the threshold voltage the gate in the n-type device is doped to be p-type and vice versa. After heavy gate doping the specimens are annealed in an ambient nitrogen atmosphere at 900 ⁰C for 30 minutes to make the amorphous silicon polycrystalline and to activate the dopants. The gate electrodes are then patterned and etched in a reactive-ion etch reactor. Finally a protective SiO2 layer is deposited and holes are etched in it to make way for the electrical contacts which are formed by a TiW-metallization process. Transmission electron micrographs of the completed device are shown in figure 5 [4]. As stated above, the thinness and narrowness of the silicon ribbon is essential to ensuring that full depletion occurs in the channel when a bias is applied. As electron-beam lithography continues to advance it may become possible to consistently make even smaller devices which would only make the Si nanowire junctionless transistor even more effective as long as suitable current drive can be maintained. This process also clearly eliminates the need for ultrafast annealing making it much cheaper and simpler then the production of junctioned transistors.

Figure 5: Transmission electron micrographs of the silicon nanoribbon devices sharing the same gate [1].


Operation:

The successful fabrication of the junctionless nanowire transistor has meant that the junctionless transistor can now be experimentally tested against the regular MOSFET. Finally modeling and estimations are no longer necessary to prove the potential of junctionless transistors. In a recent study by JP Colinge, et al., the junctionless transistor’s current-voltage characteristics were compared to those of a junctioned tri-gate FET. The graph of drain current versus gate voltage that was produced is shown in figure 6. In this study the drain voltage was ± 1 V and

the devices had a width of 30 nm and a length of 1 μm. The junctionless transistors are entitled “gated resistors” in the figure. By simply looking at the figure it can be seen that the properties of the junctionless transistor and those of the regular MOSFET are almost exactly the same. This establishes the theories that the accumulation-mode junctionless transistor can perform as well as the inversion-mode transistor. Essentially the channel can be electrostatically depleted with the same gate voltage of a regular MOSFET. The subthreshold slope can also be determined from this graph. Previously it was stated that the theoretical minimum subthreshold slope for the regular transistor is about 60 mV/decade. The best junctioned SOI transistors have reached values of 63 mV/decade. The junctionless transistor that produced these gate voltage-

Figure 6: Drain current-gate voltage characteristics for a junctionless transistor and a junctioned transistor [4].

a) b) Figure 7: Output characteristics of the junctionless transistor described by a plot of drain current versus drain voltage for a) a p-doped transistor and b) an n-doped transistor [4].


drain current characteristics had a subthreshold slope of 64 mV/decade. In addition to this exceptional performance the subthreshold slope of the transistor only changed a few percent when it was heated from room temperature to 475 K [1]. Shown in figure 7 are the output I-V characteristics for the junctionless transistor. The nanowire used for this particular output had a width of 20 nm and a length of 1 μm. To anyone who has opened an electronic properties text book or been involved with the electronics industry these curves should look familiar. They show exactly the kind of behavior that would be expected of a traditional MOSFET device. Although the operational characteristics of the junctionless transistor do not exceed those of regular MOSFETs the fact that such similar characteristics have been produced in the first published experimental study goes to show that the junctionless transistor is a feasible option for the nanoscale transistor design. Academics aren’t the only people that take this success seriously; it appears as though commercial industry has taken an interest as well. Tyndall CEO, Professor Roger Whatmore, has been quoted as saying, “We are very excited by the outstanding results that Jean-Pierre has achieved. We are beginning to talk about these results with some of the world's leading semiconductor companies and are receiving a lot of interest in further development and possible licensing of the technology [21].” Future: Whether or not the junctionless transistor continues to gain popularity most certainly depends on its ability to continue shrinking in size. L. Ansari, et al. have already begun modeling a junctionless transistor made from a silicon nanowire with a radius of 0.52 nm and a gate length of 3.1 nm. They have simulated this atomic scale device and produced some predicted current-voltage output characteristics that look very promising. Though in the present time such transistors cannot be constructed the study is still significant to the future abilities of the junctionless transistor. The team found that the short-channel effect of tunneling across the gate voltage barrier can be avoided at atomic scales as long as the gate length is greater the twice the radius of the nanowire. It was also found that at such small scales the gate-all-around structure is needed in order to produce enough electrostatic control to shut off the gate. Perhaps the most interesting result produced is that the location of the dopant or dopant atoms in the channel region can change the band structure of the nanowire significantly. This means that as the gate length shrinks the doping concentration must be increased to ensure a semi-uniform doping in the gated nanowire. The researchers concluded that the junctionless nanowire transistor would still continue to work even on the atomic scale [22]. The junctionless nanowire is certainly paving a narrow road to success in the semiconductor industry. It is almost inconceivable that the path that has lead to the junctionless transistor began more than 80 years ago. Now it would seem that having an equally doped source, drain, and channel region will be the solution that propels the transistor into the next scale reduction and carries the weight of Moore’s Law through the next decade and perhaps long after that. References: 1. J Vardalas, Twists and turns in the development of the transistor, IEEE – USA Today’s

Egineer, (2003) <http://www.todaysengineer.org/2003/May/history.asp>.


2. JE Lilenfeld, Method and apparatus for controlling electric currents, U.S. Patent 1,745,175, (1926).

3. JE Lilenfeld, Device for controlling electric current, U.S. Patent 1,900,018, (1928). 4. JP Colinge, et al., Nanowire transistors without junctions, Nature Nanotechnology, 5, 225-

229, (2010). 5. JP Colinge, Multi-gate SOI MOSFETs, Microelectronic Engineering, 84, 2071-2076, (2007). 6. JP Colinge, The new generation of SOI MOSFETs, Romanian Journal of Information Science

and Technology, 11(1), 3-15, (2008). 7. T. Sekigawa and Y. Hayashi, Calculated threshold voltage characteristics of an XMOS

trnsistor having an additional bottom gate, Soli-State Electronics, 27, 827, (1984). 8. SRN Yun, et al., Quantum-mechanical effects in nanometer scale MuGFETs,

Microelectronic Engineering, 85, 1717-1722, (2008). 9. AM Ionescu, Nanowire transistors made easy, Nature Nanotechnology, 5, 178-179, (2010). 10. CW Lee, et al., Junctionless multigate field-effect transistor, Applied Physics Letters, 94,

053511, (2009). 11. CW Lee, et al., Comparison of contact resistance between accumulation-mode and invrsion-

mode multigate FETs, Solid-State Electronics, 52, 1815-1820, (2008). 12. CW Lee, et al., Performance estimation of junctionless multigate transistors, Solid-State

Electronics, 54, 97-103, (2010). 13. CW Lee, et al., Low subthreshold slope in junctionless multigate transistors, Applied Physics

Letters, 96, 102106, (2010). 14. JP Colinge, et al., Reduced electric field in junctionless transistors, Applied Physics Letters,

96, 073510, (2010). 15. JP Colinge, Quantum wire effects in trigate SOI MOSFETs, Solid State Electronics, 51,

1153-1160, (2007). 16. A Marchi, et al., Investigating the performance limits of silicon-nanowire and carbon-

nanotube FETs, Solid-State Electronics, 50, 78-85, (2006). 17. A Afzalian, et al., Quantization effect in capacitance behavior of nanoscale Si MuGFETs,

Proceedings EUROSOI Conference, 133-134, (2009). 18. T Poiroux, et al., Multigate silicon MOSFETs for 45 nm node and beyond, Solid-State

Electronics, 50, 18-23, (2006). 19. A Afzalian, et al., Three-dimensional NEGF simulations of constriction tunnel barrier silicon

nanowire MUGFETs, ECS Transaction, 19(4), 229-234, (2009). 20. E-Beam Lithography, Unpublished document from the Tyndall National Institute, Accessed

on April 19, 2010, <http://www.tyndall.ie/PDFs/ebeam.pdf>. 21. The world's first junctionless nanowire transistor, Nanotechnology Now, Feb. 22, 2010,

<htp://www.nanotech-now.com/news.cgi?story_id=36889>. 22. L Ansari, et al., Simulations of gated Si nanowires and 3-nm junctionless transistors,

Condensed Matter, arXiv:1003.4631v1 [cond-mat.mes-hall], (2010).

the junctionless transistor - george j. ferko v

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