the leading edge of production wafer probe test …...paper 41.1 ieee international test conference...

Paper 41.1 IEEE INTERNATIONAL TEST CONFERENCE 1168 October 26 to October 28, 2004, Charlotte, NC

THE LEADING EDGE OF PRODUCTION WAFER

PROBE TEST TECHNOLOGY

William R. Manna, Frederick L. Taberb, Philip W. Seitzerc, and Jerry J. Broz, Ph.D.d

a - SWTW General Chair and Rockwell International (retired), Newport Beach, CA 92663 b - BiTS Workshop General Chair and IBM Microelectronics (retired), LaGrangeville, NY 12540 c – Distinguished Member of Technical Staff, Agere Systems, Allentown PA 18109 d - SWTW Technical Chair and International Test Solutions, Reno, NV 89523

Abstract Microelectronic wafer and die level testing have undergone significant changes in the past few years. This paper’s first section describes today’s leading edge characteristics for numerous areas of this test technology including the minimum I/O pad pitch, advances in contactor technologies, maximum number of I/Os probed, maximum number of die tested in parallel, the largest prober and substrates, and the maximum frequencies being tested at the wafer level. The second section will discuss the leading edge practices in three critical areas of wafer test: probe contactor cleaning, I/O pad damage minimization, and sorting good from bad die. The final section will present the communication methods between the design and the probe test organizations and some state-of-the-art examples for I/O pad designs..

1. Introduction Testing the individual die at the wafer level, often called probe or sort, has been an integral part of the IC manufacturing process for over four decades. Yet relatively recent events have significantly changed this test technology and the associated tooling. The rapid succession of reduced geometry new processes has enabled much more complex ICs to be designed with little increase in area. The ICs have higher performance, wider I/O busses, and need more I/O pads dedicated to power and grounds. For conventional perimeter I/O pad designs, the pad pitch, or minimum distance between pads, has been reduced requiring more and smaller probe needles. There has also been a recent trend to Area Array designs, where the I/O pads are placed over the entire die surface rather than being restricted to the perimeter. This I/O pad configuration, when coupled with flip-chip die attach, provides lower parasitic impedance than wire bonds. It also improves thermal package performance, so it is now used with the all the major high performance microprocessors and many other high speed devices. The

perimeter to area I/O pad layout design transition has required a probe tooling transition to what is known as “vertical probe cards.” What was once a probe technology used almost exclusively by IBM (they patented their vertical Cobra Probe technology in 1977 [1]), is now available from many probe card suppliers and is being integrated into numerous semiconductor wafer probe organizations and subcontracted test facilities.

In addition to the changes in the physical attributes of probe cards, the electrical requirements have become increasingly challenging. The demands for improved final test yields and for Know Good Die, often used in Multi-Chip Modules, have required more thorough die level test conditions. This situation has occurred at the same time the chip I/O frequencies have increased, and the I/O signal levels have decreased. Low cross coupling between adjacent probe needles, high current requirements for individual contactors, and low noise and even controlled impedance traces on the probe cards are now commonplace. Not surprisingly, these new requirements have been met with new probe card and contactor technologies. While they have enabled more thorough die testing, they also represent additional technologies that must be integrated into production environments and supported with new metrology equipment and staff training.

Finally, reducing the cost of test has increased parallel die probing. This technique has been used for over a decade in memories chips, but it has now become a routine requirement for most logic, mixed signal, and other devices in high volume production. Automatic Test Equipment requirements, probe test programs, probe test tooling, and even device I/O pad layouts have all undergone a transition because of parallel die testing.

1.1 What Do We Mean by Leading Edge? We describe the most advanced probe test tooling and practices specifically being used in a production


environment. Therefore, we have chosen to consider only those leading edge characteristics that are in relatively high volume production or under production evaluation. Prototypes and beta samples don’t count. We discuss what “is being done,” not “what could be done” nor “what the technologies are capable of doing.”

The time frame for our study is early in the 2004 calendar year. Major probe card and equipment companies were contacted and asked what leading edge tooling characteristics they were supplying to the semiconductors in production. They also provided information for many other sections of this discussion including some of the best practices used by their customers. Some IC manufacturers were directly contacted, and they provided interesting “off-the-record” information. While they were each proud of their accomplishments, and agreed to have them discussed, they wanted their identity kept confidential. Therefore, the individual leading edge elements will not be linked to a specific IC manufacturer unless their accomplishments are in the public domain or their company has approved the information release. The probe tooling and equipment manufacturers, on the other hand, were eager to brag.

The “Leading Edge of Probe Test Technology” was presented at the IEEE Southwest Test Workshop in June of 2004. This TTTC sponsored conference specializes in wafer test technology, and it attracted 406 wafer test professionals. It is a broad technology forum with about 50% of the attendees from probe test tooling or service companies. There were numerous and lively discussions during and after the workshop which resulted in updating much of the data in this paper. Other sources of information include the International Test Conference Proceedings, the VLSI Test Symposium Proceedings, and the Southwest Test Workshop web site, www.swtest.org, which includes an archive of the last eight years of presentations.

1.2 Background Information Figure 1 is a picture of a typical probe test cell including the Automatic Test Equipment (ATE) and a prober. Enlarged pictures of other key hardware elements have been inserted. The ATE stores the Device Under Test (DUT) stimulus and correct response. These signals are routed to and from the DUT via a Test Head in close proximity to the DUT. In the figure, the black test head is sitting directly on top of, or docked to the prober. For many of the leading edge technologies, the probers maintain “localized” clean room environment. The prober holds the wafer being tested on a vacuum chuck. The chuck moves in the horizontal x-y directions positioning the individual die on the wafer in the center of the test head.

The Prober Interface Board (PIB), sometimes called the DUT Load Board, connects to the bottom side of the test head. This PIB routes the tester channels to the specific DUT I/O pin, and it can provide DUT loads, power supply decoupling, and other DUT specific components. Below the PIB, in the stack of tooling underneath the test head, is the Spring Contactor Assembly. The PIB is hard-mounted to the test head and the probe card is hard-mounted to the prober, so the Spring Contactor Assembly must provide a little vertical compliance and theta rotation as well as routing the test signals. The bottom element in the stack is the probe card. It has connectors or pads on the top side mating to the Spring Contactor Assembly and needles on the bottom side that physically contact the I/O pads on the individual die being tested.

1.2.1 I/O Pad Configurations It is important to understand the various I/O pad configurations used on the die surface to appreciate some of the leading edge parameters. Figure 2 illustrates the three most common pad layouts. The first is the conventional perimeter layout used on the majority of designs today. Sometimes there is a second row with pads interstitially (staggered) placed with respect to the first row of pads. The I/O pads are restricted to the perimeter of the die. These pads are the targets for the probe needle contactors, and the same pads are connected to the final package I/Os by conventional bond wires.

The next configuration is that of Area Array designs. In this configuration, the I/O pads are uniformly spread over the entire surface of the die. IBM initially developed this pad layout concept in the 70s in conjunction with their flip chip packaging technology. The round ball in the center of each pad represents a solder ball, and most manufacturers probe the die after the solder ball has been added to the I/O pad.

The third configuration is commonly used for large memory devices. It is often called Line-On-Center as the pads are in one line in the center of the die.

For some devices, various combinations of the aforementioned bond pads types are used. In some cases, rows of “sacrificial” probe pads are used to evaluate the performance of the device or the integrity of the interconnect. However, these pads are not wire bonded or bumped with solder balls in the final package.

1.2.1 Typical Probe Cards

Probe cards hold the contact elements (needles, wires, etc.), which make contact to the I/O pads, and provide the signal routing to the Automatic Test Equipment. Over the past four decades the cards and contactors have evolved greatly, but we only illustrate three of the most common.


ATEProberInterface Board

Probe Card

Prober

Spring Contactor Assembly


Probe Card

Prober


Probe Card

Prober

Spring Contactor Assembly

Figure 1 – Wafer Level Testing “Test Cell” (Courtesy of Agilent Technologies).

Conventional Perimeter

AreaArray

MemoryLine-On-Center

Conventional Perimeter

AreaArray

MemoryLine-On-Center

Figure 2 – I/O Pad Layouts.

By far, the most widely used type is known as the epoxy ring and cantilever needle card, and they represent about 85% of the cards in use today. A photograph of a typical card is show in Figure 3. The shaft of each needle is

held in place by an epoxy ring. Towards the center of the card, the needles are bent at an approximate 90-degree angle to face the wafer. During the fabrication process, the tips of the needles are usually held in place


by a template with holes corresponding to the location of I/O pads, the shafts of the needles are set into an epoxy mold, and epoxy is added and cured. The epoxy structure containing the needles is then attached to the probe card, and each needle is soldered to the appropriate PCB trace on the probe card (not shown in the photograph).

Figure 4 illustrates the initial IBM vertical card for area array I/O pad configurations. In this design, the needle contactors are attached to the probe card directly above the I/O pads, one needle per pad. The figure is in only one dimension, but the actual card consists of an x-y array of needles. The lower end of each needle is held in place by an insulating guide plate, with slightly over-size hole to position the needle tip but allow it slight movement. The upper end of the needle is securely fastened to an insulating plate, and wires electrically connect the needles to the traces on the PCB probe card. This structure is called a Space Transformer since it transforms the fine pitch needles to the looser pitch on the probe card. The needles bend slightly under compression, or buckle, which gave the technology the name of “buckling beam.”

IBM initially licensed their patent to Wentworth Laboratories. When the IBM patent expired in the mid-nineties, and some IC manufacturers began a transition to the improved performance of flip chip packages which required area array I/O pad designs, many probe card suppliers developed their own vertical probe card technology. One advance in the technology has been the replacement of the space transform wires with a multi layer ceramic (MLC) substrate. Often the device ceramic package is used since it has the exact layout needed to match the I/O solder balls. The MLC package is connected to the bottom of the probe card, and vertical needles make contact to the pads inside of the package.

Figure 5 is a photograph of a membrane probe card. This technology was developed in the late 80s, and it was the first time the I/O contactors were photo lithographically defined rather than being positioned by probe needle templates or fixtures. A thin flexible membrane is plated with one or more conductive metals, and then the image of the contactors and conducting traces are photo lithographically exposed, developed, and the unwanted material is etched away. Additional plating and etching provides appropriate characteristics for the I/O contactors. The membrane is then stretched over a truncated pyramid structure, and the structure is

held in place to the PCB probe card by a spring assembly to allow a little vertical compliance. The I/O contactors are at the top, and the membrane traces are electrically connected to the PCB probe card at the bottom of the photograph. The photo also shows how small surface mount power supply decoupling capacitors and other devices can be mounted on the membrane in close proximity to the DUT.

2. Leading Edge Probe Parameters

This section presents some of the leading edge physical characteristics of probe cards, and it describes the maximum frequencies being tested at the wafer level.

2.1 Contactors Needles, made from tungsten, Paliney 7®, tungsten-rhenium, beryllium-copper, and other alloys, have been the most widely used contactor elements, and they have served the industry well for many years. However, they have a few basic disadvantages. For the most part, needle based probe cards are manually assembled and adjusted by skilled operators and technicians. This feature has limited their accuracy, although clever fixtures and procedures have enabled tip placement accuracy down to the tens of microns. Secondly, the cost of these cards is directly proportional to the number of needles. Finally, as the I/O pad pitch has been reduced, the needles have gotten smaller and more fragile. Thus, higher pin count, finer pitch probe cards also have a shorter lifetime, and the cost per touchdown has significantly increased.

New batch processed contacting elements and probe card assemblies are now becoming the leading edge; however, the transition is very slow (remember, greater than 85% of the cards are still epoxy ring, cantilever needles). The two leading technologies for the new generation of contactors are micro springs and Microelectronic Mechanical Systems (MEMS), or a combination of both. Figure 6 has four photographs of the micro spring type contactors from four different companies. The small springs of the FormFactor contactors are formed by numerically controlled wire bonders, and the others are basically photo lithographically defined. Figure 7 illustrates four representative contactor types defined by MEMS processes. The attachment of the contactors to the probe card is done by numerical controlled machines or as a part of the contactor definition process.


Figure 3 – Epoxy Ring, Cantilevered Probe Card.

WAFER

Probe Card

Space Transformer

Insulator Block

Vertical Needles

Guide Plate

WAFER

Probe Card

Space Transformer

Insulator Block

Vertical Needles

Guide Plate

Figure 4 – Vertical Style Probe Card.


Figure 5 – Core of a Membrane Probe Card (Courtesy of Cascade Microtech).

JEM HAWKFormFactor

Advantest LabsSumitomo

JEM HAWKFormFactor

Advantest LabsSumitomo

Figure 6 – Compliant Spring Type Contactors (Courtesy of respective manufacturers).


PhicomFormFactor

AMST Microfabrica

PhicomFormFactor

AMST Microfabrica

Figure 7 – MEMs Type Contactors (Courtesy of respective manufacturers).

Figure 8 – Biggest Prober currently used in Production is the MJC TP 4700 (Courtesy of MJC).


Both of these technologies are designed to be “correct by construction,” so they do not require any manual adjustments, and they have contactor accuracies far superior to conventional needle technologies. They are batch processed so their cost base is somewhat independent of the number of contactors. However, at present these technologies are still much more costly than the older needle technology for low pin count cards.

2.2 Minimum Pitch The probe card pitch is defined as the minimum center-to-center distance between two adjacent probe tips. It is usually the same pitch as the minimum distance from I/O pad to pad; however, sometimes not every pad has a probe point, and sometimes the large power pads have multiple parallel probe tips or an extra tip used for a Kelvin connection. Table 1 lists the some of the leading probe card suppliers, and it identifies the minimum pitch in microns for the three different I/O pad layouts previously described. The probe card technology, or the marketing product name, is listed before the pitch (ECN = Epoxy Cantilever Needle, MEMS = Microelectronic Mechanical System, MEMB = Membrane).

The minimum pitch on conventional epoxy ring cantilever needle cards is from 35 to 40 microns. For parallel die probing, line on center cards can be made down to about 50 microns with cantilever cards, but they require a larger pitch for the newer technologies capable of a more DUTS in parallel. For the single die area array matrix configuration, the minimum pitch is slightly over 100 microns.

2.3 Highest Pin Count Table 2 lists a few of the leading probe card suppliers and the highest pin count cards they have in production. The highest pin count for a single Area Array die is 5700, and it appears that two suppliers build the card for the same IC manufacturer. For parallel probing of multiple DUTs, logic chips and/or memory, FormFactor is the undisputed leader with an almost 10,000 pin card probing 263 DUTS. This is their PH 150 card, and it is probing a complete 300 millimeter wafer in six touchdowns!

Company Perimeter Parallel Memory (Line-On-Center)

Area Array Square Matrix

FormFactor ----- MEMS 170 µ BladeRunner 175 µ

JEM ECN 35 µ HAWK 80 µ VSCC 138 µ

K & S ECN 37 µ Cobra 105 µ Cobra 105 µ

MJC ECN 47 µ ECN 50 µ -----

Wentworth ECN 50 µ Cobra 100 µ Accumax 135 µ

TCL ECN 48 µ ECN 48 µ -----

MicroProbe ECN 42 µ Apollo 100 µ Apollo 120µ x 115µ

SV Probe ECN 37 µ ECN 80 µ Hybrid ECN 125 µ

Phicom ECN 90 µ MEMS 90 µ -----

Cascade Microtech MEMB 50 µ ----- -----

Table 1 – Minimum Probe Card Pitch.

2.4 Biggest Prober and Substrate The largest substrates being probed today are the Generation 6, Liquid Crystal Display panels. They are 1.5 meters by 1.85 meters in dimensions and less than 1 millimeter thick. Each LCD panel has 6000 I/O contactors with a 60 micron pitch in an L-shaped configuration. They are handled and processed, 25

panels at a time, in very large “cassettes.” The cassette holder and prober are shown in Figure 8, but the photograph is deceiving. There are two types of equipment mated together in the photograph: in the background is the cassette holder, and the stack of LCD panels inside the cassette can be seen; and in the foreground is the largest prober in the world, the MJC TP- 4800 from Micronics Japan Corporation. The


prober alone is 4.5 by 4.5 meters, it is 4 meters tall, and it weighs 15 tons! MJC already has an even bigger prototype prober for the G7 LCD panels (2.2 m by 2.4

m) to be released at the end of 2004, but prototypes don’t count.

Company Parallel Testing Area Array

JEM 4860 for 64 DUTS 5000

Wentworth 4480 for 64 DUTS 5700

K & S 3000 for 64 DUTS 4264

TCL 1248 for 32 DUTS ----

MicroProbe 1800 for 32 DUTS 5700

MJC 4672 for 64 DUTS -----

SV Probe 800 for 160 DUTS 3000

FormFactor 9867 for 253 DUTS -----

Table 2 – Largest Pin Count Probe Cards.

2.5 Highest Frequency To discuss the highest frequencies being tested at the wafer level, we have chosen to present the data in four different product or application areas, each with different characteristics and attributes: conventional digital chips; consumer RF devices; high speed telecom chips; and process control monitors. The driving forces behind the high frequency test conditions vary. One reason is to provide thorough testing, reject bad devices as early in the manufacturing process as possible, and achieve high package test yields. Another reason is due to the demand for Known Good Die, when customers buy chips at the die level and insist on thorough, full specification limits for the probe test conditions.

2.5.1 Digital Chips This device class is best characterized by very fast dv/dt requirements and the use of conventional digital Automatic Test Equipment. The highest frequency being used is on the order of 800 MHz for the second generation graphic RAMs (GDDR II). These devices need a relatively wide data bus, and yet they are put in limited pin count, low cost packages, so they do not have differential data drivers and receivers. However, they do have differential clocks. They also have a selectable source and termination impedance to optimize the integrity of the high frequency signals, and they are being tested with both specially laid out cantilever needle and membrane probe cards.

2.5.2 Consumer RF Devices Cell phones components, digital cordless telephone chips, and the Bluetooth and IEEE 802 standards have

stimulated the high frequency RF consumer market. These devices are characterized by only a few, single ended, controlled impedance, modulated sine wave signals, and they are usually being tested on RF or RF/mixed signal ATE. Most RF chips are being tested at the die level with relaxed limits due to the difficulty of getting high frequency signals to the die. However, the vertical integration of RF design technology, with digital control circuits on the same die, has required thorough wafer level testing to achieve high, cost effective package yields. Furthermore, the product miniaturization with multi-chip modules for complete transmit/receive radios in one package is also requiring full specification die testing for RF components. The highest frequency today is on the order of 7 GHz to handle the third harmonic of devices in the 2.4 GHz frequency band. Although there are numerous higher frequencies commercial RF chips in the radar and 5.2 GHz bands, they have not needed the full RF test conditions as yet, but it’s only a matter of time.

2.5.3 Telecom Devices The most challenging aspect of probing telecom devices, used at the edge or within the Internet, is the very high speed of the primary data I/Os. These signals are from low voltage or current mode differential drivers and feed balanced receivers. Serailizer/Deserializer devices, known as SERDES, are now being probed at 4 GHz with specially laid out epoxy ring, cantilever needle cards and ATE. The testers can’t handle the device speeds, so there are the balanced drivers and receivers on the device under test load board or probe card, and extensive digital loop back Design For Test modes are included in the chips to facilitate testing. The highest frequency being


Figure 9 – Process Evaluation Monitor Scribeline Structures.

Figure 10 Membrane Card for 40 GHz Process Control Monitors (Courtesy of Cascade Microtech).

probed today is for the 40 Giga Bits Per Second SONET OC 768 devices. They are using membrane probe cards, rack and stack test equipment, and require a 60 GHz bandwidth to test the signals with 12 – 15 pico second edge transitions.

2.5.4 Process Control Monitors Wafer fabrication process control requires special electrical test structures on individual die or within the scribe lanes or streets (sometimes called the kerf) between die. Figure 9 is a photomicrograph of one such structure in the scribe lane. These structures are sampled

within and at the completion of wafer fabrication, usually a few wafers per lot, and a few devices per wafer. New processes with increasing transistor performance have necessitated the testing of some of these structures in the RF band. In particular, some Gallium Arsenide and Silicon Germanium processes manufacturers are now testing full transistor S-Parameters at 40 GHz. Figure 10 is a photograph of a membrane probe card with controlled impedance, strip-line traces to enable this level of testing.

3. Leading Edge Practices


3.1 Probe Contactor Cleaning One of the oldest problems with probing microelectronic wafers is the constant need for cleaning of the contact elements on the probe card. As illustrated in Figure 11 the need is apparent when you test a large number of wafers without cleaning the probe card [2]. The x-axis is the normalized yield of each wafer, and the y-axis is the wafer number for the 160 wafers tested. There are normal wafer-to-wafer yield variations expected, but it can be seen that the wafer yields are well below average until the probe card contactors were abrasively cleaned for the first time at wafer number 65. The yield increases above average for a number of wafers, but then declines slightly as debris accumulates on the needle tips. The card is abrasively cleaned again at wafer number 100, and the yield increases again. The card is cleaned for the final time in the experiment at wafer number 125, the yield increases above average, and then it gradually declines again. Not surprisingly, this yield roll off is highly correlated to an increased resistance from the needle to the wafer surface, and measuring this

contact resistance, or CRES as it is called, has become the most significant parameter used in the evaluation of various cleaning materials and methods.

Abrasive on-line cleaning has been the primary technique used to control CRES for many years. The cleaning operation is performed during the wafer probing process as the wafer chucks within the probers have an area where cleaning materials can be located. Probers can be programmed to have the probe needles make contact to the cleaning material after a pre-selected number of die or wafers have been tested. For this type of cleaning, the probes are burnished multiple times on a lapping film (0.5, 1, 3, or 5-µm grit), a tungsten-carbide plate, or a ceramic block. Each time the probes are cleaned, the tips are subjected to frictional shear stresses, material is removed, and the contact surface is damaged until the probes are eventually “worn” out of specification. Particulates, bond pad metal, or probe material left on the abrasive pad from the previous cleanings can adhere to the probe tips and then be re-deposited onto the wafer.

160 Wafers Probed

-10

-5

0

5

10

Abrasive Clean Abrasive

Clean Abrasive Clean

160 Wafers Probed

-10

-5

0

5

10

Abrasive Clean Abrasive

Clean Abrasive Clean

Figure 11 – In-Situ Abrasive Cleaning [2].


WRe

P7

BeCu

W

Initial Probe Needles After 100K Cleans!!!

WRe

P7

BeCu

W

WRe

P7

BeCu

W

Initial Probe Needles After 100K Cleans!!!

Figure 12 – Abrasive Cleaning of Cantilevered Probes. (Courtesy of International Test Solutions).

Debris Collection Material

SubstratePolishing Polymer or Foam

Adhesive

Probe TipInsertion

Debris Collection Material

SubstratePolishing Polymer or Foam

Adhesive

Probe TipInsertion

Figures 13 –Semi-abrasive probe cleaning materials are a combination of several layers; however, not all the cleaning materials have the structure shown in the figure.


Probe Tip Inserted into Cleaning PolymerProbe Tip Inserted into Cleaning Polymer

Figure 14 –Leading Edge On-line Cleaning Practices and Results (Courtesy of International Test Solutions).

Although abrasive cleaning has worked relatively well in the past, the overall process has been empirically determined. As such, the cleaning material and cleaning frequency vary widely from company to company, and there are also different protocols used between probing at ambient versus elevated temperature. Figure 12 is a comparison of four different types of needles before and after 100,000 touchdowns on the most commonly used 3-µm grit abrasive lapping film. There must be a careful balance between effective abrasive cleaning to maintain die yield, and excessive needle cleaning, which reduces probe card life.

Many probe card technologies developed for fine pitch devices are built with materials that cannot withstand severe frictional shear loading or contact surface deformation against a burnishing pad. For these technologies, a non-destructive, low impact cleaning technique that effectively collects debris and cleans the contact surface is needed. Today, the leading edge cleaning practices use semi-abrasive materials, which clean and collect probe generated debris as shown in Figure 13. For some of these applications, a polymer or foam material contains polishing particles, which dislodge debris, polish the contact surface and can actually reshape the probe needles. This material can be

mounted on a substrate, the prober cleaning unit, or a wafer. Various forms of “tacky” and semi-abrasive cleaning materials are currently being supplied by ELMO, International Test Solutions, JEM-America, MIPOX, and MJC.

Figure 14 shows a cantilevered probe needle tip before and after utilization of the leading edge on-line cleaning practice of the semi-abrasive polymer material.

3.2 I/O Pad and Solder Ball Deformation Conventional epoxy ring cantilever needles have always scrubbed or slightly deformed the I/O pads in the same general area that the wire bond is made for final packaging. This situation wasn’t a serious problem until the I/O pads and the wire bond got smaller, and the I/O pad deformation started adversely affecting the wire bond adhesion. Some companies experience a final package test yield loss as the bond wires were dislodged during the plastic molding process, and there were fears of field reliability issues.

Optical probe card analyzers, which were initially developed to insure the needle mark was in the center of the I/O pad, were used to determine and characterize the percentage of the I/O pad ‘damaged’ by the probe


needles for various probing experiments. The percentage of I/O pad damage was reduced by careful control of the needle scrub mark over drive, parallelism between the probe cards and the probe chuck, and tighter specifications for the probe card planarity (the difference between when the first probe needle hits the wafer and the last needle makes contact) [3, 4, 5].

These steps mitigated the problem for a while, but the transition to even smaller I/O pads, copper metalization, and low-K dielectrics underlying the I/O pads made the problem worse. As the pads got smaller, the needles had to get smaller and sharper, and they exerted a larger force per unit area. If the needles gouged through the top aluminum metal layer and exposed the underlying copper, inter metallic properties would now adversely affect the wire bond adhesion and reliability. Furthermore, active circuitry was being placed under the I/O pads, and the low-k dielectrics had significantly different properties than the previous dielectrics. Minimizing I/O pad damage, exposure of underlying metallurgy, and fracture of underlying circuitry again became a major problem.

As before, tighter specifications and better probe operating procedures improved this situation for cantilever needles. But new probe card technologies, such as vertical and membrane contactors, now represent the leading edge in achieving minimal I/O pad damage. Figure 15 compares typical scrub marks between conventional cantilever needles and membrane contactors, and Figure 16 compares a cantilever needle and vertical needle contactor scrub mark.

I/O damage to solder balls for area array flip chip designs has also been an ongoing problem. For various reasons, area array configuration die are usually probed after the solder balls have been attached. Excess solder ball deformation, as seen in Figure 17, can dislodge the ball during probing, cause poor adhesion to the package substrate when the die is reflow soldered, or trap contaminates in the final package assembly and cause a reliability problem. As was the case with cantilever needles, careful controls of the vertical card probing process, the tip geometry, and tighter vertical probe card specifications have been used to minimize the deformation.

The leading edge in minimal deformation appears to have been achieved with the Intel-FormFactor-TEL

probing processes as described in their joint presentation at the 2003 Southwest Test Workshop [6]. FormFactor developed a new vertical probe needle called Blade Runner, illustrated in Figure 18. These vertical needles appear to be a modification of the earlier spring design, and the new design allows a finer pitch. However, they have a larger vertical force per unit over drive, so they could significantly deform the soft solder ball. FormFactor, Intel, and the TEL prober application engineers collaborated to develop a novel prober motion to insure solid needle contact but minimize the force. Like most probers, the stage and wafer is raised vertically until the needles make contact to the solder balls. Then, as illustrated in Figure 19, the chuck moves diagonally, up and to the left, insuring a good contact but reducing the vertical force on the solder ball. Figure 20 compares the deformation mark on a solder ball between the conventional probe method and their low force technique.

3.3 Sorting Good From Bad Die In the “Good Old Days” good die were sorted from rejects by one relatively simple probe test. The test equipment applied an input stimulus to the die under test, and the tester compared the output response with the response of a known good circuit. If it had the incorrect response, a drop of ink was immediately dispensed in the center of the die, through the hole in the top of the probe card and in between the needles making contact to the perimeter I/O pads of the die. In the final packaging process, the wafer was sawn or scribed to separate the individual die, and only the good die, without an ink dot, were removed for packaging and final test.

3.3.1 Spatial Relationships for Sorting Today’s leading edge sorting of die takes into consideration many more factors than the single, one-time pass/fail criteria of the probe test. Of course, the fundamental thoroughness of the single die test has improved with the use of scan Design For Test methods, more comprehensive automatically generated test patterns, built in self test, the implementation of Iddq test screens, and other new test techniques and methodologies. However, it has been found that the spatial relationships of good and bad die on a wafer can be used to improve the effectiveness of die sorting. The location of a particular die, the test results of its


Conventional Epoxy Ring

Membrane Scrub Marks


Membrane Scrub Marks

Figure 15 – Membrane Scrub Marks (Courtesy of Cascade Microtech).


MicroprobeApollo (vertical)

Figure 16 – Vertical Scrub Marks (Courtesy of Micro Probe).


Figure 17 – Solder Ball Probe Deformation (Courtesy of IBM).

Figure 18 – FormFactor Blade Runner (Courtesy of FormFactor).


1 – Prober Chuck Moves in Z-axis2 – Contact with Flip Chip Bump3 – Chuck moves diagonally

1Wafer

2

3

1 – Prober Chuck Moves in Z-axis2 – Contact with Flip Chip Bump3 – Chuck moves diagonally

1Wafer

2

3

Figure 19 – MicroForce Probing Technique Developed by Intel, TEL, and FormFactor to reduce solder ball damage.

MicroForce Probing

Pb/SBump

Standard Probing MicroForce Probing

Pb/SBump

Standard Probing Figure 20 – Solder Ball Probe Mark Comparison (Courtesy of Intel).

neighbors, and the history of test results of the same locations on other wafers can be important factors in the

possibility that an individual die is bad, or unreliable, even if the test results indicated it was good.


There have been a number of excellent studies on what has been referred to as “Good die in a bad neighborhood” [7, 8, 9]. Intel presented a classic study in 1999 at the International Reliability and Test Symposium, which was awarded Best Paper for the conference [10]. Their study clearly demonstrated that “good” die in the neighborhood of poor yielding or zero yielding die, had a worse post burn in test yield than the average. By 2001, in their International Test Conference paper [11], they indicated they were rejecting questionably good die at the wafer test to improve their post burn in final test yield and overall product reliability. Philips described their spatial screening process for an optical image sensor device in Design and Test Of Computers Magazine in 2002 [12]. It was not cost effective to provide a full image test of the die at wafer level, so they were experiencing a less than desired final test yield after packaging. They developed a pattern recognition process that identified scratches and regional areas of probable bad die, rejected those device before final packaging, and were able to significantly improve their final test yields.

Making use of the spatial information has been made possible by significant equipment advances since the “Good Old Days.” The first improvement was the availability of positional information from the prober for the die being tested. Probers can now be programmed to go to a particular x-y die location on a wafer, they can test die a specific sequence, and they can provide the x-y location of the die when stepping in a uniform sequence. With the location of individual good and bad die available, it was no longer necessary to ink the die immediately after each die was tested. “Bad die maps” could be saved and inking performed after the entire lot had been tested. Figure 21 illustrates today’s leading edge probing sequence and data routing. Test results and the x-y location of the die being tested can be sent to a post-processing system. Various spatial screening algorithms can be incorporated into this system, and the bad die map can be sent to off-line inking equipment prior to packaging. The most advanced manufacturing flows skip the inking process altogether. The bad die map is sent directly to the equipment that picks the die up from the wafer after saw and attaches it to the lead frame or substrate.

3.3.2 Outlier Rejects The concept of rejecting outliers has become widely used in die sorting since the advent of Iddq testing. However, you must first determine the normal distribution in order to identify outliers. The distributions of normal test parameters, taken at one time during product characterization, can change from lot to

lot, or wafer to wafer, due to allowable process variations. Therefore, establishing preset outlier screening limits can be ineffective. In order to effectively identify current period outliers, you need to collect and analyze all the test data for one lot or one wafer. Referring back to Figure 21, parametric data from each die tested, process monitor test data, and defect density data can all be routed to the post-processing engine for analysis.

Researchers at Portland State University and LSI Logic studied the variation in the typical outlier parameters from die to die. Their goal was to reduce the variation, by post processing analysis, to easily identify outliers [13]. Figure 22 shows the Iddq variation across the face of a wafer, where darker color represents larger Iddq value. There is a noticeable donut shape pattern, so a die that might exceed the outlier threshold of the entire wafer could be consistent with the die in its localized region. The team decided to estimate the Iddq for each die by averaging the Iddq values of the surrounding die. Then they subtracted the measured value from the estimate, and called it the Nearest Neighbor Residual (NNR). They found significant variance reduction and were able to greatly improved outlier identification [14]. Their work earned them the Best Paper award for the International Test Conference in 2001. By 2002, they introduced a complete reliability focused Statistical Post Processing system for outlier identification and elimination, and they demonstrated a 30% to 60% reduction in Early Failure Rate for a 0.18 micron product [15].

At the International Test Conference in 2002, the same group extended their concept to Vdd minimum outliers [16]. As can be seen in Figure 23, Vdd min also can have a significant variation across the face of a wafer. But it can take extensive test time to determine Vdd min for every die, so the researchers first developed a method for testing with a reduced vector set and a binary search algorithm to achieve a reasonable impact on test time. The then applied their Nearest Neighbor Residual technique on the Vdd min data, and they were able to easily identify and eliminated the outliers.

By the VLSI Test Symposium in 2003, they had extended their work to Fmax NNR outlier identification using transition delay test vectors [17]. At ITC in 2003, the same group presented another method for predicting the Iddq of a good device [18]. They measured the Iddq at nominal voltage, then reduced the voltage to a sub-threshold level taking care not to change the device logic states, and then measured Iddq again. They could estimate the normal Iddq leakage at nominal Vcc by


ATE Prober ASSY

Post Processing of Wafer Probe Data

Off-Line

Inking

Fab & PCM data

Defect density & E-Test data

X-Y location

Go-No Go test data

Parametric test data Bad Die

MapDirect

“Inkless” Probing

ATE Prober ASSY

Post Processing of Wafer Probe Data

Off-Line

Inking

Fab & PCM data

Defect density & E-Test data

X-Y location

Go-No Go test data

Parametric test data Bad Die

MapDirect

“Inkless” Probing

Figure 21 – Leading Edge Probe Sequence and Data Routing.

Figure 22 – Iddq Versus Die Location (Courtesy of LSI Logic).


Figure 23 – Vdd Min Versus Die Location (Courtesy of LSI Logic).

SAMPLE BI Duration QUANTITY FAILURES

A 72 Hrs 140 0

B 72 Hrs 390 0

C 64 Hrs 48 2

D 24 Hrs 48 2

E 64 Hrs 48 0

F 24 Hrs 28 0

G 24 Hrs 11 0

H 64 Hrs 36 4

I 24 Hrs 61 3

Table 3 – Low Yielding Wafer Burn-In Experiment.

extrapolating the exponential relationship from the sub-threshold reading. They compared this estimate with the actual measured value, calculated the difference, and used the NNR to identify outliers. LSI Logic, with the help of their colleagues at Portland State University, represents the leading edge in outlier rejection at the die sort operation.

3.3.3 Rejecting Outlier Wafer The electrical test of the process control monitors (those test devices within the streets between the die) is one way to identify and reject abnormally processed wafers. But this is only a sample test, and there can be other single wafer related problems that adversely affect die quality or reliability, and they may not be detected by the


normal die test. The leading edge practice for this situation is to identify the outlier wafers by their substandard yield, and scrap or remove them from the lot for further analysis. The procedures and the low yield threshold for removal vary from company to company.

Table 3 presents the results of an experiment to validate the removal and scrap of wafers with less than 50% of the expected yield for one particular device type. This part was in relative high volume production (on the order of 250,000 unit deliveries per month), but it took six months to obtain nine wafers below this threshold. All the questionably good die, or samples of the good die from each wafer, were package and subjected various durations of 125OC burn in. Four of the samples had a significant post burn in failure rate, and the combined average was 13,580 PPM. During the same period, there was an ongoing Quality Monitor System where samples of normal production lots were also removed for a special burn in. Over two hundred lots were sampled, 5,914 total devices, they were burned in for 1008 hours at 125OC, and there were zero post burn in failures. Considering the significant reliability difference and the relatively small number of low yielding wafers, a scrap procedure was immediately instituted.

3.4 Voltage Stress During Test Some leading edge companies are applying a voltage stress during the test, and then retesting the device, in order to reduce Early Life Failures. The voltage stress levels and duration depend on the process and device, and there is very little written about this procedure [19]. One device manufacturer developed one such stress protocol for a 0.18 micron telecom device. They were experiencing about a 2,000 PPM Early Life Failure rate, they wanted to eliminate burn in to reduce the product cost, but they needed data to demonstrate the effectiveness to their customer.

The manufacturer decided on a one-second stress level so as not to excessively extend the test time, and they used a 1.5 X Vdd stress level (high enough to stress the week transistors but not enough to exceed the normal process voltage breakdown level). They were unsure of the most effective temperature at which the stress should be applied, so they split 5 lots, 112 wafers, three ways for an experiment. The first one-third was stressed at ambient temperature, and there were five stress-related failures out of 4989 tested. These failures were below the expected 2000 PPM, and there were additional failures during the post burn in tests.

The second one-third was stressed at 90OC, and this sample had 7 stress-related failures from 4966 devices. Unfortunately, this sample also had additional failures at the post burn in test. They decided to provide a stress at

both temperatures. They probed the last one-third sample at ambient temperature with the stress, and then provided another stress during final package test at 90OC. There were 12 stress related-failures, consistent with the 2000 PPM failure rate expectations, and there were zero failures during the post burn in test. They presented the data to the customer and eliminated the 100% production burn in.

4. Design Methodology & Communication In the early days of integrated circuit manufacturing, a probe test engineer didn’t need much information to complete a probe card design. Although the probe card was a great improvement over the manually positioned individual probes, it contained only a few probe needles, and they could still be re-positioned as needed to insure they were accurately positioned on the I/O pads. The situation today is quite different. It is not possible to design a probe card for today’s integrated circuits without some key information from the chip designer.

4.1 Communications with the Probe Card Designer It seems obvious that the Wafer Probe design organization needs the chip designer to provide all the information they require to build a production probe card. The amount of information is small compared to the huge files needed to describe a modern chip’s mask set, but it must be accurate, timely, and preferably contained in one place.

The list of absolutely required information is really quite short:

• The X and Y coordinate of the center of each pad to be probed.

• The X and Y dimension of each bond pad.

• A designation for each pad that is either power or ground.

• The chip dimensions.

• The “street” width between die.

In the “Good Old Days,” when bond pads were large, it was no problem to generate this information. Sometimes the coordinates could even be determined by “bomb-sighting” them, or manually measuring the distance from a reference point on the chip to the pad center using a measuring microscope with cross-hairs. Although time consuming, this procedure could be done by the probe engineer if no other information was available. It didn’t matter if there were errors of 20 or 30 microns in the coordinates because the probes could always be


“tweaked” toward the pad centers if they were out of alignment.

Today’s leading edge probe technology requires that this information be extremely accurate. Tiny bond pad sizes require the X and Y coordinates to be in the center of the bond pad, within one or two microns. Errors greater than this will use up the probe needle scrub margin, resulting in a probe card that performs poorly in production. Photo lithographic probe technologies, such as membrane cards, demand this accuracy and also require the power and ground designations to be absolutely correct. One power or ground probe which is misidentified as a signal probe can result in an expensive and long lead-time probe card that will not be usable.

Building an optimal probe card for today’s complex integrated circuits requires more than just the essential information previously listed. Because many designs now include circuitry under the bond pads (CUP), the probe card designer must understand the structure and behavior of the bond pad itself. This information is essential to determine the amount of probe force per unit area that can be applied without introducing dielectric cracking, which can become a reliability problem.

The probe card designer also needs to understand the properties of the bond pad material and composite structure, so the scrub length and penetration depth can be optimized for minimization of contact resistance without compromising reliability. Excessive damage to the I/O pad, either by too large a scrub area or by penetrating into the underlying metal, can have a negative impact on the quality and reliability of wire bonding. The real-world properties of the newest low-K dielectrics are still poorly understood, and that makes it even more difficult for the probe card designer to obtain the information he really needs. But, knowledge of the actual structure under the pads (materials, thickness, mechanical properties and layers) certainly helps.

It is also important to know the amount of power the device will dissipate during probing. Extra device cooling may be required to insure that the device temperature does not exceed specified limits. There are usually maximum current limits on each power and ground pin. The allowable voltage drop often dictates these maximums, but they may also be limited by the probe card technology. For example, excessive current can burn open the traces on a membrane probe card.

The probe card designer frequently needs to know specific information about the chip being tested. If certain pins are critical signals, he will need to know information such as impedance, matched signal pairs, termination requirements and maximum allowable capacitance during test. If special components such as

crystals, bypass capacitors, termination resistors or protection diodes are required, they must also be specified.

The size or shape of a bond pad can be important to the chip electrical requirements. This is critical for chips designed to operate at microwave RF frequencies, where the metal of the I/O pad may act as an electrical stub, adversely affecting the characteristics or performance of the chip. The I/O pad may also be part of an internal strip-line. Probing on the wrong part of the pad may produce erroneous test results because the impedance seen during test may be incorrect. The probe designer needs to know when the probe testing frequency is high enough that these conditions must be considered.

In some cases, the chip designer may also specify the type of tester to be used at probe and the specific tester resources that must be attached to a particular signal pin during probe. This information, which is most important to the test engineer who writes the test program, must also be known when the probe card is designed or specified.

4.2 Communications with the IC Designer Knowledge of probe card issues is not just the responsibility of the probe engineer. The chip designer needs to have a basic understanding of probe issues in order to produce a design that will be durable and cost effective in a manufacturing environment. An understanding of probe constraints can make the difference between a chip that is easy to probe and one that is totally un-manufacturable.

Every designer needs to understand that the probe I/O pads should always be as large as possible. The bigger the I/O, the easier it is to probe. It would seem that this should be obvious, but there are always design tradeoffs. Designers are constantly encouraged to reduce the size of the die. Chip area is money, and every micron saved on a chip dimension represents savings in the cost to produce a chip. Unfortunately for probe, this design goal influences the I/O pad designs, perhaps even more than it should.

Many chip designs are “bond pad limited.” This means that the minimum size of the chip is being constrained by the size and number of bond pads that can be arranged along the edges of the die, not by the area required by the circuitry. Bond pad limited chip designs will always use the minimum allowable pad dimensions and spacing. It is important that the designer know what those minimum dimensions are so they can be applied to the design without compromising probe or assembly. Even though a particular design is not bond pad limited and there is room for larger pads, designers have a tendency to use the minimum pad size and spacing. A designer


who understands probe issues will use larger pads wherever possible.

Some chip designers may also be able to influence the choices in bond pad construction (such as number of layers, material thickness and composition). This is not common, since these decisions are usually made when a new technology is initially defined. A specifically chartered team of process, device design, probe, and packaging engineers determines the optimum I/O pad configuration, metallurgy and dielectric stack, and allowable circuitry underlying the pads. This I/O pad structure is universally used for all designs in that process. The specific details of I/O pad configurations differ widely from company to company and process to process, and they is beyond the scope of this paper

4.3 The Reality of the Situation The Wafer Probe design organization needs all the information necessary to specify/build a production probe card. It would appear that this is a simple situation - the designer simply extracts the information from the chip design as part of the transfer to manufacture, bundles it into a standardized form so probe can use it, and transmits it to the Probe Organization. But, in reality, things are not so simple.

Designing a chip today is a very complex process. It is time consuming, can be frustrating, and requires intense attention to detail. Design teams are almost always on a very tight time schedule - driven by customer requirements and the extremely short “window of opportunity” for a new product to be profitably introduced before a competitor gets the market share. The last few weeks before design completion (known as “tapeout”) are hectic for the designers. Most are required to work extremely long hours during this period because the simulations and design checks require many around-the-clock hours to complete. Design teams are taxed to the limit and many significant last minute changes are often required. Simple changes such as swapping a signal pin with a ground pin frequently happen and sometimes may not be documented when the data for probe is extracted.

After tapeout, the design team is concentrating on the generations of test patterns, and some individuals may even be moved to the next design challenge. Details of updating the probe files or notifying the probe design organization can easily be forgotten. In reality, the probe card design information is not guaranteed to be accurate until the first wafers are probed, and by this time the necessary communication may be too late to be useful.

In many integrated circuit manufacturing companies, design teams are located in satellite locations - small

design offices that are located close to key customers. These designers rarely, if ever, get the opportunity to interact in person with the probe design organization. In addition to the physical separation, there may be barriers of language and time differences that add to the difficulty of communication.

Other innovations of modern chip design also make it difficult for the designer to provide probe with the necessary information. Many “systems on a chip” contain intellectual property (IP) that is simply purchased or licensed from another design company or manufacturer and “dropped” into position on the die. These IP “macros” usually include bond pads buried in their design that the chip designer is unable to modify. The physical construction and size of these pads often cannot be changed and may not even be known to the chip designer.

Because of the high costs of fabricating wafers, especially in the latest technologies, multiple prototypes are frequently combined into one mask set. This concept, known as the multiple project wafer or a shuttle run, results in the generation of prototype die that are located across the wafers spaced apart by multiples of the mask step distances rather than multiples of the die size. The chip designer probably will not know what the mask step distances are, so this information will not be available to the probe designer. This results in manufacturing delay until the correct distances can be determined.

4.4 Improving Communications Probably the easiest way to insure designers do not produce problems at probe is to develop a set of probe design rules and to insure an appropriate design rule check process. Almost all chip designs are required to be checked by physical design verification software without generating design rule violations. If the requirements of probe are stated in a set of probe design rules, it is relatively easy to add these rules to the verification software and insure that probe requirements are met.

A probe design rules set should include such requirements as minimum bond pad pitch and spacing, minimum distances from the edge of the chip and between rows and pad orientation. Restrictions on the total number of pads, perhaps as a function of die size, should be included. Additional rules can address pad structure requirements such as thickness and material sets. Requirements for corner pads also need to be specified, since the corner congestion is especially problematic for probe. All these rules can differ depending on the I/O pad configuration, such as perimeter, area array, memory line-on-center, etc. They


can also change for a given I/O pad configuration based on which probe card technology is used, or if multiple die are to be probed in parallel.

Unfortunately, it is difficult to develop a complete set of probe design rules that cover every case and are not unnecessarily restrictive. Some designs may violate certain of the design rules, yet the probe card design can still be simple and straightforward. A review process for designs that violate the probe rules is a necessity, and through this review process, frequently informally, the designer and the probe engineer learn and gain understanding of each other’s issues.

One method frequently used in many companies to improve communications between chip designers and the probe organization is the addition of a mandatory “Ready for Manufacture” design review meeting as part of the transfer to manufacturing. At this review there are representatives from device design, device technology, test, probe and package engineering, the quality organization and manufacturing locations. During the meeting, a ready-for-manufacture checklist is reviewed.

It requires the designers to respond to key probe questions, indicating such items as minimum bond pad size, chip power dissipation and number of pads to be probed. Information on the checklist allows the probe engineer to assess the manufacturing risk and to provide a mitigation plan for those areas of concern. Participation in these reviews has heightened the awareness of designers to many manufacturing concerns, including those of the probe organization.

5. I/O Pad Examples and Lessons Learned Chip designers and probe test engineers have developed significant improvements in the I/O pad layouts. However, designers have also introduced innovative ideas that were intended to reduce die area, but they did not understand the impact on manufacturing operations of wafer probe and wire bonding. In this section, we discuss the lessons learned and some of the leading edge I/O pad layouts.

Rp3

Rp1

Rp2

E2

E1

Rp3

E2

Rp1

Rp2

E1

Rp3

Rp1

Rp2

E2

E1

Rp3

E2

Rp1

Rp2

E1

Figure 24 – (a) An example of Triple-Staggered Bond Pads as Originally Designed, and (b) Triple-Staggered Bond Pads After Design Rules Applied.

5.1 Triple Staggered Pads When a chip design is bond pad limited, designers will do everything they can to squeeze the largest number of pads along each side of the die. One example of this effort was the introduction of “triple staggered pads”. A designer reasoned, “If I can’t get all the pads I need in two rows, why not add a third one?” The result of this reasoning is shown in Figure 24A. In the original design, the pads were arranged in three rows and the centerlines of the rows were spaced an equal distance

apart (E1 and E2 were equal). The pads were spaced so that the distances between centers were not less than a constant value (Rp1 = Rp2 = Rp3 = the minimum row pitch).

The original design simply could not be manufactured in the probe card technology that had to be used. It was impossible to build a probe card because the closeness of the rows prohibited meeting the probe force and scrub length requirements without having the “knees” of the probe needles touch each other. Additionally, it was impossible to wire bond to all of the pads due to the lack


of clearance between them. This problem was worse in the corners of the die because of the wire angle needed to bond between the chip pad and the package pad.

It was necessary to establish some design rules that were specifically applied to triple staggered pads. In order to build a probe card, the spacing between one of the rows and the other two had to be greatly increased. Dimension E1 would not be equal to E2; one of them would have to be significantly larger than the other. Also, the minimum spacing dimensions could not be the same in all three rows; the spacing of the middle row and the row nearest to it had to be larger than that of the remaining row. In this example, rules would require E1 to be much greater than E2, and both Rp2 and Rp3 would have to be larger than Rp1. The extra space obtained by following these rules allowed probe needle knees to be spaced far enough apart that they would not touch.

Additional rules had to be put in place in the corners to accommodate wire bonding. The dimension Rp in each row had to be increased at the ends of the rows. These rules caused the design to be “flex-staggered” rather than true staggered. The values for dimensions Rp were chosen to maximize the number of pads consistent with the requirements of wire bonding.

The result of implementing these rules, shown in Figure 24B, was a design that was manufacturable and still had more pads along a side than would have been possible with only two true staggered rows of pads.

5.2 Rotated Corner Pads Another interesting example of lessons learned can be shown in the case of rotated corner pads. Refer to Figure 25 for this discussion.

Consider bond pad A. This pad is located on the same centerline as a row of pads that are parallel to the left side of the chip. Consequently, its longer dimension runs left to right, perpendicular to the left chip edge. However, it also is located so that it is on the same centerline as pad B. Because of its location, it might be easier to design a probe card that included the probe for pad A in the same probe tier as that used for pad B. In the case of a multi-site shelf probe card, this might be the only option. A probe to contact this pad and scrub parallel to its long dimension would have to come in from the right side on at least one site. The probe would have to reach over the entire row of probes, including the probe for pad B. This single probe would either have a very long tip or it would short to the probe for pad B. But putting it in the same tier as the pad B probe would

cause the scrub to be parallel to the short dimension instead of the long one.

The solution to this problem was to establish a rule that required all corner pads to be square, and the dimensions of both sides must both be at least as long as the longer dimension of a non-corner pad. A corner pad is defined as any pad having a center that lies within the hashed area of figure 25. Dimension X is large enough to insure that the probe shorting problem will not occur. Another solution was to simply not place a pad in the corner if possible.

5.3 Probe Over Passivation There are numerous examples of the positive impact of collaboration between the chip designer, the probe test engineer, and the packaging engineer. The problem of I/O pad deformation by the probe needles was described in section 3.2. Freescale Semiconductor, previously the semiconductor division of Motorola, developed an interesting method to completely avoid the problem. They have expanded the I/O pad area up on top of the passivation layer in a process called Probe Over Passivation (POP) [20]. This design completely eliminates the probe and wire bond contention, and it can be implemented with only a one mask change. Since the probe portion of the pad is on top of the passivation, there is no chance of the needles punching through to the copper layer. The pad is enlarged toward the center of the die so there is also no increase in die size. Extensive testing had to be completed to insure the probe needle would not damage any underlying circuitry. These tests were successful, and this technique is being used on new designs, and some old designs are being retrofitted.

5.4 Staggered Pads for Parallel Probing Multi die parallel probing was initially used to reduce the probe cost for memory die, and now it is being used for most high volume logic devices at leading edge manufacturers. The parallel probe requirement can affect the die design. One interesting example occurred when the die was to have a single row of perimeter I/O pads on a minimum allowable pitch. Although a single die could be probed with a conventional epoxy ring cantilever needle card, probing four die in parallel, in a square array, exceeded the capabilities that technology.

A vertical probe technology had to be used to get access to the I/O pads in the interior of the four-die array. Yet the minimum pitch of a vertical card was much larger than the pad pitch for the initial perimeter configuration. Using a vertical card would require a staggered pad configuration, which would slightly enlarge the die and


X

X

BA

X

X

BA

Figure 25 – Development of the Corner Pad Rule.

Figure 26, Perimeter I/O Pads Redistributed Into Area Array Solder Bumps.

increase the cost. An extensive cost trade-off study was completed to compare the reduced cost of probe test with the increased die cost, and it was determined that the stager pad design with parallel die testing was the lower cost option.

5.5 Perimeter Pad Redistribution Chip designs usually begin with the I/O pad configuration defined to be compatible with a particular package type. Perimeter I/O configurations can be used with conventional wire bonding in low cost plastic quad flat packs (PQFP), or the same die can be bonded to a

laminate substrate for a ball grid array. Occasionally there is a marketing request for the same device in different package types with different I/O configurations required. For example, a low cost PQFP would require a perimeter I/O pad configuration whereas a thermally efficient ceramic Pin Grid Array package would require an area array configuration. Figure 26 is an interesting example of a product initially designed with perimeter I/O pads, and then and extra mask and metalization layer was added to route the perimeter pads to area array pads required for solder ball and flip chip packaging. This minimum design effort and an optional process step


enabled the same basic design to serve slightly different markets.

6. Conclusions We have presented some of the leading edge characteristics and practices used in the wafer test portion of the microelectronic device manufacturing industry. Only those elements that are being used in reasonably high volume production in early calendar year 2004 have been discussed. The authors wanted to provide the production leading edge performance rather than arguable “capabilities.” This information is time dependent, it will improve quickly, and there are many important characteristics we did not discuss. We apologize to those interested in specifics on the cost of probe, metrology, probe card tracking systems, probe productivity, maximum touchdowns for various probe card technologies, and the metallurgy and dielectric stacks underlying the I/O pads. The wafer test professional deals these and many more factors every day, but they were beyond the scope of this paper.

7. References [1] U.S. Patent 4027935, June 1977

[2] J.J. Broz J.C. Andersen, and R.M. Rincon, “Reducing device yield fallout at wafer level test with electro-hydrodynamic (EHD) cleaning”, International Test Conference, September 2000.

[3] G. Hotchkiss, G. Ryan, J. Broz, R.M. Rincon, S. Mitchell, R. Rolda, R. “Effects of Probe Damage on Wire Bond Integrity”, IEEE ECTC, 2001.

[4] G. Hotchkiss, J. Aronoff, J. Broz,, C. Hartfield, R. James, L. Stark, W. Subido, V. Sundararaman, and H. Test, 2002. “Probing and Wire Bonding of Aluminum Capped Copper Pads”, IEEE IRPS, 2002.

[5] W. Sauter, T. Aoki, T. Hasida, H. Miyai, K. Petrarca, F. Beaulieu, S. Allard, J. Power, and M. Agbesi, “Problems with Wire Bonding on Probe Marks and Possible Ssolutions”, IEEE ECTC, 2003.

[6] R. Martens, A. Abdelrahman, and S. Martinez, “MicroForce Probing for low-k ILD Testing,” Southwest Test Workshop, June 2003, www.swtest.org

[7] D. Larkin II, A. Singh, “Exploiting Defect Clustering to Screen Bare Die for Infant Mortality Failures; An Experimental Study,” International Test Conference, September 1999, pp 23-30.

[8] T. S. Barnett, A. Singh, and V. P. Nelson, ‘Burn-In Failures and Local Regional Yield: An Integrated Yield-Reliability Model,” VLSI Test Symposium, May 2001, pp. 326-332.

[9] T. Barnett, A. Singh, M. Grady, and K. Purdy, “Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction,” VLSI Test Symposium, April 2002, pp 75-80.

[10] W. Riordan, R. Miller, J. Sherman, and J. Hicks, “Microprocessor Reliability Performance as a Function of Die Location for a .25u, Five Layer Metal Logic Process,” International Reliability and Physics Symposium, 1999, pp 1-11.

[11] R.B. Miller and W.C. Riordan, “Unit Level Predicted Yield: a Method of Identifying High Defect Density Die at Wafer Sort,” International Test Conference, October 2001, pp. 1118-1127.

[12] C.C. Wang, C.J. Huang, and C.F. Wu, “Identification of Wafer Clustering Using Image Processing Techniques,” Design & Test Of Computers, March-April 2002, pp 44-48.

[13] W.R. Daasch, J. McNames, D. Blockelman, K. Cota, and B. Madge, “Variance Reduction Using Wafer Patterns in Iddq Data,” International Test Conference, October 2000, pp. 189-198.

[14] W. Robert Daasch, K. Cota, J. McNames, and B. Madge, “Neighborhood Selection for Variance Reduction in Iddq and Other Parametric Data,” International Test Conference, October 2001, pp. 92-100.

[15] R. Madge, M.Rehani, K Cota, and W. R. Daasch, “ Statistical Post-Processing at Wafersort: An Alternative to Burn-In and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies,” VLSI Test Symposium, May 2002, pp. 69-74.

[16] R. Madge, B. H. Goh, V. Rajagopalan, C. Macchietto, R. Daasch, C Schuermyer, C. Taylor, and D. Turner, “Screening MinVdd Outliers Using Feed-Forward Voltage Testing,” International Test Conference, October 2002, pp. 673-682.

[17] B. R. Benware, R. Madge, C. Lu, and C. Daasch, “Effective Comparison of Outlier Screening Methods for Frequency Dependent Defects on Complex ASICs,” VLSI Test Symposium, April 2003, pp. 39-46.

[18] C. Schuermyer, B. Benware, K. Cota, R. Madge,R. Daasch, and L. Ning, “Screening VDSM Outliers using Normal and Sub-threshold Supply Voltage


IDDQ,” International Test Conference, September 2003, pp. 556-573.

[19] R.C. Aitken, “Test Generation and Fault Modeling for Stress Testing,” International Symposium on Quality Electronic Designs, March 2002, pp. 95-99.

[20] B. Williams, T. Angelo, S.S. Yan, T.A. Tran, Stephen Lee, and Mat Ruston, “A 44 Micron Probe Process Characterization and Factory Deployment and Probe – Over – Passivation,” Southwest Test Workshop, June 2003, www.swtest.org.

the leading edge of production wafer probe test …...paper 41.1 ieee international test conference...

Documents