The MOS Transistor

Debdeep MukhopadhyayIIT Madras

Introduction• So far, we have treated transistors as ideal switches• An ON transistor passes a finite amount of current

– Depends on terminal voltages– Derive current-voltage (I-V) relationships

• Transistor gate, source, drain all have capacitance– I = C (∆V/∆t) -> ∆t = (C/I) ∆V– Capacitance and current determine speed

• Also explore what a “degraded level” really means

MOS Characteristics

• MOS – majority carrier device• Carriers: e-- in nMOS, holes in pMOS• Vt – channel threshold voltage (cuts

off for voltages < Vt)

nMOS Enhancement Transistor• Moderately doped p type Si substrate• 2 Heavily doped n+ regions

I vs. V Plots

• Enhancementand depletiontransistors– CMOS – uses

only enhancement transistors

– nMOS – uses both

Materials and Dopants

• SiO2 – low loss, high dielectric strength – High gate fields are possible

• n type impurities: P, As, Sb• p type impurities: B, Al, Ga, In

Bipolar vs. MOS• Bipolar – p-n junction – metallurgical• MOS

– Inversion layer / substrate junction field-induced– Voltage-controlled switch, conducts when Vgs Vt

– e-- swept along channel when Vds > 0 by horizontal component of E

– Pinch-off – conduction by e–- drift mechanism caused by positive drain voltage

– Pinched-off channel voltage: Vgs – Vt (saturated)– Reverse-biased p-n junction insulates from the

substrate

≥

MOSFET Transistors• MOSFET – For given Vds & Vgs, Ids

controlled by:– Distance between source & drain L– Channel width W– Threshold VoltageVt– Gate oxide thickness tox– dielectric constant of gate oxide ε– Carrier mobility µ

MOS Capacitor

• Gate and body form MOS capacitor• Operating modes

– Accumulation– Depletion– Inversion

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg < 0

(b)

+-

0 < Vg < Vt

depletion region

(c)

+-

Vg > Vt

depletion regioninversion region

Terminal Voltages• Mode of operation depends on Vg, Vd, Vs

– Vgs = Vg – Vs

– Vgd = Vg – Vd

– Vds = Vd – Vs = Vgs - Vgd

• Source and drain are symmetric diffusion terminals– By convention, source is terminal at lower voltage– Hence Vds ≥ 0

• nMOS body is grounded. First assume source is 0 too.• Three regions of operation

– Cutoff– Linear– Saturation

Vg

Vs Vd

VgdVgs

Vds+-

+

-

+

-

nMOS Cutoff

• No channel• Ids = 0

+-

Vgs = 0

n+ n+

+-

Vgd

p-type body

b

g

s d

nMOS Linear• Channel forms• Current flows from d to s

– e- from s to d• Ids increases with Vds

• Similar to linear resistor• At drain end of channel,

only difference between gate & drain voltages effective for channel creation

+-

Vgs > Vt

n+ n+

+-

Vgd = Vgs

+-

Vgs > Vt

n+ n+

+-

Vgs > Vgd > Vt

Vds = 0

0 < Vds < Vgs-Vt

p-type body

p-type body

b

g

s d

b

g

s d Ids

nMOS Saturation

• Channel pinches off• Ids independent of Vds

• We say current saturates• Similar to current source

+-

Vgs > Vt

n+ n+

+-

Vgd < Vt

Vds > Vgs-Vt

p-type bodyb

g

s d Ids

I-V Characteristics

• In Linear region, Ids depends on– How much charge is in the channel?– How fast is the charge moving?

Channel Charge

• MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

• Qchannel =

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate

Channel Charge

• MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

• Qchannel = CV• C =

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate

Channel Charge

• MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

• Qchannel = CV• C = Cg = εoxWL/tox = CoxWL• V =

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate

Cox = εox / tox

Channel Charge

• MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel

• Qchannel = CV• C = Cg = εoxWL/tox = CoxWL• V = Vgc – Vt = (Vgs – Vds/2) – Vt

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2 gate oxide(good insulator, εox = 3.9)

polysilicongate

Cox = εox / tox

Carrier velocity

• Charge is carried by e-• Carrier velocity v proportional to lateral E-

field between source and drain• v =

Carrier Velocity

• Charge is carried by e-• Carrier velocity v proportional to lateral E-

field between source and drain• v = µE µ called mobility• E =

Carrier Velocity

• Charge is carried by e-• Carrier velocity v proportional to lateral E-

field between source and drain• v = µE µ called mobility• E = Vds/L• Time for carrier to cross channel:

– t =

Carrier Velocity

• Charge is carried by e-• Carrier velocity v proportional to lateral E-

field between source and drain• v = µE µ called mobility• E = Vds/L• Time for carrier to cross channel:

– t = L / v

nMOS Linear I-V

• Now we know– How much charge Qchannel is in the channel– How much time t each carrier takes to crossdsI =

nMOS Linear I-V

• Now we know– How much charge Qchannel is in the channel– How much time t each carrier takes to cross

channelds

QIt

=

=

nMOS Linear I-V

• Now we know– How much charge Qchannel is in the channel– How much time t each carrier takes to cross

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QIt

W VC V V VL

VV V V

µ

β

=

⎛ ⎞= − −⎜ ⎟⎝ ⎠

⎛ ⎞= − −⎜ ⎟⎝ ⎠

ox = WCL

β µ

nMOS Saturation I-V

• If Vgd < Vt, channel pinches off near drain– When Vds > Vdsat = Vgs – Vt

• Now drain voltage no longer increases current

dsI =

nMOS Saturation I-V

• If Vgd < Vt, channel pinches off near drain– When Vds > Vdsat = Vgs – Vt

• Now drain voltage no longer increases current

2dsat

ds gs t dsatVI V V Vβ ⎛ ⎞= − −⎜ ⎟

⎝ ⎠

nMOS Saturation I-V

• If Vgd < Vt, channel pinches off near drain– When Vds > Vdsat = Vgs – Vt

• Now drain voltage no longer increases current

( )2

2

2

dsatds gs t dsat

gs t

VI V V V

V V

β

β

⎛ ⎞= − −⎜ ⎟⎝ ⎠

= −

nMOS I-V Summary

• Shockley transistor models

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V VVI V V V V V

V V V V

β

β

⎧⎪ <⎪⎪ ⎛ ⎞= − − <⎜ ⎟⎨ ⎝ ⎠⎪⎪

− >⎪⎩

0, ,g insg

C WLWK K CL WL D

µβ ∈ ∈= = =Note the dependencies

on W, L

Activity1) If the width of a transistor increases, the current willincrease decrease not change

2) If the length of a transistor increases, the current willincrease decrease not change

3) If the supply voltage of a chip increases, the maximum transistor current will

increase decrease not change4) If the width of a transistor increases, its gate capacitance

willincrease decrease not change

5) If the length of a transistor increases, its gate capacitance will

increase decrease not change6) If the supply voltage of a chip increases, the gate

capacitance of each transistor willincrease decrease not change

MOS as switch

• MOS can be viewed as switches.• The switches are electrically controlled.

NMOS as a switch• Assume capacitor

(CL) is initially discharged

• Gate=1, Vin=1– CL begins to conduct

and charges toward 1 (Vdd) and stops at (Vdd-Vt)

– Signal is degraded

Gate=Vdd

Vin=VddVout

Ground

Load Capacitor

Vgs

I

Gate=Vdd

Vin=0Vout=Vdd

Ground

Load Capacitor

Vgs

I• Gate=1, Vin=0

– CL begins to discharge toward 0

– Good passer of 0.

CMOS Signal Transfer Property

Open1Closed0PathGate

Gate

Drain

Source

Gate

Source

Drain

Closed1Open0PathGate

pMOS

nMOS

• Transmits 1 well• Transmits 0 poorly

• Transmits 0 well• Transmits 1 poorly

CMOS Transmission Gate

• Transmit signal from INPUT to OUTPUT when Gate is closed

Gate (complementary of Gatecomplementary of Gate)

Source Drain

Gate

INPUT OUTPUTINPUTONON1

ZZOFFOFF0

OUTPUTnMOSpMOSGate

ZZ : High-Impedance State, consider the terminal is “floating”

CMOS Inverter

• Combines the best of both.

Vin

Vcc

nMOS Operation

Vgsn >

Vdsn >

Vgsn >

Vdsn <

Vgsn <SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

nMOS Operation

Vgsn > Vtn

Vdsn > Vgsn – Vtn

Vgsn > Vtn

Vdsn < Vgsn – Vtn

Vgsn < Vtn

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

nMOS Operation

Vgsn > Vtn

Vdsn > Vgsn – Vtn

Vgsn > Vtn

Vdsn < Vgsn – Vtn

Vgsn < Vtn

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

Vgsn = Vin

Vdsn = Vout

nMOS Operation

Vgsn > Vtn

Vin > Vtn

Vdsn > Vgsn – Vtn

Vout > Vin - Vtn

Vgsn > Vtn

Vin > Vtn

Vdsn < Vgsn – Vtn

Vout < Vin - Vtn

Vgsn < Vtn

Vin < Vtn

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

Vgsn = Vin

Vdsn = Vout

pMOS Operation

Vgsp <

Vdsp <

Vgsp <

Vdsp >

Vgsp >SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

pMOS Operation

Vgsp < Vtp

Vdsp < Vgsp – Vtp

Vgsp < Vtp

Vdsp > Vgsp – Vtp

Vgsp > Vtp

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

pMOS Operation

Vgsp < Vtp

Vdsp < Vgsp – Vtp

Vgsp < Vtp

Vdsp > Vgsp – Vtp

Vgsp > Vtp

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

Vgsp = Vin - VDD

Vdsp = Vout - VDD

Vtp < 0

pMOS Operation

Vgsp < Vtp

Vin < VDD + Vtp

Vdsp < Vgsp – Vtp

Vout < Vin - Vtp

Vgsp < Vtp

Vin < VDD + Vtp

Vdsp > Vgsp – Vtp

Vout > Vin - Vtp

Vgsp > Vtp

Vin > VDD + Vtp

SaturatedLinearCutoff

Idsn

Idsp Vout

VDD

Vin

Vgsp = Vin - VDD

Vdsp = Vout - VDD

Vtp < 0

CMOS Inverter Voltage TransferCharacteristic

Vout

Vin1 2 3 4 5

12

34

5

NMOS linPMOS off

NMOS satPMOS sat

NMOS offPMOS lin

NMOS satPMOS lin

NMOS linPMOS sat

3 INPUT CMOS NAND GATE

PULL UPNETWORK

PULL DOWNNETWORK

A

B

C

Y=~ABC

Key Points

• There is always a path from VDD or GND to the output.

• There is no path from the VDD to GND (for our purpose). Thus this gate has a very low power consumption.

• Fully restored logic (why?)

Complex CMOS gates• DesignF=ab+bc+ac

Design the complementary logic…

Exercises

• Design an AND OR Inverter gate:

Tristate Inverter

011

101

Z10

Z00

OutInpEN

What will be the CMOS level circuit for the above?

Tristate Inverter