the physical structure (nmos)users.encs.concordia.ca/~asim/coen 451/lectures/l2.1...concordia vlsi...

25
CONCORDIA VLSI DESIGN LAB 1 The Physical Structure (NMOS) Field Oxide SiO2 Gate oxide Field Oxide n+ n+ Al Al SiO2 SiO2 Polysilicon Gate channel L P Substrate D S L W (D) (S) Metal n+ n+ (G) Poly contact

Upload: others

Post on 19-Feb-2021

1 views

Category:

Documents


0 download

TRANSCRIPT

  • CONCORDIAVLSI DESIGN LAB

    1

    The Physical Structure

    (NMOS)

    Field Oxide

    SiO2

    Gate oxide

    Field Oxiden+n+

    AlAlSiO2SiO2

    Polysilicon Gate

    channel

    L

    P Substrate

    DS

    L

    W

    (D)(S)

    Metal

    n+n+

    (G)

    Poly

    contact

  • CONCORDIAVLSI DESIGN LAB

    2

    3D Perspective

  • CONCORDIAVLSI DESIGN LAB

    3

  • CONCORDIAVLSI DESIGN LAB

    4

    Fabrication Process

    •Crystal Growth

    •Doping / Diffusion

    •Deposition

    •Patterning

    •Lithography

    •Oxidation

    •Ion Implementation

  • CONCORDIAVLSI DESIGN LAB

    5

    Fabrication- CMOS Process

    Starting Material Preparation

    1. Produce Metallurgical Grade Silicon (MGS)SiO2 (sand) + C in Arc FurnaceSi- liquid 98% pure

    2. Produce Electronic Grade Silicon (EGS)HCl + Si (MGS) Successive purification by distillationChemical Vapor Deposition (CVD)

  • CONCORDIAVLSI DESIGN LAB

    6

    Fabrication: Crystal Growth

    Czochralski Method

    Basic idea: dip seed crystal into liquid pool

    Slowly pull out at a rate of 0.5mm/min

    controlled amount of impurities added to melt

    Speed of rotation and pulling rate determine diameter of the ingot

    Ingot- 1to 2 meter longDiameter: 4”, 6”, 8”

  • CONCORDIAVLSI DESIGN LAB

    7

    Fabrication: Wafering

    Finish ingot to precise diameter

    Mill “ flats”

    Cut wafers by diamond saw: Typical

    thickness 0.5mm

    Polish to give optically flat surface

  • CONCORDIAVLSI DESIGN LAB

    8

    Fabrication: Oxidation

    Silicon Dioxide has several uses:- mask against implant or diffusion- device isolation- gate oxide-isolation between -layers

    SiO2 could be thermallygenerated or through CVDOxidation consumes siliconWet or dry oxidation

    Quartz Tube

    Wafers

    Quartz Carrier

    Resistance Heater

    O2 or Water

    VaporPump

  • CONCORDIAVLSI DESIGN LAB

    9

    Fabrication: Diffusion

    Simultaneous creation of p-n junction over the entire surface of wafer

    Doesn’t offer precise control Good for heavy doping, deep junctions Two steps:

    Pre-depositionDopant mixed with inert gas introduced in to a furnace at 1000 oC.Atoms diffuse in a thin layer of Si surfaceDrive-inWafers heated without dopant

    Resistance Heater

    wafers

    Temp: 1000

    Dopant Gas

  • CONCORDIAVLSI DESIGN LAB

    10

    Fabrication: Ion

    Implantation

    Precise control of dopant Good for shallow junctions and threshold adjust Dopant gas ionized and accelerated Ions strike silicon surface at high speed Depth of lodging is determined by accelerating field

  • CONCORDIAVLSI DESIGN LAB

    11

    Fabrication: Deposition

    Reactant

    0.1 -1 Torr

    Loader

    Pump

    Used to form thin film of Polysilicon, Silicon dioxide, Silicon Nitride, Al.

    Applications: Polysilicon, interlayer oxide, LOCOS, metal.

    Common technique: Low Pressure Chemical Vapor Deposition (CVD).

    SiO2 and Polysilicon deposition at 300 to 1000 oC.

    Aluminum deposition at lower temperature- different technique

  • CONCORDIAVLSI DESIGN LAB

    12

    Fabrication: Metallization

    Standard material is Aluminum

    Low contact resistance to p-type and n-type

    When deposited on SiO2, Al2O3 is formed: good adhesive

    All wafer covered with Al

    Deposition techniques:Vacuum EvaporationElectron Beam EvaporationRF Sputtering

    Other materials used in conjunction with or replacement to AlIn today’s technology are cupper and its alloys.

  • CONCORDIAVLSI DESIGN LAB

    13

    Fabrication: Etching

    Wet Etching Etchants: hydrofluoric acid (HF), mixture of nitric acid and HF Good selectivity Problem:

    - under cut- acid waste disposal

    Dry Etching Physical bombardment with atoms or ions good for small geometries. Various types exists such as:

    Planar Plasma Etching Reactive Ion Etching

    Plasma Reactive species

    RF

  • CONCORDIAVLSI DESIGN LAB

    14

    Fabrication: Lithography

    Mask making

    Most critical part of lithography is conversion from layout to master mask

    Masking plate has opaque geometrical shapes corresponding to the area on the wafer surface where certain photochemical reactions have to be prevented or taken place.

    Masks uses photographic emulsion or hard surface

    Two types: dark field or clear field

    Maskmaking: optical or e-beam

  • CONCORDIAVLSI DESIGN LAB

    15

    Lithography: Mask making

    Optical Mask Technique

    1. Prepare Reticle Use projection like system:

    -Precise movable stage-Aperture of precisely rectangular size and angular orientation-Computer controlled UV light source directed to photographic plate

    After flashing, plate is developed yielding reticle

  • CONCORDIAVLSI DESIGN LAB

    16

    Fabrication: Lithography

    Step & Repeat

    Printing

    Printing

  • CONCORDIAVLSI DESIGN LAB

    17

    Lithography: Mask

    making

    Electron Beam Technique

    Main problem with optical technique: light diffraction

    System resembles a scanning electron microscope + beam blanking and computer controlled deflection

  • CONCORDIAVLSI DESIGN LAB

    18

    Patterning/ Printing

    Process of transferring mask features to surface of the silicon wafer.

    Optical or Electron-beam

    Photo-resist material (negative or positive):synthetic rubber or polymer upon exposure to light becomes insoluble ( negative ) or volatile (positive)

    Developer: typically organic solvant- e.g. Xylen

    A common step in many processes is the creation and selective removal of Silicon Dioxide

  • CONCORDIAVLSI DESIGN LAB

    19

    Patterning: Pwell mask

  • CONCORDIAVLSI DESIGN LAB

    20

    Patterning/ Printing

    substrate

    SiO2

  • CONCORDIAVLSI DESIGN LAB

    21

    Fabrication Steps

    Apply PR

    Pre-bake

    Printer align expose

    mask

    Develop, rinse, dry

    Post bake

    Inspect, measure

    Etch

    Strip resist

    Deposit or grow layer

  • CONCORDIAVLSI DESIGN LAB

    22

    Fabrication Steps

  • CONCORDIAVLSI DESIGN LAB

    23

    3D Perspective

  • CONCORDIAVLSI DESIGN LAB

    24

    The Physical Structure

    (NMOS)

    Field Oxide

    SiO2

    Gate oxide

    Field Oxiden+n+

    AlAlSiO2SiO2

    Polysilicon Gate

    channel

    L

    P Substrate

    DS

    L

    W

    (D)(S)

    Metal

    n+n+

    (G)

    Poly

    contact

  • CONCORDIAVLSI DESIGN LAB

    Videos for Fabrication

    A very clear site showing each fabrication step http://www.virlab.virginia.edu/VL/MOS_kit.htm/state/related

    4 min wafer production https://www.youtube.com/watch?v=AMgQ1-

    HdElM&list=PL8InEUrivGYt2Fze1vXsdkHDPWBP7NTXw&index=

    9 min video showing IC fabrication process

    https://www.youtube.com/watch?v=i8kxymmjdoM

    A 10 minute presentation of Global Foundries IC manufacturing process. https://www.youtube.com/watch?v=qm67wbB5GmI&index=13&list=PL8InEUrivGYt2Fze1vXsdkHDPWBP7N

    TXw

    3 min animation of IC fabrication

    https://www.youtube.com/watch?v=d9SWNLZvA8g

    A 4 min very nice presentation with animation of 3D IC manufacturing https://www.youtube.com/watch?v=YIkMaQJSyP8

    25

    http://www.virlab.virginia.edu/VL/MOS_kit.htm/state/relatedhttps://www.youtube.com/watch?v=qm67wbB5GmI&index=13&list=PL8InEUrivGYt2Fze1vXsdkHDPWBP7NTXwhttps://www.youtube.com/watch?v=d9SWNLZvA8ghttps://www.youtube.com/watch?v=YIkMaQJSyP8