PSEC ASIC series 5-15 GSa/s waveform sampling/digitizing ICs

The PSEC-3 & PSEC-4 ASICs5-15 GSa/s waveform sampling/digitizing ICsEric Oberla20-May-2011LAPPD Electronics + Integration GPC ReviewOutlinePSEC series architecture review

PSEC-3 --- testing results Submitted 11-Aug-2010, 40 parts received 16-Dec-2010

PSEC-4 --- design & specificationsSubmitted 9-May to MOSIS prototyping run

PlansLAPPD Electronics + Integration GPC review5/20/20112

5/20/2011LAPPD Electronics + Integration GPC review3PSEC series architecture Waveform sampling using Switched Capacitor Array (SCA)On-chip digitization up to 12 bitsSerial data readoutRegion of interest readout capability Self-triggering option

Designed to handle fast pulses (MCPs)Sampling rate capability > 10GSa/sAnalog bandwidth > 1 GHz (challenge!)Relatively short buffer sizeMedium event-rate capability (~100 KHz)

IBM 130 nm CMOS process

Primary front-end chip for LAPPD MCPs

5/20/2011LAPPD Electronics + Integration GPC review4PSEC-3

Design targeted to fix issues with PSEC-2Still a prototyping version6 channels (2 test + 4 regular)Test structures on chipTesting underway December, 20104.3mm4.0mm5/20/2011LAPPD Electronics + Integration GPC review5PSEC-3 specifications + resultsSPECIFICATIONACTUALSampling Rate500 MS/s-17GS/s2.5 GSa/s-17GS/s# Channels4 4Sampling Depth256 cells256 CellsSampling Window256*(Sampling Rate)-1 256*(Sampling Rate)-1Input Noise1 mV RMS1-1.5 mV RMSAnalog Bandwidth1.5 GHzAverage 600 MHzADC conversionUp to 12 bit @ 2GHzUp to ~10 bit @ 2GHzLatency2 s (min) 16 s (max)3 s (min) 30 s (max)Internal Triggeryesyes5/20/2011LAPPD Electronics + Integration GPC review6PSEC-3 die photo

Open-cavity ceramic package

PSEC-3 Evaluation Card (revA & B)

5/20/20117LAPPD Electronics + Integration GPC review

PSEC-3 Evaluation Card (revA & B)

PSEC-3USB 2.0 FPGA: Altera Cyclone III Firmware developed at UCUSB readout software joint UH/UC effort5/20/20118LAPPD Electronics + Integration GPC review5/20/2011LAPPD Electronics + Integration GPC review9PSEC-3 Sampling Rate

Sampling rates adjustable 2.5 17 GSa/sCurrently running at 10 GS/s, sampling lock with on-chip Delay-Locked Loop (DLL) Good agreement with data + post-layout simulation Custom delay locked loop (DLL) design Works great, except for some issues of de-locking when ADC is runningAttributed to drop in rail voltage/digital noise ---> issues addressed in PSEC-4Video:5/20/2011LAPPD Electronics + Integration GPC review10PSEC-3 Sample Lock

5/20/2011LAPPD Electronics + Integration GPC review11PSEC-3 ADC performance

Wilkinson ADC runs successfully to 2GHz (registers can be clocked to 3GHz) Firmware has ADC running in ~10 bit mode: 700 ns conversion (ramp ->0-1V) @ 1.6 GHzTest structure (counter + ring oscillator)Channel clock fan-outA/D conversion main power consumer in PSEC-3 ~15 mW per channel

(only ON during 700 ns ADC period)PSEC-3 Linearity & Dynamic Range

Channel 3 Channel 4Fine DC scan + fit in linear region to get voltage/count conversionBlue data points are raw data, without correction Very linear in 450-900 mV rangeDeviation < 400mV not fully understood (possibly due to comparator/buffer response or transistor Vthresh)5/20/201112LAPPD Electronics + Integration GPC review

Channel 3 Channel 4Plot of fit residuals + cubic spline interpolationCreate look up table (LUT) to correct for ADC differential non-linearityCurrently, a software correction work with Andrew Wong (UHawaii)In linear region, V < 1 LSB no (very few) missing codesPSEC-3 Linearity & Dynamic Range5/20/201113LAPPD Electronics + Integration GPC review135/20/2011LAPPD Electronics + Integration GPC review14PSEC-3 NoiseInput noise ranges ~1-1.5 mV RMS

Dominant source of on-chip noise comes from analog buffers Issue addressed in PSEC-4 design

NOISE CHANNELS 1-4

5/20/2011LAPPD Electronics + Integration GPC review15PSEC-3 Noise

5/20/2011LAPPD Electronics + Integration GPC review16PSEC-3 AC performance

80 MHz sine wave @ 10GSa/s(time-base not calibrated)

Analog BandwidthTiming Calibrations save for Kurtis talk

5/20/2011LAPPD Electronics + Integration GPC review17PSEC-3 Analog Bandwidth Quantify observation of attenuation along chip input line-High series R of line (~160ohm) --- bad! Histogram random phase sine waves get amplitude along line Example (400MHz):

Overlay sine data on 256 cells ------------>

From histograms, amplitudes comparedfor 3 groups of cells: 1-5 61-65 141-145

More examples: (CW from top left 100MHz, 400 MHz, 1.2 GHz, 700MHz)

5/20/201118LAPPD Electronics + Integration GPC review185/20/2011LAPPD Electronics + Integration GPC review19

PSEC-3 Analog BandwidthTime-domain reflectrometery (TDR) of PSEC-3 input -> input line is much too capacitive ~11pF! (>> 2pF expected from post-layout extraction) - suspected culprits: coupling to subtrate/top layer fill metal

Herve Grabas

5/20/2011LAPPD Electronics + Integration GPC review20PSEC-3 Analog BandwidthBandwidth highly dependent on location along input line:First 5 cells have -3dB ~1.3 GHz (excluding 800MHz region)Need to take more data to confirm trend 600-900 MHzReducing input line resistance should extend 1.3 GHz BW to later cells > PSEC-4--Careful layout to reduce input capacitance > PSEC-4

5/20/2011LAPPD Electronics + Integration GPC review21PSEC-3 summaryPSEC-3 = working waveform sampling ASICRoom for improvement:ABWDynamic flip-flops proven difficult in ADC designOverall readout speedFixes covered in careful redesign -> PSEC-4

Still to characterize:Timing calibrations -> timing measurements (resolution, jitter, etc.)Temperature dependence

Up next:Readout a detector!

5/20/2011LAPPD Electronics + Integration GPC review22PSEC-4

Design targeted to fix issues with PSEC-36 identical channelseach 256 samples deepSubmitted to MOSIS 9-May 201140 partsMay get a larger run via CERN MPW if necessary5/20/2011LAPPD Electronics + Integration GPC review23PSEC-4 specificationsSampling Rate2.5 GSa/s-17GS/s# Channels6 (or 2)Sampling Depth256 (or 768) pointsSampling WindowDepth*(Sampling Rate)-1Input Noise less sensitive to distortion + easier to control impedance + less coupling to substrate! (=less parasitic capacitance)ABW ~1.5 GHz seen by first cells in PSEC-3 should extend to all cells in PSEC-4

IBM 130nm 8RF-DM layer resistivity ----->Herve Grabas

5/20/2011LAPPD Electronics + Integration GPC review26PSEC-4 ADC improvementChange fast, dynamic flip flop + latch configuration in ADC counter with storage d-flip flopLose encoding capability > 2 GHz, but OKOverall architecture unchanged12 bit +1 bit overcount with cell-addressed tri-state drivers on each for readout.

Simulation:

TransferEncoding @ 2 GHzStoring digital values(~10 us)Readout5/20/2011LAPPD Electronics + Integration GPC review27PSEC-3 & PSEC-4 plansParallel work on both chips PSEC-3:Continue characterizing PSEC-3 work with Kurtis on time calibrationsTiming measurements!Detector readout (later talk for details/opportunities)

PSEC-4:Design of evaluation board (possibly using existing revA digital card)Much of PSEC-3 firmware will transferCharacterization (expect chip ~August)

PSEC-4 is baseline ASIC for LAPPD readout. PSEC-3 is working 4-channel prototype and will be used extensively in meantime

BACKUP5/20/2011LAPPD Electronics + Integration GPC review28

Charge pumpPhase Compa-rator

5/20/2011LAPPD Electronics + Integration GPC review29PSEC architecture timing generation

256 Delay units starved current inverter chain -----------> Sampling window strobe (8x delay) sent to each channels SCAOn chip phase comparator + charge pump for sample lock5/20/2011LAPPD Electronics + Integration GPC review30PSEC architecture -- sampling

5/20/2011LAPPD Electronics + Integration GPC review31PSEC architecture ADC + readoutRamping circuitClk enable2-2.5 GHz Ring OscillatorComp.fast 12 bit register12 bit data busRead enableReadout shift register/one-shot:Token256xLevel from sampling cellBandwidth with gain=2 amplifier

Comments: On-board amplifier (channel 4) unstable with unity gain works with gain=2 -3dB BW ~700 MHz for first cells Amplifier = THS4304

5/20/201132LAPPD Electronics + Integration GPC review32