the road ahead for sic beyond 2020 - ohio state university€¦ · commercial sic mosfets are...

The Ohio State UniversityDepartment of Electrical and Computer Engineering

Center for High Performance Power Electronics

The Road Ahead for SiC Beyond 2020

2021 OSU MATERIALS WEEK

Prof. Anant Agarwal and Ms. Susanna Yu (OSU)Prof. Swaroop Ganguly and Mr. Suvendu Nayak (IIT Bombay)

Video Course on WBG Devices:https://cusp.umn.edu/power-electronics/wide-band-gap-wbg-devices

https://cusp.umn.edu/power-electronics/wide-band-gap-wbg-devices

PEOPLEThe SiC Reliability Group, OSU

Anant Agarwal, [email protected] #2

• PartnersIndustry: FORD Motor Co., GeneSiC Semiconductor, SemiQ Power Semiconductors, Alpha-Omega, II-VI Foundation, Sicamore Semi

National Labs: Sandia National Laboratories (SNL), National Renewable Energy Laboratory (NREL)

PARTNERS

Government: Advanced Research Projects Agency-Energy (ARPA-E), Office of Naval Research (ONR), Department of Energy (DoE), Army Research Laboratory (ARL), Air Force Research Laboratory (AFRL), PowerAmerica

University: State University of New York Polytechnic Institute, Georgia Institute of Technology, IIT Bombay


Worldwide Suppliers of SiC

#4

SiC Foundry Business Emerges

#5

Many users can use the same process, simple coordination

Several SiC foundry vendors are entering or expanding

Applications


WBG Applications

#7

GaN SiC

PFC / Power Supply

Home Appliance

UPS

Motor Control

EV / HEV

PV Inverter

Wind Energy

Ships

SiC / GaN Competition

Railway

Power Grid

Developing SiC MOSFETs Large Voltage & Current

Voltage Ratings (V)

Round trip efficiency advantage of 6-8% with SiC

Where is Silicon Carbide Being Usedin Electric Vehicles?

#8

Source from ST Micro Electronics

• Dream

Microgrid

Main Grid

1MW 13.8kV

Asynchronous Converter

DREAM - More than 50% Renewables in the grid enabled by 10 kV SiC MOSFETs.

Microgrid Renewables

+Co-generation

+Storage

13.8kV

1MW

1MW

3ɸ AC/AC

13.8kV

OSU, FSU, NRELNCSTATEUT-KnoxvileDr. Al Hefner (DOE)


Each GridLink eHouse can be customized for a particular load. The standard 6 MVA e-Houses use a redundant series of 2MVA blocks for converting the power from AC to DC and back to AC. Each package is the size of a shipping container, including two transformers. They are prepackaged and burned in at the factory

for easy installation on-site.

Microgrids for D

ata Centers

Page 18

of 20

Pareto Energy’s Grid Link System

http://www.paretoenergy.com/whitepaperfiles/PresentationParetoEnergyMicrogridsForDataCentersWebPageVersion.pdf

SiC 10-20 kV devices can reduce the system size by at least 5x


http://www.paretoenergy.com/whitepaperfiles/PresentationParetoEnergyMicrogridsForDataCentersWebPageVersion.pdf

SiC SMART Power IC Technology

Anant Agarwal, [email protected] #11Prof. Ayman Fayed

Prof. Woongje Sung at SUNY POLY

25 V25 V400-800 V

Development in the right sequence saves time and money

Every technology takes a minimum of 25 years

1. Performance2. Reliability3. Cost


Performance


The Big PictureSi PiN Diodes and IGBTs (600 V to 6.5 kV)

To be Replaced bySiC Schottky Diodes and DMOSFETs (600 V to 12 kV)

Reduced Switching Losses at the same switching frequencyË

3% higher efficiency per power conversion (1200 V)

#14Anant Agarwal, [email protected] #14

Performance

• The total efficiency of the converter increases by ~ 3% at 1200 V and the advantage grows with higher voltage.

• Low switching losses allow high switching frequencies and reduce size of the converter as a trade-off with efficiency gain.

• High temperature (TJ of 200°C - limited by packaging) èeffective cooling and high power density at the cost of higher conduction losses and efficiency.


Reliability


ReliabilityGood NewsCommercial SiC chips (600 – 1.7 kV) pass JDEC and automotive reliability test over 1000 hrsIs that Enough?

High Density of Interface traps ⇒ Low inversion layer mobility

Si: 𝜇n ~ 400 cm2/V·sSiC: 𝜇n ~ 20 cm2/V·s


Reliability

𝑅!" =𝐿𝑐ℎ𝑊

𝑑#$𝜇%𝜖#$(𝑉& − 𝑉')

Low


n+ n+Lch

Rch

Wdox

Si IGBT ~1000 Å of dox →

SiC ~ 400 Å of dox →

VG = 20 V LCH = 1-2 μmVT = 5 V

VG = 20 V LCH = 0.4 μmVT = 2 V

2.5x high electric fieldIn gate oxide Short Circuit time is reduced

Modeling


Mobility model optimization

#20

For the simulation of 4H-SiC MOSFETs, ALTCVT model combines four mobility components

[Mobility components]§ BO (Bulk only)§ BCS (Bulk & Coulomb Scattering)§ BSR (Bulk & Surface Roughness)§ BSP (Bulk & Surface Phonon)§ T (Total)

Dashed line : Default Solid line : Parameter fitting

§ Field effect mobility fitting § Temperature-dependent field effect mobility using optimized parameters

Journal of ELECTRONIC MATERIALS, Vol. 41, No. 5, 2012

VD=0.1 V VD=0.1 V

#21

Transfer and Output characteristics simulation

Dashed: Exp.Solid: Simul.

VD=0.1 V

VG

Short Lch results in lower Rch but reduces short-circuit time (tsc)

Dra

in c

urre

ntLong Channel

Short Channel

Drain voltage

Source MetalInter Layer Dielectric

N drift layer for 1.2 kV device: 10 µm, 1E16 /cm3

Gate Ox, 400Å

N+ Poly Si

Ni Ohmic

Drain

Substrate

Retrograde P-well

N+ SourceP+JFET

3E16/cm3

Vgs = 20V

Lch

#22

#23

1. REF1.5 2. REF1.5 + P+ shield 3. REF1.0 (7E17) + P+ shield 4. REF1.0 (7E17) + P+ shield + Tox 300Å

Designs for longer SC time

5. N Source resistance

1

Drain voltage (V)

Dra

in c

urre

nt (A

)

1

23

4

Design


Low Cgd Design Layouts

Cell pitchP+

JFET

Octagonal cell

Cell pitch

P+ JFET

Graphene cell

N+ poly SiInter Layer Dielectric

Source Metal

Source

P+P+N+ Source N+ Source

N Drift Layer

N+ SubstrateDrain

P Well

SiO2 Source

JFET

𝐶𝑒𝑙𝑙 𝑝𝑖𝑡𝑐ℎ

Cgd

Cell pitch

P+

Stripe cell

JFET

JFET density reduced by 76%

JFET density reduced by 62%


Dielectric Isolation, Polymide, 7 µm

Top Metal (Current Spreading), Al, 4 µm

Si3 N4, 200 nm Si3 N4, 200 nm

SiO2, 1 µm SiO2, 1 µm

n--Drift, 16µm, ND=5.2E15 cm-3

n+-substrate, 350µm, ND=2E18 cm-3

P-Well, 1E18 cm-3

N+ Source 1E19 cm-3

N+ Source 1E19 cm-3

P, 2E17 cm-3

P, 2E17 cm-3

P-Well, 1E18 cm-3

N+ Source 1E19 cm-3

P, 2E17 cm-3

N+1E19 cm-3

N+ Poly Si, 500 nmN+ Poly Si, 500 nm

Gate Ox, 50 nm

P+, 1E19cm-3

P+, 1E19cm-3

P+, 1E19cm-3

P+, 1E19cm-3

SiO2, 1 µm

Si3 N4, 200 nm

Ni, 100 nm Ni, 100 nm

Ni, 140 nm

Ti/Ni/Ag, 50/300/100 nm

0.8µm 50 µm2µm0.5 µm 5 µm2 µm0.3 µm2 µm0.5 µm1 µm 2 µm2 µm0.5 µm 55 µm

Guard rings “46”Total length = 128.8 µmΣGR Spacing = 36.8 µm

JFET 3E16 cm-3

JFET 3E16 cm-3

P-Well, 1E18 cm-3

Gate Ox, 50 nm Gate Ox, 50 nm

2.3 µm0.5 µm

0.5 µm

1 µm


SiC Power MOSFET Cell

Students learn about the Layouts of SiC MOSFET and Diode Chips


Summary

#28

ICommercial SiC MOSFETs are sufficiently Robust and Reliable in all respects but reliability can be further improved by design and process.

IIIIT Bombay and OSU team is attempting to make the design more robust through modeling and experimentation.

IIIThe collaboration brings synergy in both the groups and leverages our respective strengths.

IVOne key problem of low inversion layer mobility has been recently solved. Our model will try to alter the designs to take advantage of high mobility.

Thank You


the road ahead for sic beyond 2020 - ohio state university€¦ · commercial sic mosfets are...

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