the university of tokyo - pilab.jp · the university of tokyo pkt_size= 1 5 14b, i million flow...
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FLARE Open Deeply Programmable Network Node Architecture
Contact: NakaoLab@The University of Tokyo [email protected] Acknowledgement : This research is supported by NICT, KDDI
Deep Programmability Enables Tailored Optimization
So#ware Defined Data Plane
Northbound Interface (NBI)
Service Applica>ons
Control PlaAorm
Southbound Interface (SBI)
SDN HW OpenFlow JUNOS OnePK
Service Abstrac>on Layer (SAL)
NFV Control PlaAorm
Orchestrator
Data Plane API
NFV
Hardware So#ware
Commodity Hardware
SDN So#ware Switch
So#ware
Commodity Hardware
Data Plane Elements(DPE)
Assump>on of IP Network
Commodity Hardware (x86, ManyCore NetProc)
Monolithic Orchestrator
Orchestrator
No Assump>on of IP Network
NBI
DPE
Data Plane Processing (SDN Switch + NFV)
Control PlaAorm
SAL
Present Near Future
FLARE Architecture Vision: Software-Defined Data-Plane Enables Fusion of SDN &NFV
x86 Processor Many Core
Processor
Software Defined OFS1.3 on FLARE Performance vs. CPUs
Throughput linearly scales up as the number of CPU cores
FLARE EX (32x10Gbps)
FLARE2 (2x10 + 8x1Gbps)