The value of a FPGA in the digital

back end of a radar system

Denel Overberg Test Range is a versatile missile and aircraft test range specialising in in-

flight systems performance measurements for the local and international aerospace

industries

The following types of tests can be accommodated at Denel Overberg Test Range, either

on systems under development or during operational evaluation and certification:

Air to air tests

Air to surface (land or sea) tests

Surface to surface (land or sea) tests

Surface to air (land or sea) tests

Anti-tank tests, also from helicopter

Assistance with aircraft performance, carriage and release clearance, avionics

evaluation and certification

Denel OTR - Layout

Denel OTR Tracking Radar

High precision coherent tracking radar (TR):

– Ability to track targets in both skin and beacon

– High measurement precision in range, azimuth, elevation and radial velocity

Operational performance data:

– Frequency : 5400 – 5900 MHz

– Peak power : 650 kW

– Range : 180 km (1 m2 RCS)

: 2800 km (beacon)

– Accuracies : 1.5 m Range

: 100 uR Az/El

– Antenna Gain : 43 dB

– Polarization : VP/CLP/CRP

– Antenna Beamwidth : 1°

Radar System

Radar systems process data received from the

transmitted signal. The received signal holds

key information.

Target Identification

Position

Velocity

Course / Trajectory

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Radar System (continued … ) In order to extract these information from the received signal:

Signal Conditioning

Down Conversion of Signal

Acquire Bipolar Signal (I & Q Signal)

Convert Data : A/D [n-dimensional array]

Signal Processing

TRLA

LNABPF

fc = 5.4 – 5.9 GHz

LO-1 LO-2

BPF

I Video

Q Video

COHO

LPF

LPF

30 MHz

90º

FIF2 = 30 MHz

SVCU

Antenna

RF FRONT

ENDRF HEAD

TRANSMITTER

RECEIVER SVCU

Mo

no

pu

lse

Co

mp

arat

or

and

Po

lari

ser

∑

∆AZ

∆EL

Pilot Pilot

∑

∆AZ

∆EL

n

∑V

∑T

∆AZ

∆EL

∑T(I,Q)

∆AZ(I,Q)

∆EL(I,Q)

∑V(1,2)

∑D(I,Q)

MASTER

COMPUTER

CCAPEDESTALPEDESTAL

CONTROL

Demanding Hardware Resources

Analogue to Digital Conversion

[Multi-Chanel, Synchronized]

Computation

[Matrix Manipulation,

Floating Point Arithmetic]

Filter Design

[Correlation, Convolution]

Signal Processing and Analysis

[FFT, IFFT, DFT]

Timing

[Synchronization, Complex

Trigger Waveforms]

Advantage of Using a FPGA based hardware

Multiple process running concurrently in a signal device

DSP, Waveform Generation, PLLs, Computations

Floating point arithmetic and / or signal processing requires multiple or multi core chips

Compromise in hardware needed as resource is being shared between multiple operation

Single FPGA can perform all these task in a single form factor. Improves performance and reduces size

Speed: All Function Implemented on Hardware

Energy Efficient - Consumes far less Power

TEST MUXVIDEO

REC

TEST GENERATOR

EVENT CONTROLLER

DETECTION A/D SUBSYSTEM

MEASUREMENT A/D SUBSYSTEM 1

DISPLAY UNIT

A/D CONTROLLER

ARITHMETIC CALIBRATION UNITFORMAT TRANSLATOR AND

OUTPUT MUX

TIME UNIT CONTROL PANEL

MICROCOMPUTER (SBC86) REMOTE TERMINAL UNIT

HSDI

AUXILIARY TIME UNIT (STCG)

DUAL PORT MEMORY

∑T(1,Q)

∆AZ(I,Q)

∆EL(I,Q)

∑DI

∑DQ

∑TI

∑TQ

SV1

SV2

∆AZI

∆AZQ

∆ELI

∆ELQ

SV1,2

∑D(I,Q)

DET CONTROLS

IT QT

MB

MB

MB MB

MB

MB

MB

DI

DQ

M1

P1

M1-CONTROLS

A/DSTART

EOC

TRACK MARKAFC GATE

ABSOLUTE TIME WORD

SVCU SUB-SYTEM BUS: SB86 MULTIBUS

A/DSTART EOC

RADAR SYNCHSTX, PTX, ETXIPILOT

10MHz

COMPOSITE VIDEO (CV1, CV2)TO A-SCOPES

(CCA)

SV1,2

1553BRADAR SYSTEM BUS

TEST SYNCH

FIFO BUS

TEST CONTROLS

T0 TIME SYNCH

12 16 32

MULTIBUS

MUXCONTROL FIFO BUS

TEST MUXVIDEO

REC

TEST GENERATOR

EVENT CONTROLLER

DETECTION A/D SUBSYSTEM

MEASUREMENT A/D SUBSYSTEM 1

DISPLAY UNIT

A/D CONTROLLER

ARITHMETIC CALIBRATION UNITFORMAT TRANSLATOR AND

OUTPUT MUX

TIME UNIT CONTROL PANEL

MICROCOMPUTER (SBC86) REMOTE TERMINAL UNIT

HSDI

AUXILIARY TIME UNIT (STCG)

DUAL PORT MEMORY

∑T(1,Q)

∆AZ(I,Q)

∆EL(I,Q)

∑DI

∑DQ

∑TI

∑TQ

SV1

SV2

∆AZI

∆AZQ

∆ELI

∆ELQ

SV1,2

∑D(I,Q)

DET CONTROLS

IT QT

MB

MB

MB MB

MB

MB

MB

DI

DQ

M1

P1

M1-CONTROLS

A/DSTART

EOC

TRACK MARKAFC GATE

ABSOLUTE TIME WORD

SVCU SUB-SYTEM BUS: SB86 MULTIBUS

A/DSTART EOC

RADAR SYNCHSTX, PTX, ETXIPILOT

10MHz

COMPOSITE VIDEO (CV1, CV2)TO A-SCOPES

(CCA)

SV1,2

1553BRADAR SYSTEM BUS

TEST SYNCH

FIFO BUS

TEST CONTROLS

T0 TIME SYNCH

12 16 32

MULTIBUS

MUXCONTROL FIFO BUSAntenna

RF FRONT

ENDRF HEAD

TRANSMITTER

RECEIVER SVCU

Mo

no

pu

lse

Co

mp

arat

or

and

Po

lari

ser

∑

∆AZ

∆EL

Pilot Pilot

∑

∆AZ

∆EL

n

∑V

∑T

∆AZ

∆EL

∑T(I,Q)

∆AZ(I,Q)

∆EL(I,Q)

∑V(1,2)

∑D(I,Q)

MASTER

COMPUTER

CCAPEDESTALPEDESTAL

CONTROL

Antenna

RF FRONT

ENDRF HEAD

TRANSMITTER

PXIe – FPGA BASED HARDWARE

Mo

no

pu

lse

Co

mp

arat

or

and

Po

lari

ser

∑

∆AZ

∆EL

Pilot Pilot

∑

∆AZ

∆EL

n

∑V

∑T

∆AZ

∆ELMASTER

COMPUTER

CCAPEDESTALPEDESTAL

CONTROL

RECEIVER SVCU

∑T(I,Q)

∆AZ(I,Q)

∆EL(I,Q)

∑V(1,2)

∑D(I,Q)

1 2 3 4 5 6

1 250 MS/s, 14-Bit, FPGA Based Digitizer

A/D conversion at Intermediate Frequency (IF) rather than at baseband Level

The signal can then be Digitally Down Converted (DDC)

Digital filter design

2 3 Virtex-5 SX50T based FPGA Module + High Speed Digital I/O Adapter Module

Direct Access to FPGA I/O Pins

Very low transition time (Digital Logic) [5ns]

Synchronization and Timing: PLLs, Distribution of CLKs, Triggers, Complex Digital Waveform

4 GPS, IRIG-B, IEEE 1588, or PPS Timing and Synchronization

Synchronize the PXI System with Test Range Time (STGC)

5 6 Intel Core i5-4400E processor + Express Chassis

High-Speed Peer to Peer Communication

Ethernet Communication with Radar Central Computer and Sub-Systems

Programming of the FPGA module

Digital Down Conversion

Digital stability

It is not affected by temperature or manufacturing processes.

With a DDC, the system works indefinitely – no tuning or component tolerances

Controllability

Most DDCs are controlled using software are stable.

Analog down converters make us of local oscillator which can change frequency swiftly between samples.

These frequency shifting can be significant, due to the settling time of the oscillators.

Size & Power

A single ADC can be used with many DDC.

A single DDC can be implemented in part of an FPGA device.

Multiple Channel

DDC (Continued…) Downside of DDC:

Dynamic Range is of ADC is limited in terms of quantization error.

𝐷𝑦𝑛𝑎𝑚𝑖𝑐 𝑅𝑎𝑛𝑔𝑒 = 20 × 𝑙𝑜𝑔102𝑋

1≈ 6.02 × 𝑋 [𝑑𝐵]

14-bit ADC, gives absolute maximum dynamic range of 84dB. Additional

Automatic Gain Control (AGC) circuit can be used to best utilize this dynamic

range.

DDC in NI FPGA based Hardware

using Xilinx IPs

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Numerically controlled oscillator (NCO),

provided by the XILINX™ CORE

Generator™ DDS Compiler

High-throughput multiply VI

enables the highest possible

clock rates

FIR filter. The XILINX™ CORE

Generator™ FIR Compiler provides

a very efficient FIR filter

implementation

I

Q

Match Filtering Class of Finite Impulse Response (FIR) filters.

It maximizes the signal to noise ratio

Used to detect a template or pulse of known shape of a signal that is buried

in noise.

𝑦[𝑛] =

𝑘=−∞

∞

ℎ 𝑛 − 𝑘 𝑥[𝑘]

Correlating a known signal (template) with a noisy or unknown signal, or

Convolving the unknown signal with a conjugated time reverse version of

template

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3

4

Point by Point

Convolution VIs

Convolution – Multiplication

in the Frequency Domain

Express VI under

Signal Analysis Palette

Convolution Vis under

Advance FIR Design Palette

4FIR Complier IP

Value of using a FPGA based hardware

Deterministic Hardware

All Time Critical and Real-Time Process are all being run on Hardware

Parallel Execution of Processes

Un-Interrupted

Form Factor

Modular Design – Ability to add modules to perform other task of sub-system of Radar

Space Efficient

Project Management

Time Spent on building the prototype is immensely reduced by using LabVIEW

Easy to understand graphical programming (similar to block diagram), visual feedback (graphs, indicator, etc.)

Stability

Low Maintenance

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Thank You