the verification of unicore-ii microprocessor sun hanxin peking university microprocessor r&d...
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![Page 1: The Verification of UniCore-II Microprocessor Sun Hanxin Peking University Microprocessor R&D Center](https://reader035.vdocument.in/reader035/viewer/2022081516/56649eb65503460f94bbf1f6/html5/thumbnails/1.jpg)
The Verification of UniCore-II Microprocessor
Sun HanxinPeking University Microprocessor R&D Center
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Outline
• Introduction to UniCore-II microprocessor
• Simulation-based verification methodology
• Bug driven activity
• Conclusions and future work
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Pkunity-3 Architecture
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ICSoC2005, Aug 05ICSoC2005, Aug 05
UniCore-II Microprocessor
• UniCore Frequency: 600MHz
• 32-bit harvard-architecture RISC CP
U
• UniCore32 instruction set compatible
• Add conditional mov & BLX instructio
ns
• 8-stage instruction pipeline
• Dynamic prediction policy: G-share
• Pipelined I&D Cache
• Two-level TLB
ISS
DEC
IF2
IF1
EXE1
EXE2
MSW
WB
MUL1
MUL2
MADD
MAG
MEM1
MEM2
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Design Verification Problem
• Functional verification is widely recognized as the bottleneck of hardware design cycle:The ever-growing demand
for processor performanceThe dramatically increase
in hardware complexityLow tolerance for bugs on
finished productTime-to-market pressure
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Solution to Verification Problem
• Different Tests, Different Methods:Formal Verification:
• Small block testSimulation:
• Directed test• Constrained-random test
Simulation Acceleration:• Regression test
FPGA Prototyping:• BIOS, Linux kernel, Application test
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Simulation-based Verification
• Simulation metric
• Checking scheme
• Test generation
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Simulation Metric
• Code coverage: line coverage toggle coverage FSM coverage condition coverage
• Functional coverage: pipelined instruction state coverage AHB bus transaction coverage
• Assertion coverage
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Checking Scheme
• Self-check assembly code• OpenVera assertion• Golden reference model comparison
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Checking Scheme
• SystemC in the design flow:Find out problems of docu
mented specificationEvaluate design early in the
design cycleGolden reference model of
RTL design verification
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Test Program Generation
• The key issue of processor verification: Test vector efficiency Verification time Quality of product
• Some examples of processor verification: Intel Pentium-4 verification Alpha21164 verification IBM Genesys, GenesysPro test generator
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Test Program Generation
UniGener: UniCore-II test program generator
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Bug Driven Activity
1031 32 24 18 22 13 5 10 6 10 6 3 2 3 0 01041
7397
115137
150 155 165 171 181 187 190 192 195 195 195
0
50
100
150
200
250
1系列2系列
1系列 10 31 32 24 18 22 13 5 10 6 10 6 3 2 3 0 0
2系列 10 41 73 97 115 137 150 155 165 171 181 187 190 192 195 195 195
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
UniCore-II Bug trends:
Bug driven activity of UniCore-II processor verification:
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Bug Analysis: Example
Bug原因
发现方式
总计占 Bug总量
百分比代码检查
定向测试
定向比对
随机比对
随机断言 FPGA
笔误 1 2 4 2 0 0 9 14.5
对设计规范理解错误 0 1 1 0 0 0 2 3.2
对接口规范理解不一致或不清晰 0 0 0 0 0 0 0 0.00
设计结构错误 0 5 1 2 0 0 8 12.9
对设计内部细节考虑不全面 3 16 7 13 2 1 42 64.5
已有设计发生逻辑错误1 0 0 2 0 0 3 4.8
总计 5 24 13 19 2 1 64 100
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Conclusions
• Different tests, different methods.• Metric-checking-generation triangle• Processor verification needs an efficient test pro
gram generator• UniCore-II test program generator: UniGener• Bug driven activity
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Future Work
• Introduce more useful concept on coverage of processor verification
• Introduce more algorithm to UniGener
We’re glad to discuss with you about UniGener
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ICSoC2005, Aug 05ICSoC2005, Aug 05
Thank you