the wires

EE141© Digital Integrated Circuits2nd Wires1

The WiresThe Wires

Dr. Shiyan HuOffice: EERC 518

Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

EE4271EE4271VLSI DesignVLSI Design


Modern InterconnectModern Interconnect

transmitters receivers


Modern Interconnect - IIModern Interconnect - II


0.18

Source: Gordon Moore, Chairman Emeritus, Intel Corp.

0

50

100

150

200

250

300

Technology generation (m)

Del

ay (

pse

c)

Transistor/Gate delay

Interconnect delay

0.8 0.5 0.250.25

0.150.35

Interconnect Delay Dominates Interconnect Delay Dominates


Wire ModelWire Model

EE141© Digital Integrated Circuits2nd Wires

CapacitorCapacitor

A capacitor is a device that can store an electric charge by applying a voltage

The capacitance is measured by the ratio of the charge stored to the applied voltage

Capacitance is measured in Farads


33D Parasitic CapacitanceD Parasitic Capacitance

Given a set of conductors, compute the capacitance between all pairs of conductors.

-

-

--

-

- -+

+

++

+C=Q/V

1V


Simplified ModelSimplified Model

Area capacitance (Parallel plate): area overlap between adjacent layers/substrate

Fringing/coupling capacitance: between side-walls on the

same layer between side-wall and

adjacent layers/substrate

m2m2 m2

m1

m3


The Parallel Plate Model (Area Capacitance)The Parallel Plate Model (Area Capacitance)

Dielectric

Substrate

L

W

H

tdi

Electrical-field lines

Current flow

WLt

cdi

di

Capacitance is proportional to the overlap between the conductors and inversely proportional to their separation


Wire CapacitanceWire Capacitance

More difficult due to multiple layers, different dielectric

m2m2 m2

m1

m3

=3.9

=8.0

=4.0

=4.1

multipledielectric


Simple Estimation Methods - ISimple Estimation Methods - I

C = Ca*(overlap area)

+Cc*(length of parallel run)

+Cf*(perimeter) Coefficients Ca, Cc and Cf are given by

the fab Cadence Dracula Fast but inaccurate


Simple Estimation Methods - IISimple Estimation Methods - II

Consider interaction between layer i and layers i+1, i+2, i–1 and i–2

Cadence Silicon Ensemble Accuracy 50%


Library Based MethodsLibrary Based Methods

Build a library of tens of thousands of patterns and compute capacitance for each pattern

Partition layout into blocks, and match with the library

Accuracy 20%


Accurate Methods In IndustryAccurate Methods In Industry

Finite difference/finite element method Most accurate, slowest Raphael

Boundary element method FastCap, Hicap


Fringing versus Parallel PlateFringing versus Parallel Plate

(from [Bakoglu89])

Coupling capacitance dominates.


Wire ResistanceWire Resistance

Basic formula R=(/h)(l/w)

: resistivity h: thickness, fixed for a given technology and layer

number l: conductor length w: conductor width

hl

w


Sheet ResistanceSheet Resistance

Simply R=(/h)(l/w)=Rs(l/w)

Rs: sheet resistance Ohms/square, where h is the metal thickness for that metal layer. Given a technology, h is fixed at each layer.

l: conductor length w: conductor width

l

w


Typical Rs (Ohm/sq)Typical Rs (Ohm/sq)

Min Typical Max

M1, M2 0.05 0.07 0.1

M3, M4 0.03 0.04 0.05

Poly 15 20 30

Diffusion 10 25 100

N-well 1000 2000 5000


Contact and ViaContact and Via

Contact: link metal with diffusion (active) Link metal with gate poly

Via: Link wire with wire


Interconnect Interconnect DelayDelay


Analysis of Simple RC CircuitAnalysis of Simple RC Circuit

)()()(

)())(()(

)()()(

tvtvdt

tdvRC

dt

tdvC

dt

tCvdti

tvtvtiR

T

T

state variable

Inputwaveform

± v(t)CR

vT(t)

i(t)


Analysis of Simple RC CircuitAnalysis of Simple RC Circuit

Step-input response:

match initial state:

output response for step-input:

v0

v0u(t)

v0(1-e-t/RC)u(t)

)()()(

0 tuvtvdt

tdvRC

)()( 0 tuvKetv RCt

)()1()( 0 tuevtv RCt

0 0)( 0)0( 00 vKtuvKv


0.69RC0.69RC

v(t) = v0(1 - e-t/RC) -- waveform

under step input v0u(t)

v(t)=0.5v0 t = 0.69RC i.e., delay = 0.69RC (50% delay)

v(t)=0.1v0 t = 0.1RC

v(t)=0.9v0 t = 2.3RC i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd)

For simplicity, industry usesTD = RC (= Elmore delay)

We use both RC and 0.69RC in this course. In textbook, it always uses 0.69RC.


Elmore DelayElmore Delay

Delay

1. 50%-50% point delay

2. Delay=RC (Precisely,

0.69RC)


Elmore Delay - IIIElmore Delay - III

What is the delay of a wire?


Elmore Delay – IVElmore Delay – IV

Assume: Wire modeled by N equal-length segments

For large values of N:

Precisely, should be 0.69RC/2


Elmore Delay - VElmore Delay - V

27

n1 n2

C/2 R C/2

n1 n2

R=unit wire resistance*lengthC=unit wire capacitance*length


RC Tree DelayRC Tree Delay

28

2 7

2

2

1 1 3.53.5

Unit wire cap=1, unit wire res=1

4

2

7

4

2*(1+3.5+3.5+2+2)=24 24+7*3.5=48.5

24+4*2=32

RC Tree Delay=max{32,48.5}=48.5 Precisely, 0.69*48.5


More Accurate RLC Delay ModelMore Accurate RLC Delay Model

29

At time t=0, switch is on. This effect is not felt everywhere instantaneously. Rather, the effect is propagated with a speed u. Denote by c0 the speed of light, epsilon the permittivity and mu the permeability of the dielectric of the medium which the wire is in, L and C the unit wire inductance and capacitance, respectively. According to Maxwell’s law,

I=V/R at t=0 is not right since you assume that you can see R with 0 time


RLC Delay - IIRLC Delay - II

30

Voltage and Current at time t1 and t2

R0 is the resistance you can really see at t1. R cannot be seen yet.


RLC Delay - IIIRLC Delay - III What is R0? The front of the voltage travels from 0 to l.

Suppose that the distance it moves is dx, the capacitance to be charged is Cdx. The charge is thus dQ=CdxV.

Current I=dQ/dt=CVdx/dt=CVu

where is called characteristic impedance.


RLC Delay - IVRLC Delay - IV R0 is a function of the medium For Printed Circuit Board (PCB), it is about

50-75 ohm For any x between 0 and l, we always have

Ix=Vx/R0,Il=Vl/R0 when x=l Note that there is a resistor R. We should

have Il=Vl/R

What happens if R!= R0?


RLC Delay - VRLC Delay - V At load, the wave will be reflected back to the source. The amplitude and polarity of this reflected wave are such that the

total voltage, the sum of incident voltage and reflected voltage, satisfies Il=Vl/R

If the incident voltage is V, denote by pV the reflected voltage, where p is called the reflection coefficient.

If incident current is V/R0, then reflected current is –pV/R0

Thus, (V+pV)/(V/R0–pV/R0)=R.

p=(R/R0-1)/(R/R0+1) R=R0, p=0, no reflection

R=infty, p=1, wire is unterminated R=0, p=-1, wire is short-circuited

There can be multiple rounds of reflections.


RLC Delay ExampleRLC Delay Example Consider a wire of length l, R0=100 ohm, R=900 ohm driven by the source

resistance (transistor equivalent resistance) Rs= 14 ohm. Source voltage is 12V as a step input at time t=0. We want to compute the waveform at the end of l.

Reflection coefficient

At t=0, V1=12*R0/(R0+Rs)=10V since it cannot see R yet

At t=td=l/u, wave V1 arrives at the end and is reflected as V2=pRV1=8V. The total voltage at the end is V1+V2 =18V

At time t=2td, wave V2 arrives at the source and reflected as V3=pSV2=-0.75*8=-6V

At time t=3td, wave V3 arrives at the end and is reflected as V4=PRV3=-4.8V, so the total voltage at the end is V1+V2+V3+V4=7.2V

Continues this process. Next total voltage at the end is 13.7V. The total voltage at l will converge to 12*R/(R+Rs)=11.7V

Rs=14


RLC Delay Example - IIRLC Delay Example - II

35

Voltage at the end of l


When To Use RLC ModelWhen To Use RLC Model

The voltages at first few td have large magnitudes and are quite different from RC model. This is because Rs<R0.

When Rs>>R0, V1 is small and is the reflected voltage V2. The total voltage at the end of the wire will gradually

increase to 11.7V, which is the same as predicted by RC model.

Thus, RLC model should only be used when Rs is small (see also Figure 4-21 in the textbook) since RLC model is expensive to compute.

RLC model can be used when the switching is fast enough since signal transition time is proportional to Rs.

v0v0u(t)

v0(1-e-t/RC)u(t)RC Model, V0=12


SummarySummary Wire capacitance

Fringing/coupling capacitance dominates area capacitance

Wire resistance RC Elmore delay model for wire

For single wire, 0.69RC/2 RC tree

RLC model for wire Reflection When to use

the wires

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