the world leader in high-performance signal processing solutions data conversion fundamentals...
TRANSCRIPT
The World Leader in High-Performance Signal Processing Solutions
Data Conversion Fundamentals
Analog-Digital Converters
Online Seminar
Fall 2002
The World Leader in High-Performance Signal Processing SolutionsThe World Leader in High-Performance Signal Processing Solutions
Introduction to A/D Converters
A/D Converter (ADC) Introduction
A/D Fundamentals Sampling Quantization
Factors Affecting A/D Converter Performance Static Performance Dynamic Performance
ADC Architectures SAR ADCs Pipelined ADCs Flash Type ADC Sigma-Delta ADCs
High Speed ADC Application Considerations
The Measurement & Control Loop
MUXANALOGSIGNAL
PROCESSOR
A - DCONVERTER
D - ACONVERTER
ANALOGSIGNAL
PROCESSORMUX
MICROPROCESSOR
ORDSP
PROCESSOR
REFERENCE• Multiplier/Divider• Log Amplifier• rms-dc Converter• F-V/V-F Converter
• Operational Amp• Differential Amp• Instrumentation Amp• Isolation Amp
nbits
nbits
ADC SAMPLED ANDQUANTIZED WAVEFORM
DAC RECONSTRUCTEDWAVEFORM
ADC
DAC
DSP MemoryChannel
Analog Digital
timetime
An
alo
g
Dig
ita
l
Am
pli
tud
e
Valu
e
“REAL WORLD” SAMPLED DATA SYSTEMS CONSIST OF ADCs and DACs
ANALOGINPUT
DIGITALOUTPUT
RESOLUTIONN BITS
REFERENCEINPUT
Analog Input DIGITAL OUTPUT CODE = x (2N - 1) Reference Input
What is an Analog-Digital Converter?
Produces a Digital Output Corresponding to the Value of the Signal Applied to Its Input Relative to a Reference Voltage
Finite Number of Discrete Values : 2N Resulting in Quantization Uncertainty
Changes Continuous Time Signal into Discrete Time Sampled Representation
Sampling and Quantization Impose Fundamental yet Predictable Limitations
Sampling Process
Representing a continuous time domain signal at discrete and uniform time intervals
Determines maximum bandwidth of sampled (ADC) or reconstructed (DAC) signal (Nyquist Criteria)
Frequency Domain- “Aliasing” for an ADC and “Images” for a DAC
DISCRETETIME SAMPLING
AMPLITUDEQUANTIZATION
y(t)
y(n)
y(n+1)
n-1 n n+1 n+3 ts
t
Quantization Process
Quantization Process Representing an analog signal having infinite resolution with a digital
word having finite resolution Determines Maximum Achievable Dynamic Range Results in Quantization Error/Noise
100
11
10
01
00
Dig
ital
Analog0 1/4 1/2 3/4 1 = FS
1LSB
Any Analog Input in this Range Gives the Same
Digital Output Code
DIG
ITA
L O
UT
PU
T
1 LSB
ANALOG INPUT
1/8 2/8 3/8 4/8 5/8 6/8 7/8
001
010
011
100
101
110
111
Conversion Relationshipfor an Ideal A/D Converter
Quantization Noise
001
010
011
100
101
110
111
1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS
NORMALIZED ANALOG INPUT
DIG
ITA
L O
UT
PU
T
quantization noise error
q = 1 LSB
0 volts
+q/2
-q/2
Quantization Noise (con’t)
The RMS value of the quantization noise sawtooth is its peak value, q2, divided by 3, or q12
For Sine Wave Full Scale RMS Value is 2(N-1)/2 For Saw Tooth Quantization Error Signal RMS Value is q /12 Thus S/N is 1.225 x 2N Expressed in dB as 1.76 + 6.02N, where N is the resolution of the
A/D converter
OUTPUT
FSIGNALFS/2 FS
RMS QUANTIZATION NOISE
HARMONICS OF FSIGNAL
(EXAGGERATED FOR CLARITY)
If the quantization noise is uncorrelated with the frequency of the AC input signal, the noise will be spread evenly over the Nyquist bandwidth of Fs/2.
If, however the input signal is locked to a sub-multiple of the sampling frequency, the quantization noise will no longer appear uniform, but as harmonics of the fundamental frequency
Quantization Noise (con’t)
ADC Resolution vs. Quantization Parameters
Resolution, Bits (n)
2n
LSB, mV (2.5V FS)
% Full Scale
ppm Full Scale
dB Full Scale
8 256 9.77 0.391 3906 -48.0
10 1024 2.44 0.098 977 -60.0
12 4096 0.610 0.024 244 -72.0
14 16,384 0.153 0.006 61 -84.0
16 65,536 0.038 0.0015 15 -96.0
18 262,164 0.0095 0.00038 3.8 -108.0
Analog Input Signal Definitions
Unipolar and Bipolar Converter Codes
0 0 0
FS - 1LSB FS - 1LSB FS - 1LSB
ALL"1"s 1 AND ALL "0"S
ALL"1"s
UNIPOLAR OFFSET BINARY 2’s COMPLEMENT
-FS -(FS - 1LSB)
Factors Affecting A/D Converter Performance- Offset And Gain for Unipolar Ranges
ACTUAL
OFFSET
ERROR
WITH GAIN ERROR:OFFSET ERROR = 0
ACTUAL
IDEAL IDEAL
ZERO ERROR
NO GAIN ERROR:ZERO ERROR = OFFSET ERROR
0 0
GAIN
ACTUAL
OFFSETERROR
WITH GAIN ERROR:OFFSET ERROR = 0ZERO ERROR RESULTSFROM GAIN ERROR
ACTUAL
IDEAL IDEAL
ZERO ERROR ZERO ERROR
NO GAIN ERROR:ZERO ERROR = OFFSET ERROR
0 0
Factors Affecting A/D Converter Performance- Offset And Gain for Bipolar Ranges
DC Specifications (Ideal)
Ideal ADC code transitions are exactly 1 LSB apart.
For an N-bit ADC, there are 2N codes. (1 LSB = FS/ 2N )
For this 3-bit ADC, 1 LSB = (1V/23 = 1/8th)
Each “step” is centered on an eighth of full scale
001
111
110
101
100
011
010
000
1/8 7/83/45/81/23/81/40
Analog Input
Dig
ital O
utpu
t 1 LS B
A D C T ransfer Function(Idea l)
DC Specifications (DNL)
Differential Non-Linearity (DNL) is the deviation of an actual code width from the ideal 1 LSB code width
Results in narrow or wider code widths than ideal and can result in missing codes
Results in additive noise/spurs beyond the effects of quantization 001
111
110
101
100
011
010
000
1/8 7/83/45 /81 /23 /81 /40
Analog Input
Dig
ital O
utpu
t
A D C T ransfer Function(D N L E rror)
+1/2 LSB
+1/2 LSB
-1/2 LSB
DC Specifications (DNL)
DNL error is measured in lsbs.
A given ADC will have a typical DNL pattern.
These patterns will also have an element of randomness to them.
DC Specifications (INL)
Integral Non-Linearity (INL) is the deviation of an actual code transition point from its ideal position on a straight line drawn between the end points of the transfer function.
INL is calculated after offset and gain errors are removed
Results in additive harmonics and spurs
001
111
110
101
100
011
010
000
1/8 7/83/45 /81 /23 /81 /40
Analog Input
Dig
ital O
utpu
t
A D C T ransfer Function(IN L E rror)
+1/2 LSB
+1 LSB
+1/2 LSB
DC Specifications (INL)
Some typical INL patterns
Bow indicates 2nd order nonlinearity
“S” indicates 3rd order nonlinearity
QUANTIFYING ADC DYNAMIC (AC) PERFORMANCE
Harmonic Distortion
Worst Harmonic
Total Harmonic Distortion (THD)
Total Harmonic Distortion Plus Noise (THD + N)
Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Analog Bandwidth (Full-Power, Small-Signal)
Spurious Free Dynamic Range (SFDR)
Two-Tone Intermodulation Distortion
Noise Power Ratio (NPR) or Multitone Power Ratio (MPR)
Dynamic Testing of A/D Converters
LOW PHASE
JITTER
SINEWAVE SOURCE
A/D CONVERTER
ON
EVALUATION BOARD
BANDPASS
FILTER
LOW PHASE
JITTER
SAMPLING
CLOCK SOURCE
FFT
ANALYZER
POWER
SUPPLIES
A Fast Fourier Transform (FFT) Analyzer is used to measure dynamic performance
time
amp
litu
de
f1
3f1
2f1
frequency
amp
litu
de
f1 2f1 3f1
...to this
Fast Fourier Transform converts
this…
An M-Point FFT
The Effective Noise Floor of an M-Point FFT Is Less Than The RMS Value
of the Quantization Noise
SNR = 6.02N + 1.76 dB
RMS Quantization Noise Level
FFT Floor = 10 log 10 (M 2)
0 dB
18 dB, M = 128
21 dB, M = 256
24 dB, M = 512
27 dB, M = 1024
30 dB, M = 2048
33 dB, M = 4096
Bin Spacing = F = FS M
Actual FFT Plot for AD7484, 14-Bit SAR ADC Sampling at 3MHz
-140
-120
-100
-80
-60
-40
-20
0
0 200 400 600 800 1000 1200 1400
Frequency (kHz)
dB
fIN = 1.013MHz
SNR = 77.7dBSNR+D = 77.6dBTHD = -95.5dB
2 Signals that are Mixed Together Produce Sum and Difference
Frequency Components
Nyquist Theory Stipulates that the Signal Frequency, FSIGNAL must
be < to ½ FSAMPLING to Prevent a Condition Known As “Aliasing”, in
which the Difference Component Appears Within the Signal
Bandwidth of Interest
Nyquist Bandwidth & Aliasing
The Signal Frequency Is < 1/2 the Sampling Frequency and So the Sum
and Difference Components Fall Outside (Beyond) the Signal Passband
1 MHz 4 MHz
fsampling fsampling + fsignalfsampling - fsignal
signalpassband
3 MHz 5 MHz
fsignal
The Nyquist Bandwidth & Aliasing(FSIGNAL < ½ FSAMPLING)
The Signal Frequency Is > 1/2 (approx 2/3) the Sampling Frequency. An
“Alias” or False Image is Thus Created that Falls Within the Passband of
Interest.
The Nyquist Bandwidth & Aliasing(FSIGNAL > ½ FSAMPLING)
fsampling- fsignal fsignal fsampling fsampling + fsignal
2.5 MHz1.5 MHz1 MHz“Alias”0.5 MHz
SINAD (Signal-to-Noise-and-Distortion Ratio) The ratio of the rms signal amplitude to the
mean value of the root-sum-squares (RSS) of all other spectral components, including harmonics, but excluding dc
ENOB (Effective Number of Bits)
SNR (Signal-to-Noise Ratio, or Signal-to-Noise Ratio Without Harmonics) The ratio of the rms signal amplitude to the
mean value of the root-sum-squares (RSS) of all other spectral components, excluding the first five harmonics and dc
SINAD, ENOB, and SNR
02.6
76.1 dBSINADENOB
ADC LARGE SIGNAL (OR FULL POWER) BANDWIDTH
Full-power bandwidth is defined as the input frequency where the fundamental in an FFT of the output, rolls off to its 3 dB point
ADC’s SHA generally determines the FPBW FPBW often limited by slew rate of the internal circuitry. May not be compatible with the converter’s maximum
operating rate Ideally fFPBW >> fs / 2
Many High Speed Converters have fFPBW < fs / 2
Use as a “prerequisite” specification for comparing ADC’s IF undersampling capabilities. But need to consider distortion as well.
Successive Approximation ADC
“Recursive” One-Bit Sub-Ranging Architecture
ANALOGINPUT
STARTCONVERT
COMPARATOR EOC ORDRDY
SHA +
-
DAC
SAR*
*SUCCESSIVE APPROXIMATION
REGISTER
DIGITALOUTPUT
Successive Approximation ADC
+FS
-FS
A nalogInput
P eriod 1
M S B
B it 4
B it 3
B it 2
P eriod 3P eriod 2P eriod 1P eriod 4P eriod 3P eriod 2
A nalogInput
In terna l s igna ls fo r a 4-b it successive approxim ation A D C
test a t 1
test a t 1
test a t 1
test a t 1
test a t 1
test a t 1
test a t 10
00
0
0
0
0
00
0
0
01
0
1
0
11
1
00
C onversion com ple te (1011),start on next conversion
How a Successive Approximation A/D Converter Works
Rising/Falling Edge of Convert Start Pulse Resets Logic
Falling/Rising Edge Begins Conversion Process
Bit Comparisons Made on Each Clock Edge
Conversion Time Equals Number of Comparisons
(Resolution) Times Clock Period
The Accuracy of Conversion Depends on the DAC Linearity
and Comparator Noise
EXAMPLE : ANALOG INPUT = 6.428V, REFERENCE = 10.000V
MSB5.000V
2SB2.500V
3SB1.250V
LSB0.625V
VIN > 5.000V VIN > 6.875VVIN > 6.250VVIN > 7.500V
YES
1
NO
0
YES
1
NO
0
How Successive Approximation Works
Advantages to SAR A/D converters
•Low Power (12-bit/1.5 MSPS ADC: 1.7 mW)
•Higher resolutions (16-bit/1 MSPS)
•Small Die Area and Low Cost
•No pipeline delay
Tradeoffs to SAR A/D converters
•Lower sampling rates
Typical Applications
•Instrumentation
•Industrial control
•Data acquisition
Successive Approximation ADC
Pipelined Sub-ranging ADC
Conversion divided into discrete stages thus causing pipeline delay1st Stage ADC is 6-bit
FLASH2nd Stage ADC is 7-bit
FlashTotal resolution is 12
bits (one bit used for error correction)
ANALOGINPUT
7
12
SHA1
6-BITADC
7-BITADC
GAIN
6
+
-
ERROR CORRECTION LOGIC
6-BITDAC
SHA2
SHA3
OUTPUT REGISTER
12
BUFFER
REGISTER
6
+FS
-FS
A nalogInput
In terna l s igna ls fo r a p ipe lined A D C
First conversion (101) Zoom in and performsecond conversion (011)
Pipelined Sub-ranging ADC
+FS
-FS
A nalogInput
In terna l s igna ls fo r a p ipe lined A D C
First conversion (101)
Pipelined Sub-ranging ADC
Advantages to Pipelined Sub-ranging A/D converters
•Higher resolutions at high-speeds (14-bits/105 MSPS)
•Digitize wideband inputs
•Tradeoffs to pipelined sub-ranging A/D converters
•Higher power dissipation
•Larger die size
Typical Applications
•Communications
•Medical imaging
•Radar
Flash or Parallel ADC
2N-1 comparators form the digitizer array, where N is the ADC resolution
Analog input is applied to one side of the comparator array, a 1 lsb reference ladder voltage is applied to the other inputs.
The comparator array is clocked simultaneously and decides in parallel.
Output logic converts from thermometer code to binary
ANALOGINPUT
DIGITALOUTPUT
N
R
R
R
R
R
R
0.5R
1.5R+VREF
STROBE
PRIORITYENCODER
ANDLATCH
Flash or Parallel ADC
Advantages to Flash A/D converters
•Fastest conversion times (up to 1 GSPS)
•Low data latency
Tradeoffs to Flash A/D converters
•Higher power consumption
•High capacitive input is difficult to drive
Typical Applications
•Video digitization
•High-speed data acquisition
FIRST-ORDER SIGMA-DELTA ADC
+
_
+VREF
–VREF
DIGITALFILTER
ANDDECIMATOR
+
_
CLOCK
Kfs
VINN-BITS
fs
fs
A
B
1-BIT DATASTREAM1-BIT
DAC
LATCHEDCOMPARATOR(1-BIT ADC)
1-BIT,
Kfs
SIGMA-DELTA MODULATOR
INTEGRATOR
OVERSAMPLING, DIGITAL FILTERING, NOISE SHAPING, AND DECIMATION
fs
2
fs
QUANTIZATIONNOISE = q / 12 q = 1 LSBADC
fs NyquistOperation
A
KfsKfs
2
fs
2
REMOVED NOISE
MODDIGITALFILTER
Kfs
DEC
fs
Oversampling+ Noise Shaping+ Digital Filter+ DecimationC
Kfs
2
Kfsfs
2
DIGITAL FILTER
REMOVED NOISEADCDIGITALFILTER
Kfs
Oversampling+ Digital Filter+ DecimationB
DEC
fs
DEFINITION OF "NOISE-FREE" CODE RESOLUTION
EFFECTIVERESOLUTION
= log2
FULLSCALE RANGERMS NOISE BITS
P-P NOISE = 6.6 × RMS NOISE
NOISE-FREECODE RESOLUTION = log2
FULLSCALE RANGEP-P NOISE BITS
= EFFECTIVE RESOLUTION – 2.72 BITS
NOISE-FREECODE RESOLUTION
= log2FULLSCALE RANGE
6.6 × RMS NOISEBITS
0.4uVrms
20mV
16.5bits
SIGMA-DELTA ADCs
Advantages to Sigma-Delta A/D converters
•High resolutions and accuracy (24-bits)
•Excellent DNL and INL performance
•Noise shaping capability
Tradeoffs in Sigma-Delta A/D converters
•Limited input bandwidth
•Slower sampling rates
Typical Applications
•Precision data acquisition and measurement
•Medical instrumentation
High Speed ADC Time Domain Specifications Considerations
Aperture Jitter and Delay
ADC Pipeline Delay
Duty Cycle Sensitivity
DNL Effects
EFFECTS OF APERTURE AND SAMPLING CLOCK JITTERJitter:
Most systems assume the signal is sampled uniformly Clock noise leads to non-uniform sampling (i.e. jitter)
Jitter leads to SNR degradation for high frequency inputs:
LSBpja VVTf 2
SNR DUE TO APERTURE AND SAMPLING CLOCK JITTER
SNR(dB)
ENOB
FULLSCALE SINEWAVE INPUT FREQUENCY (MHz)
100
80
60
40
20
0
16
14
12
10
8
6
4
1 3 10 30 100
SNR = 20log101
2ftj
SAMPLINGCLOCK
ANALOG INPUTSINEWAVE
ZERO CROSSING
+FS
-FS
0V
+te-te
te
Typically not an issue in frequency domain applications May vary slightly among devices of same product due to
variations in SHA bandwidth and CLK prop. delays
EFFECTIVE APERTURE DELAY TIME
ANALOGINPUT
SAMPLINGCLOCK
OUTPUTDATA
DATA N - 3 DATA N - 2 DATA N - 1 DATA N
N N + 1 N + 2 N + 3
Many High Speed ADC’s, such as subranging types, use pipeline architectures to: Reduce chip size, and power consumption Allows multiple samples to be converted simultaneously in ADC Results in fixed delay between Sampled Input and corresponding
digital output.
ADC LATENCY OR PIPELINE DELAY
ADC DUTY CYCLE SENSITIVITY
High Speed ADCs are often sensitive to duty cycle of the CLK input CLK oscillators are usually
specified as 40/60 or 45/55 Digital Specifications of
datasheet provide a minimum CLK HIGH/LOW period (nsec) to achieve rated performance.
Some datasheets show SNR/THD graphs as a function of duty cycle
Note, ADC also has minimum specified sample rate
Ideal ADC code transitions are exactly 1 LSB apart. DNL is the deviation from this value.
Results in additive noise/spurs beyond the effects of quantization Limits ultimate achievable SNR and low level signal SFDR performance
Predictable for a given device once error transfer function is known. DNL error pattern varies among devices of a given product
Dynamic correction techniques include adding “dither” or element shuffling
DNL ERRORS LIMIT IDEAL NOISE AND SPUR FLOOR PERFORMANCE
Example : AD9433 SFDR
SFDRENABLED
DISABLED
Example : AD9433 SFDR
SFDR
ENABLED
DISABLED
Encode = 105MspsAin = 70MHz, -0.5dBFs
Example of Data Sheet Specifications for AD9430 ADC
Example of Data Sheet Specifications for AD7476 ADC
For complete information
on the World’s most extensive line of
A/D converters visit
WWW.ANALOG.COM