there are three main parts to this process: fetch retrieves the instruction that is required to be...
TRANSCRIPT
Fetch-execute cycle
Fetch-execute cycle
Fetch decode & execute cycleThere are three main parts to this process:
Fetch• Retrieves the instruction that is required to be used
Decode• The instructions is interpreted and broken down into it’s
constituent parts (eg opcode / operand)
Execute• The instruction is performed and carried out.
Fetch-execute cycle
Instructions called into the processor from main memory having been fetched and decoded.
Instruction
Instruction
Data
Data
Instruction
Main memory
Instructions being fetched, decoded and executed.
Processor
Processor
Fetch decode & execute cycle
Fetch cycle
Program Counter PC
Points to the next instruction that needs to be executed. It is incremented by one to point to the next instruction
+1Program Counter
The memory address register (MAR) holds the address of the currently addressed memory location.
Memory Address Register (MAR)
Program Counter PC
+1
Memory Address Register (MAR)
Fetch cycle
The Memory Address Register (MAR) points the next instruction in main memory.
Main Memory
Program Counter PC
+1
Memory Address Register (MAR) Data
Main memory
1
Data2
ADD #63
Data4
Data5
Data6
Address Bus
Fetch cycle
The instruction is located and loaded into the memory data register (MDR) also called the MBR.
Memory Data Register (MDR)
Program Counter PC
+1
Memory Address Register (MAR) Data
Main memory
1
Data2
ADD #63
Data4
Data5
Data6
Address Bus
Data Bus
Memory Data Register (MDR)
Fetch cycle
The instruction resides in the Current Instruction register (CIR). This is the end of the ‘fetch’ part of the cycle.
Current Instruction Register (CIR)
Program Counter PC
+1
Memory Address Register (MAR) Data
Main memory
1
Data2
ADD #63
Data4
Data5
Data6
Address Bus
Data Bus
Current Instruction Register (CIR)
Memory Data Register (MDR)
Fetch cycle
Program Counter PC
+1
Memory Address Register (MAR) Data
Main memory
1
Data2
ADD #63
Data4
Data5
Data6
Address Bus
Data Bus
Current Instruction Register (CIR)
Memory Data Register (MDR)
Decode cycle
Instruction decoder
The instruction in the current instruction register (CIR) is decoded.
Decode
Decodes the instruction
Program Counter PC
+1
Memory Address Register (MAR) Data
Main memory
1
Data2
ADD #63
Data4
Data5
Data6
Address Bus
Data Bus
Current Instruction Register (CIR)
Memory Data Register (MDR)
Decode cycle
Instruction decoder
OperandOp-code
The instruction is separated into the opcode and the operand as part of this process.
Decode
Program Counter PC
+1
Memory Address Register (MAR) Data
Main memory
1
Data2
ADD #63
Data4
Data5
Data6
Address Bus
Data Bus
Current Instruction Register (CIR)
Memory Data Register (MDR)
Execute cycle
Instruction decoder
OperandOp-code
The fetched and decoded instruction is now executed to complete the process.
Execute
ALU AccumulatorFinally executes the instruction