thermal and mechanical stress modelling of smart power switches under active loading ansys
DESCRIPTION
Smart power switches (SPS) for industrial and automotive applications have to withstand substantial power dissipation during operation. They are expected to work even under extreme temperature and electrical stresses, such as transient start up or overload. Several thousands of cyclic loading of electric pulses might cause failure to this SPS device. The reason behind this failure is that the electrical pulses induce thermal stress, which in turn leads to mechanical stress. Due to the multi-material design of SPS, the thermal stress often induces tractions at the material interfaces. These tractions might initiate cracks and delamination, which can lead to a device failure due to loss of electrical contact. If a crack is not nucleated, the device may fail due to overheating. Therefore, thermal and mechanical stress plays a crucial role to determine the device failure and thereby the lifetime modelling of the device. Finite Element simulation is used to analyse heat transfer and mechanical problems in SPS. ANSYS is the FEM simulation tool which is used to perform the electrical, thermal and mechanical simulations. Electro-Thermal simulation is initially carried out in a 3D model of the SPS for various electrical pulses and as a result, the thermal stress in the model is analysed. Thermo-Mechanical chip simulation is performed with the thermal stress as loading conditions and the mechanical stress across the model is analysed. Microscopic stress simulation of the SPS sub- model is performed to analyse the stress in power metal. The electrical, thermal and the mechanical problem are solved using the FEM method in ANSYS.TRANSCRIPT
Thermal and mechanical stress
modelling of smart power
switches under active loading
Bala Karunamurthy, KAI, Villach. ACUM’14. Vienna
Infineon Technologies AG
65 % of reliability issues are due to Thermo-mechanical loads
(M Glavanovics, KAI: ESSDRC 2004)
Stressed and Unstressed DMOS
Thermally induced loads cause failures
Electric pulses generate temperature
Delamination, cracks, voids, excessive plastic deformation, metal crawling etc.
Metal Extrusion & Cracks(T Smorodin, Infineon: ESSDRC 2007)
(W Kanert, Infineon: Journal of Microelectronics Reliability 2012)
Metal Degradation
Si Ingot Slicing Deposition/Etching
Chip Dicing Die Attach Moulding
Chris Welham, Coventor Inc.
Images: APCMag
How can we test a design/product?
Testing Vs Service conditions
Fundamental understanding
A B C D0
500100015002000250030003500400045005000
Design
CTF
A B C D0
500100015002000250030003500400045005000
Design
CTF
-40 to +150 C0 to +80 C
Prof Peter Borgesen
Stress induced voiding (SIV) – process of diffusion and concentration of vacancies to form
voids
Flux, in atoms per unit area per time,
Mobility ; Where,
Driving Force Flux ,
kT
DM
rF H
kT
Q
eDD
0
N
i i
Hii
kT
Q
rVeD
kTAC
J
10 .
FMCAJ
Where does the stress come from?
E1, ν1, α1
E2, ν2, α2
1. INTRINSIC: Film nucleation and coalescence
2. EXTRINSIC: CTE mismatch
E2, ν2, α2
E1, ν1, α1
Heat
Wafer Fabrication
Die Attach
Moulding
Temperature cycling
1 2 3 4 5 6 7 8 9 100
100200300400500600700800900
1000
Process Steps
Tem
pera
ture
(C)
1
2
3
4
Activate and deactivate element
Use ANSYS “Birth & Kill” Feature
The 5 Challenges
1. Structural complexity
2. Material Matrix
3. Multi-scale & Multi-physics
4. Computational Effort
5. Experimental Validation
(B Karunamurthy, KAI: Journal of Microelectronics)
(S Eiser, KAI)
Elastic, Elastic-Plastic, viscoelastic and visco-plastic behaviour
Interface strength
Temperature dependent
Strain-rate dependency
Micro tensile experiments
Nanoindendation
4-point bending
Wafer curvature measurement
Lap shear and HCF/LCF Testing
ANSYS Input: BKIN, MKIN, Chaboche, Anand, Prony series etc. or USER MAT
What we need? Methods used
(V Kosel, KAI: 2011)
(G Kravchenko, 2011)
El.Therm Simulations
1 2 3 4 5 60
50
100
150
200
250
300
350
400
450
Time (s)
Pow
er
σxy σyz σxz
¼ of Chip-package
Die, Die attach &
Lead frame
In-plane (σxy) and out-of-plane (σxz and σyz) on a chip
70 um
Silicon
Mould Compound
Sub Model
Silicon
Silicon
Mould Compound
Lead Frame
Just one surface: Half-a-million elements!
Nested Sub-Modelling
Homogenization Technique
Micro Model
1
2
3
(B Karunamurthy, KAI: Techconnect, Washington 2013)
Stress peak regions correspond to failure sites
Fracture mechanics simulations
Crack and simulated stress state
Experimental validation
Stress Modelling Our ultimate goal?
Acknowledgements:
Funding bodies:(FFG, Project no. 831163) and the Carinthian Economic Promotion Fund (KWF, Contract KWF-15212274134186).
KAI & Infineon Technologies AG.
© CADFEM 2014
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