IEEE ELECTRON DEVICE LETTERS, VOL. 15, NO. 10. OCTOBER 1994 399

Thermally and Electrically Isolated Single Crystal Silicon Structures in CMOS Technology

Richard J. Reay, Student Member, ZEEE, Erno H. Klaassen, Student Member, IEEE, and Gregory T. A. Kovacs, Member, IEEE

Abstract- Thermally and electrically isolated single crystal silicon structures have been fabricated using a post-processing anisotropic tetramethyl ammonium hydroxide (TMAH) electro- chemical etch. The process was carried out on CMOS circuits fabricated by a commercial foundry. Since the etch consists of a single micromachining step performed on packaged and bonded dice, this technique has the potential for cost-effective prototyping and production of integrated sensors and circuits.

Suspended N-Well

Collect

I. INTRODUCTION

UCH recent work has been done to create CMOS M or bipolar compatible thermal transducers using post- processing techniques [ 11-[7]. These devices are either real- ized with suspended oxide membranes [l] or cantilever-style single crystal silicon structures [2]. The thermally isolated A B structures can sense a localized change in temperature, making them useful for applications such as infrared detection, gas flow monitoring and ac power measurement [1]-[5], [SI. While oxide membranes are useful for building thermopiles and polysilicon heating resistors, they do not allow for the formation Of active devices such as diodes or transistors. Silicon cantilevers, while providing diodes for highly sensitive temperature transducers, are connected to the substrate with low thermal resistance single crystal silicon. Moreover, the processes used for the fabrication of these cantilevers are either not CMOS compatible [2] or require backside alignment 151. In either Case PrOteCtiOn of the metaliZatiOn layers is required during the electrochemical etch.

In contrast to previous work, the technique presented here consists of an electrochemical post-processing etch on an

mercial CMOS process. ~ ~ ~ ~ ~ t h ~ l ammonium hydroxide

Of a p-type silicon substrate, leaving n-type wells suspended from oxide beams. circuits in these n-wells thermally and electrically insulated from the substrate. This technique combines the advantages of the oxide membrane and silicon cantilever by providing the high thermal isolation of oxide beams and the excellent sensitivity of silicon diode temperature sensors. ne etchant in this process is also safer,

Oxide ta P+ Aluminum N-Well N+ EI P-Substrate

EI P-Base 61 Emitter

Fig. 1. (a) Schematic view of a CMOS vertical bipolar transistor inside a fully suspended n-well. (b) Schematic cross-section Of the Structure.

manly used for CMOS compatible anisotropic silicon etching. Since no special processing steps, masks or materials are needed, this process has the potential for simple, cost-effective prototyping and production of integrated Sensor systems.

11. DESIGN AND FABRICATION

unprotected, packaged and bonded IC fabricated using a corn- The packaged Parts used in this experiment were fabricated in a 2 pm commercial CMOS process. Regions of bare silicon

cut, via cut, and Pad opening in the layout file 171. TWO different device structures were fabricated. The first is a pair of ratioed vertical bipolar transistors inside an n-well. The second consists of two series connected diodes in two closely spaced n-wells. Fig. 1 gives a schematic view of an n-well containing a sing1e vertical transistor*

Electrical Contacts for biasing the n-wells and P-substrate

(TMAH) is used to selectively etch exposed front-side regions were exposed by superimposing a device active area, 'Ontact

more easily handled, and less corrosive to the aluminum bond pads than ethylene diamine pyrocatechol (EDP), which is corn-

during the etching were made by connecting TeflonTM coated wires to the appropriate package pins* Without using pro- tective material, such as wax or epoxy, the package was then submerged in TMAH. The n-well was biased at 0.8 v above the p-substrate using a laboratory power supply. The potential between the substrate and the etching solution was maintained at -1.6 V [9] with a potentiostat, using a platinum counter

Manuscript received May 12, 1994. Richard Reay and Erno maassen are

The authors are with the Center for Integrated Systems, Department of

IEEE Log Number 9405144.

supported by NSF Graduate Fellowships.

Electrical Engineering, Stanford University, Stanford, CA 94305 USA.

0741-3106/94$04.00 01994 IEEE

IEEE ELECTRON DEVICE LETTERS, VOL. 15, NO. 10, OCTOBER 1994

Fig. 2. Scanning electron micrograph of two npn bipolar transistors inside a thermally isolated n-well, suspended by oxide beams over an etched pi t, formed by a post-processing etch on a standard CMOS process.

electrode and a silverhilver chloride reference electrode. The etchant used was 8 wt. % TMAH doped with 40 g/L of dissolved silicon. The dissolved silicon adjusts the pH of the solution such that it does not etch the exposed aluminum [lo]. The etching solution was kept at 80 OC and covered with a reflux condenser to keep the concentration of the etchant constant. The TMAH did not noticeably attack the exposed passivation layer, bond pads or bond wires during the six hour etch required to undercut the n-well structures.

Scanning electron micrographs of the resultant structures are shown in Fig. 2 and Fig. 3. The suspended n-well is visible underneath the oxide membrane in each of the figures. Note that in the structure of Fig. 3 the n-well was slightly etched at its comers. This was prevented in the device of Fig. 2 by the collector contact, which forms a guard ring. The thin region of p-silicon between the two n-wells in Fig. 3 was not etched away for reasons not yet fully understood. As is typical for TMAH, the (1 11) plane side walls are very smooth, while the (100) plane bottom shows some surface roughness [9].

111. DEVICE CHARACTERISTICS AND DISCUSSION The thermal characteristics of the ratioed bipolar transistor

structure of Fig. 2 were measured in air by using one of the two transistors as a temperature sensor and the other as a heater. To sense the temperature, a constant current of 2 pA

Fig. 3. Scanning electron micrograph of two series-connected pn diodes inside n-wells suspended by oxide beams over an etched pit, formed by a post-processing etch on a standard CMOS process.

was passed through the diode-connected sense transistor and the voltage across it was measured. The thermal resistance of the structure was measured to be 16.7 WmW, which is relatively low due to the short oxide beams used for isolation. This value is close to the simulated value of 15.2 WmW, which was calculated using a simple thermal model. Devices currently being fabricated with longer isolation beams will have a much higher thermal resistance. The sensitivity of the detector with respect to temperature was measured to be 1.98 mVK, giving a total responsivity of 30.4 V/W. The measured thermal time constant was 1.4 ms.

The dc device characteristics of the transistors in the sus- pended n-wells were measured before and after the etch. The characteristics were not noticeably altered by the etching process. Beta for the transistors was nominally 70, which is typical for minimum sized npn transistors in this CMOS process.

The performance of thermally isolated silicon diode sensors should be significantly better than traditional thermopile based structures for several reasons. The voltage output for a given change in temperature is 1980 pV/K for a pn junction sensor compared to 58 pV/K for an aluminudpolysilicon thermo- couple [ 111 and 3 19 p V K for a n-polysilicodp-polysilicon ther mocouple [3 ] . Another advantage is that pn junctions can be stacked in series w ithout the additional interconnects to the substrate that are necessary for the rmocouple based sensors (Fig. 3). These extra interconnects decrease the sensit ivity of thermopile detectors by increasing the thermal conductance

REAY et al.: THERMALLY AND ELECTRICALLY ISOLATED SINGLE CRYSTAL SILICON STRUCTURES IN CMOS TECHNOLOGY 401

to the subs trate. Additionally, the high Seebeck coefficient in polysilicon thermopiles is coupled with a large ohmic resistance, which leads to high Johnson noise. The noise in a pn junction detector is dominated by shot noise, the effect of which on the signal can be more than an order of magnitude lower than the noise in a polysilicon thermopile.

IV. CONCLUSIONS We have presented a new post-processing electrochemical

etching technique for the fabrication of isolated single crystal silicon structures using a commercial CMOS process. These thermally isolated structures can be used as sensitive temper- ature transducers for applications sensing infrared radiation, pressure and gas flow. Another potential application is for low-power, temperature regulated circuits such as a high performance voltage reference [ 121. This etch technique allows for the simple integration of sensitive thermal transducers with readout and processing electronics. Several such systems are currently under development.

REFERENCES

[l] J. Suehle, R. Cavicci, M. Gaitan, and S. Semancik, “Tin oxide gas sensor fabricated using CMOS micro-hotplates and in-situ processing ,” ZEEE Electron Device Lett., vol. 14, no. 3, pp. 118-120, 1993.

[2] Y. Xu, R. Huang, and G. Rigby, “A silicon-diode-based infrared thermal detector array,” Sensors and Actuators A, vol. 37-38, pp. 226-230,1993.

[3] H. Baltes and D. Moser, “CMOS vacuum sensors and other applications of CMOS thermopiles” in Transducers ’93 Dig. Tech. Papers, New York, 1993, pp. 736741.

[4] D. Jaeggi, H. Baltes, and D. Moser, “Thermoelectric AC power sensor by CMOS technology,” IEEE Electron Device Len., vol. 13, no. 7, pp. 366-368, 1992.

[5] A. van Herwaarden, D. van Duyn, B. Oudheusden, and P. Sarro, “Integrated thermopile sensors,” Sensors and Actuators A, vol. 21-23, pp. 621430, 1989.

[6] N. Swart, A. Nathan, M. Shams, and M. Parameswaran, “Numerical optimization of flow-rate microsensors using circuit simulation tools,” in Transducers 91 Dig. Tech. Papers, New York, pp. 26-29, 1991.

[7] M. Parameswaran, H. Baltes, L. Ristic, A. Dhaded, and A. Robinson, “A new approach for the fabrication of micromechanical structures,” Sensors and Actuators, vol. 19, pp. 289-307.

[8] I. Choi and K. Wise, “A silicon-thermopile-based infrared sensing array for use in automated manufacturing,” ZEEE Trans. Electron Devices, vol. 33, no. 1, pp. 72-79, 1986.

[9] 0. Tabata, R. Asahi, H. Funabashi, K. Shimaoka, and S. Sugiyama, “Anisotropic etching of silicon in TMAH solutions,” Sensors and Actuators A, vol. 34, pp. 51-57, 1992.

[lo] U. Schnakenberg, W. Benecke, and P. Lange, “TMAHW etchants for silicon micromaching,” in Transducers ’91 Dig. Tech. Papers, New York, pp. 815-818, 1991.

[ 1 I ] D. Moser, R. Lenggenhager, and H. Baltes, “Silicon gas flow sensors US- ing industrial CMOS and bipolar IC technology,” Sensors and Actuators

[ 121 R. Dobkin, “Monolithic temperature stabilized voltage reference with 0.5 p p d 0 drift,” in ZSSCC Dig, Tech. Papers, pp. 108-109, 1976.

[13] M. Huff, S. Senturia, and R. Howe, “A thermally isolated microstructure suitable for gas sensing applications,” in Tech. Digest IEEE Solid State Sensors Workshop, Hilton Head, S.C., pp. 47-50, June, 1988.

A, vol. 25-27, pp. 577-581, 1991.