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ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED

CHARGE PUMPS WITH HIGH PERFORMANCE

A Thesis

Presented to

The Faculty of Graduate Studies

of

The University of Guelph

by

YOUNIS ALLASASMEH

In partial fulfilment of requirements

for the degree of

Master of Applied Science

Guelph, Ontario, Canada

cYounis Allasasmeh, August, 2011


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ABSTRACT

ANALYSIS, DESIGN, AND IMPLEMENTATION OF INTEGRATED

CHARGE PUMPS WITH HIGH PERFORMANCE

Younis Allasasmeh

University of Guelph, 2011

Advisor:

Professor Stefano Gregori

This thesis presents the design of new integrated charge pumps with high performance. An

analysis method is determined to evaluate the voltage gain, the output resistance and the conversion

efficiency parameters of integrated charge pumps. An optimization method is developed to improve

the performance through capacitor sizing based on area constraints. Several charge pumps structures

are optimized and compared including the losses due to devices parasitics. Results show that the

Dickson charge pump (voltage doubler) is the best structure for integration. Therefore, techniques to

improve performance and conversion efficiency of integrated voltage doubler are proposed. Switch

bootstrapping technique prevents short-circuit losses, improves driving capability, and enhances the

overall efficiency. The application of charge reuse technique reduces the dynamic power losses of

integrated voltage doublers and double charge pumps. A prototype of the integrated voltage dou-

blers was fabricated in a 0.18-m CMOS process with the proposed techniques. Measured results

have been presented, demonstrating the improvements in performance and conversion efficiency,

with a good correlation between measured and predicted results.


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Acknowledgements

I would like to take this opportunity to express my sincere appreciation to my advisor

Dr. Stefano Gregori for his support and encouragement throughout my research. Without

his faith in my abilities and his consistent help, this work would not have been possible. I

would also like to thank Dr. Hussein Abdullah, who never let an opportunity pass without

lending me his sincere feedback, help, and advice.

I deeply appreciate the support from Kapik integration, and I would like to thank Kapik

team for the experience they have brought me throughout my internships. Also, I would

like to thank CMC for providing the semiconductor fabrication service that made the im-

plementation of my design possible.

Thanks to all my friends in the analog Nano-electronics group for their technical help

and feedback in the past three years. I am greatful to my relatives and friends in Jordan,

Morocco, and Guelph. Thanks for the great help and kindness.

Most of all, thanks are owed to my family for their countless care and sacrifice. To my

father, Dr. Abdelaziz Allasasmeh. To my mother, Dr. Wafa Alami. To my sisters, Alia,

Sarah, and Saja. To my love, Sara Altamimi. To them, I owe all. It was their motivation

and unconditional support that guides me throughout this long journey.

i


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Contents

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Charge Pump Analysis 10

2.1 Method of Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Charge Pump Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.1 Ideal Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.2.2 Gain with Parasitic Capacitances . . . . . . . . . . . . . . . . . . . 15

2.3 Charge Pump Output Resistance . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 Analysis of Output Resistance with Parasitic Capacitances . . . . . 16

2.4 Power Losses in Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.1 Load-Dependent Losses . . . . . . . . . . . . . . . . . . . . . . . 17

2.4.2 Load-Independent Losses . . . . . . . . . . . . . . . . . . . . . . 18

2.5 Analysis of Single-Sided Charge Pumps . . . . . . . . . . . . . . . . . . . 19

2.5.1 Optimization of the Output Resistance . . . . . . . . . . . . . . . . 20

2.5.2 Single-Sided Charge Pumps with Parasitic Capacitances . . . . . . 22

2.6 Analysis of Double Charge Pumps . . . . . . . . . . . . . . . . . . . . . . 25

ii


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CONTENTS iii

2.6.1 Double Charge Pumps Performance with Parasitic Capacitances . . 26

2.7 Charge Reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.8 Simulation Results with Charge Reuse . . . . . . . . . . . . . . . . . . . . 30

2.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3 Design 34

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2 Voltage Doubler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3 Losses and Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.3.1 Load-Dependent Power Losses . . . . . . . . . . . . . . . . . . . . 37

3.3.2 Load-Independent Power Losses . . . . . . . . . . . . . . . . . . . 38

3.3.3 Short-Circuit Power Losses . . . . . . . . . . . . . . . . . . . . . 39

3.4 Proposed Switch Bootstrapping Technique . . . . . . . . . . . . . . . . . . 41

3.5 Charge Reuse Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.5.1 Charge Reuse Voltage Doubler Design . . . . . . . . . . . . . . . . 43

3.6 Design Constrains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.6.1 MOS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.6.2 Bootstrapping Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.6.3 Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.7 Technology Constrains . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.7.1 Integrated Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.7.2 Bulk Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.8 Design of CPs Auxiliary Circuits . . . . . . . . . . . . . . . . . . . . . . 51

3.8.1 Clock Generation Circuit . . . . . . . . . . . . . . . . . . . . . . . 51

3.8.2 Inverter Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . 52

3.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53


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CONTENTS iv

4 Results 54

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.2.1 Steady-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.2.2 Transient Analysis Results . . . . . . . . . . . . . . . . . . . . . . 64

4.3 Prototype Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.3.1 Fabrication Technology . . . . . . . . . . . . . . . . . . . . . . . . 67

4.3.2 Tools and Design Flow . . . . . . . . . . . . . . . . . . . . . . . . 68

4.3.3 Test Setup Realization . . . . . . . . . . . . . . . . . . . . . . . . 69

4.3.4 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . 71

4.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.5 Discussion of the Results and Design Considerations . . . . . . . . . . . . 81

5 Conclusion and Future Work 85

5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

A Testing 89

A.1 View of the Full Chip and the Designed Circuits . . . . . . . . . . . . . . . 89

A.2 Circuits and Pads Arrangement for the Design . . . . . . . . . . . . . . . . 92

A.3 Bonding Diagram for the Design . . . . . . . . . . . . . . . . . . . . . . . 93

A.4 Test Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

A.4.1 Package Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

A.4.2 Adding Off-Chip Passive Components . . . . . . . . . . . . . . . . 95

A.4.3 Clamping the Package to the Fixture . . . . . . . . . . . . . . . . . 96

A.5 Schematic View of Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 97

B Published Papers 104

B.1 Refereed Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104


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CONTENTS v

Bibliography 105


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List of Tables

2.1 Heap CP Design Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2 Fibonacci CP Design Parameters. . . . . . . . . . . . . . . . . . . . . . . . 25

2.3 Exponential CP Design Parameters. . . . . . . . . . . . . . . . . . . . . . 28

4.1 Devices available in the fabrication technology. . . . . . . . . . . . . . . . 67

5.1 Modular CP Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

A.1 Signal types and description. . . . . . . . . . . . . . . . . . . . . . . . . . 90

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List of Figures

1.1 Four stage conventional Dickson CP [1]. . . . . . . . . . . . . . . . . . . . 3

1.2 Four stage bootstrapped Dickson CP [2]. . . . . . . . . . . . . . . . . . . . 4

1.3 Simplified schematic of the boosted voltage generator for DRAM word-

line driver [3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 Double charge pump [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.5 One stage voltage doubler CP [5]. . . . . . . . . . . . . . . . . . . . . . . 7

2.1 Block diagram of a generic charge pump. . . . . . . . . . . . . . . . . . . 11

2.2 Generic 2-phase CP building block. . . . . . . . . . . . . . . . . . . . . . 11

2.3 Procedure for evaluating CP gain. . . . . . . . . . . . . . . . . . . . . . . 14

2.4 Integrated capacitor model. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5 Procedure for evaluating CP output resistance. . . . . . . . . . . . . . . . . 16

2.6 Schematic diagrams of conventional charge pumps with parasitic capaci-

tances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.7 Sketch of capacitors with optimal size of Dickson, heap, and Fibonacci CPs

of equal area and gain (i.e. left A= 5, centreA= 8, rightA= 13). . . . . . 22

2.8 Normalized input conductanceg of Dickson, heap, and Fibonacci CPs as a

function ofA, when= 0.1and= 0.05. . . . . . . . . . . . . . . . . . 23

2.9 Normalized output resistancer of Dickson, heap, and Fibonacci CPs as a

function ofA, when= 0.1and= 0.05. . . . . . . . . . . . . . . . . . 24

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LIST OF FIGURES viii

2.10 Schematic diagrams of double charge pumps. . . . . . . . . . . . . . . . . 27

2.11 Sketch of capacitors with optimal size of double Dickson and double expo-

nential CPs of area and gain (i.e. leftA= 4, rightA= 8). . . . . . . . . . . 282.12 Charge reuse configuration of a generic double CP. . . . . . . . . . . . . . 29

2.13 Description of charge reuse concept in double charge pumps. . . . . . . . . 30

2.14 Schematic diagrams of double charge pumps with charge reuse (parasitic

capacitances are omitted for simplicity). . . . . . . . . . . . . . . . . . . . 31

2.15 Normalized input conductanceg versus voltage gain A for the three CP

types in standard configuration and with charge reuse, when = 0.1, and

= 0.05. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.16 Conversion efficiency and output characteristics of the three CP types as a

function of the output current IO, whenn = 4for Dickson and heap CPs

and N= 3for the Fibonacci CP, VDD = 1.8V, CT= 200pF, f= 10MHz,

= 0.1, and= 0.05. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.1 Conventional 2-phases cross-coupled voltage doubler stage. . . . . . . . . . 36

3.2 2-phases cross-coupled voltage doubler stage. . . . . . . . . . . . . . . . . 39

3.3 Proposed bootstrapping technique applied to a voltage doubler stage. . . . . 41

3.4 Bootstrapped voltage doubler stage with charge reuse. . . . . . . . . . . . . 44

3.5 Maximum efficiency versus transistor width for a voltage doubler when

N= 1,VDD = 1.8 V,f= 10 MHz,CT= 250 pF,= 0.015, and= 0.01. . 46

3.6 Bootstrapping capacitor size versus the maximum efficiency. . . . . . . . . 47

3.7 CV curve of nMOS capacitor (Spectre simulation). . . . . . . . . . . . . . 49

3.8 Equivalent series resistance of MOS capacitor. . . . . . . . . . . . . . . . . 49

3.9 2-phases cross-coupled voltage doubler stage with dynamic bulk biasing

for pMOS switches [6]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.10 Nonoverlapping clock generation scheme (detailed schematic is shown in

Appendix A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52


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LIST OF FIGURES ix

3.11 A CMOS inverter driver with tapering factor 4 (detailed schematic is shown

in appendix A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.1 Schematic diagrams of the conventional voltage doublers. . . . . . . . . . . 55

4.2 Schematic diagrams of the proposed voltage doublers. . . . . . . . . . . . . 56

4.3 Charge pump block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.4 Output characteristics, conversion efficiencies, and input power improve-

ment of a one stage latched and bootstrapped voltage doublers as a function

of the output current IO, when N= 1, VDD = 1.8 V, f= 1 MHz, CT= 262.5

pF,= 0.015, and= 0.01(Spectre simulations). . . . . . . . . . . . . . 584.5 Output characteristics and conversion efficiencies of a one stage latched

and bootstrapped voltage doublers, and savings in input power due to switch

bootstrapping as a function of the output current IO when N = 1, VDD =

1.8 V, f = 10 MHz, CT = 262.5 pF, = 0.015, and = 0.01 (Spectre

simulations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.6 Output characteristics and conversion efficiencies of a two stage latched


bootstrapping as a function of the output current IOwhen N= 1, VDD = 1.8

V,f= 1 MHz,CT= 525 pF,= 0.015, and= 0.01(Spectre simulations). 61

4.7 Output characteristics and conversion efficiencies of a two stage latched


bootstrapping as a function of the output current IOwhen N= 1, VDD = 1.8

V, f= 10 MHz, CT= 525 pF,= 0.015, and = 0.01(Spectre simulations). 62

4.8 Output characteristics and conversion efficiencies of a two stage bootstrapped

voltage doubler and bootstrapped voltage doubler with charge reuse as a

function of the output currentIO, whenN = 2,VDD = 1.8 V,CT= 525 pF,

f= 1 MHz, = 0.015, and= 0.01(Spectre simulation). . . . . . . . . . 63


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LIST OF FIGURES x

4.9 Output characteristics and conversion efficiencies of a two bootstrapped

voltage doubler and bootstrapped voltage doubler with charge reuse as a

function of the output currentIO, whenN = 2,VDD = 1.8 V,CT= 525 pF,f= 10 MHz,= 0.015, and= 0.01(Spectre simulation). . . . . . . . . 64

4.10 Start-up transient with 1 nF capacitive load (two-stage charge pump,VDD

= 1.8 V, andf = 10 MHz) (Spectre simulation). . . . . . . . . . . . . . . . 65

4.11 Energy consumption versus output current (IO) of a latched and bootstrapped

voltage doublers with 1nF capacitive load (two-stage charge pump, VDD =

1.8 V,f = 1 MHz) (Spectre simulation). . . . . . . . . . . . . . . . . . . . 65

4.12 Simulated waveforms of the current drawn from the power supply of the

proposed charge reuse bootstrapped charge pump and the bootstrapped

charge pump (two-stage charge pump,VDD = 1.8 V,f= 10 MHz) (Spectre

simulation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.13 Diagram of the analog design flow used in the design (adapted from CMC). 68

4.14 Photograph of the 24-pin CFP package containing the fabricated chip. . . . 69

4.15 Layout of the designed test board. . . . . . . . . . . . . . . . . . . . . . . 70

4.16 Block diagram of the experimental setup. . . . . . . . . . . . . . . . . . . 71

4.17 Chip design layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.18 Microphotograph of the design; the chip size is 1 mm 1.5 mm. . . . . . . 73

4.19 A microphotograph showing circuits designed in a one stage bootstrapped

voltage doubler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.20 Measured and simulated output characteristic and conversion efficiency of

a fully integrated two stage bootstrapped voltage doubler as a function of

the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . . . . . . . 75


a fully integrated two stage bootstrapped voltage doubler with charge reuse

as a function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . 76


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LIST OF FIGURES xi

4.22 Measured and simulated improvement in input power consumption of the

two-stages bootstrapped voltage doubler with charge reuse with respect to

the two-stages bootstrapped voltage doubler as a function of the output

currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . . . . . . . . . . . . 77

4.23 Measured and simulated output characteristics and conversion efficiency

of a fully integrated two stage cross-coupled (latched) voltage doubler as a

function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . 78


a fully integrated one stage bootstrapped voltage doubler as a function of

the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . . . . . . . 79

4.25 Measured and simulated output characteristics and conversion efficiency

of a fully integrated one stage cross-coupled (latched) voltage doubler as a

function of the output currentIO, whenVDD = 1.8 V,f = 1 MHz. . . . . . . 80


one stage bootstrapped voltage doubler with respect to the one stage latched

voltage doubler as a function of the output current IO, whenVDD = 1.8 V,

f = 1 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81


two stages bootstrapped voltage doubler with respect to the two stages

latched voltage doubler as a function of the output currentIO, whenVDD =

1.8 V,f = 1 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.28 Measured load independent power losses versus input supply voltage of

two-stage voltage doublers bootstrapped, latched, and bootstrapped with

charge reuse atf = 1 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.29 Measured maximum efficiencies versus frequency of two stage voltage

doublers latched, bootstrapped, and bootstrapped with charge reuse at a

supply voltageVDD = 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . 83


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LIST OF FIGURES xii

4.30 Measured and calculated [7] output resistance of the two stage bootstrapped

voltage doublers at a supply voltageVDD = 1.8 V with parasitic resistance

of 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.1 Proposed bootstrapping technique in a modular CP stage used to build

generic double CPs (e.g. doubler-based CP, heap CP, Fibonacci CP, and

exponential CP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.2 Proposed bootstrapping technique in a modular CP stage used to build any

two-phase double CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

A.1 Top view of the designed chip schematic. . . . . . . . . . . . . . . . . . . 89

A.2 Block view of the six circuits. . . . . . . . . . . . . . . . . . . . . . . . . 91

A.3 Chip layout and pads arrangement. . . . . . . . . . . . . . . . . . . . . . . 92

A.4 Bonding diagram for the design. . . . . . . . . . . . . . . . . . . . . . . . 93

A.5 Photograph of the fabricated test board. . . . . . . . . . . . . . . . . . . . 94

A.6 Technical drawing of the 24-pin CFP package (Spectrum Semiconductor,

Inc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

A.7 Circuit 1 schematic (2stMVD). . . . . . . . . . . . . . . . . . . . . . . . . 97

A.8 Circuit 2 schematic (1stMVD). . . . . . . . . . . . . . . . . . . . . . . . . 98

A.9 Circuit 3 schematic (2stMVDDBB). . . . . . . . . . . . . . . . . . . . . . 99

A.10 Circuit 4 schematic (2stCSDBB). . . . . . . . . . . . . . . . . . . . . . . . 100

A.11 Circuit 5 schematic (1stCCVD). . . . . . . . . . . . . . . . . . . . . . . . 101

A.12 Circuit 6 schematic (2stCCVD). . . . . . . . . . . . . . . . . . . . . . . . 102

A.13 Clock generation circuit schematic. . . . . . . . . . . . . . . . . . . . . . . 103


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Chapter 1. Introduction

Chapter 1

Introduction

1.1 Motivation

Charge pumps (CPs) are power converters that convert the power supply voltage to higher

or lower constant (DC) voltages. Charge pumps transfer charge packets from the power

supply to the output terminal using only capacitors and switches to generate the required

voltage level, thereby allowing integrated implementations.

In microsystems, charge pumps are usually fully built on-chip, rather than off-chip,

to simplify chip and board design and reduce costs. Integrated implementations of charge

pumps exploit integrated capacitors as storage elements and transistors as transfer switches,

where the drain and source terminals are the two switch terminals, and the gate terminal

is used to control the switch state. Many MOS-based systems such as Flash memories,

DRAMs, OTPs, RS-232 transceivers, and driver circuits require multiple supply voltage

levels for their functional blocks and therefore are equipped with charge pumps. Integrat-

ing the CP and other functional blocks on the same die is critical for footprint and cost

reduction, however, it presents unique design challenges in terms of power efficiency, de-

vice reliability, driving capability, and performance.

The first and most important challenge is power efficiency; charge pumps with low

1


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Chapter 1. Introduction 2

power efficiency limit the benefit of power conversion on chip. It is desirable to increase

charge pumps efficiency not only in battery-powered systems, but also in many applications

with common supply voltages to reduce the integrated circuits packaging cost because of

heat dissipation.

A second challenge involves the driving capability; for some applications, a wide range

of load currents and output voltages are desirable. However, it is of particular impor-

tance that charge pumps are designed to function effectively for certain steady-state oper-

ating points with minimum silicon area. In addition, the down-scaling of oxide thickness

of MOS devices increases the oxide leakage currents and lessens the oxide breakdown

voltage, which in turn limits the maximum voltages that can be safely handled on chip.

The reliability of MOS structures is primarily determined by three threatening mechanisms

namely punchthrough, oxide breakdown, and well-diffusion junction breakdown. In typ-

ical CMOS design, the first two factors happen at lower voltages than the well-substrate

junction breakdown.

The start-up time is an important factor in integrated charge pumps because start-up

time limits the functionality and the performance of other blocks, also a faster start-up time

can reduce the CP energy consumption during transients and improve the overall efficiency.

Finally, the output voltage ripple is a critical design specification; larger output ripple

degrades the performance of some functions. In particular, the ripple at the output of a

charge pump can have a negative impact on sensitive analog circuits such as reference

voltage generators, op-amps, and charge pump control circuitry.

1.2 Literature Review

The first widely used monolithic charge pump is the Dickson charge pump [1]. This circuit,

shown in Fig. 1.1, uses diode connected (N) MOS transistors and a chain of capacitors (C)

driven by two complementary phases1 and 2 to transfer charges from the power supply


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Figure 1.1: Four stage conventional Dickson CP [1].

at a voltageVDD to the load capacitorCL at a higher voltage. The ratio between the output

voltage and the input voltage is the conversion ratio. The main drawback of this config-

uration is the threshold voltage drop associated with the diode connected transistors. At

higher conversion ratios, the performance is even worse because of the increased threshold

voltage due to the body effect. Moreover, conversion ratios decrease at low-supply voltages

since the threshold voltage shift cannot be scaled down.

In the bootstrapped Dickson CP [2], limitations of the switch on resistance, low con-

duction, and voltage drop associated with diode connected transistors are alleviated by

introducing an additional MOS switch Nb and capacitorCb for boosting the gate voltage

of the main switchesNas shown in Fig. 1.2. This implementation needs devices able to

withstand high voltages and the generation of four nonoverlapping clock phases (1, 2, 3,

and4), which also prevent short-circuit currents from nodes at higher voltages to nodes

at lower voltages. However, when the diode connected transistor of the output stage is for-

ward biased, it causes a voltage loss equal to the diode threshold voltage. This reduction is

particularly critical in the presence of low voltage power supplies.

A word-line driver with a boosted voltage generator is employed to improve DRAMs

performance [3]. The boosted voltage generator is conceived with cross-coupled nMOS

transistors driven by the nonoverlapping phases 1 and 2. In this configuration, shown


18/123


Figure 1.2: Four stage bootstrapped Dickson CP [2].

in Fig. 1.3, a controlled serial switchNSis required at the output to obtain a constant DC

output voltage. The output switch is controlled with a feedback technique by utilizing two

additional charge pump circuits, an inverter, and two additional clock phases 3and 4.

To improve the performance of charge pumps, the double charge pump in Fig. 1.4 was

conceived to reduce the output ripple by feeding the load in each half period using the same

total capacitance [4]. The transfer capacitors of the last stage (C = C

) are alternately

charged to the voltage of the previous stage (Vp) and then boosted by the same voltage

level to charge the load at a higher output voltage. The clock signals of1 and 2 are

bootstrapped to the same level asVpto connect the two capacitors in series.

The voltage doubler of Fig. 1.5 usually consists two latched CMOS pairs in each

stage [5]. The complementary voltage swings of the internal nodes are used to control

the switches of opposite branches. This circuit eliminates the voltage drop at the out-

put switches, reduces the output voltage ripple, and uses only two nonoverlapping phases.

Moreover, the voltage across each transistor is never higher than the power supply voltage

VDD. At high output currents, the overdrive voltage decreases causing the output resistance

to rise due to higher switch resistance, thus increasing resistive power losses and reducing

power efficiency and driving capability. Moreover, a short-circuit loss from higher voltage


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Figure 1.3: Simplified schematic of the boosted voltage generator for DRAM word-line

driver [3].

Figure 1.4: Double charge pump [4].


20/123


nodes to lower voltage node exists during transitions. The resulting short-circuit current

reduces the charge pump efficiency and output voltage.

The two series pMOS transistors (P and P

) in Fig. 1.5 act as charge-transfer devices to

provide a constant output voltage at the output. If the well potential is too low, the vertical

parasitic bipolar transistors create a leakage path to the substrate. As an effort to solve this

issue, the pMOS well potential is kept higher than the source and drain terminals by means

of a bulk biasing circuit [6]. The solution involves a switching circuit that connects the

well to the highest potential. Moreover, the pMOS transistors are driven independently by

an additional level shifter to improve their conductivity. However, the implementation is

constrained by an input supply voltage of one third the device voltage rating specified in

the process.

In the conventional voltage doubler [5], the complementary voltage transitions of inter-

nal nodes occur simultaneously during switching. The resulting short-circuit currents can

be reduced by exploiting two parallel stages to generate control signals of the main transfer

switches [8], or by using four nonoverlapping phases and bootstrapping the pMOS switches

[9]. In these implementations, at high output currents, the voltage driving the switches de-

creases, therefore, reducing both the driving capability and the power efficiency.

To overcome the limitation of the charge pump driving capability, an unconventional

boosting technique to control switches is suitable for cascaded voltage doubler operating at

low supply voltages [10]. The auxiliary boosting circuit generates the proper control signals

from the main clock phases. The solution enhances the driving capability and allows the

use of low voltage devices, but does not eleminate short-circuit losses.

The maximum power efficiency is limited by dynamic power losses due to charging

and discharging the parasitic capacitances. Reusing some of the charges that are normally

wasted for charging and discharging parasitic capacitances at each cycle is a promising

approach for reducing power dissipation in charge pumps [11]. This technique improves

the power efficiency and reduces electromagnetic emission of conventional bootstrapped


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C C'

P'

PN

N'V

DD

CL

0

VDD

VDD

Figure 1.5: One stage voltage doubler CP [5].

Dickson charge pumps.

Several charge pump topologies with a voltage gain which increases at a higher rate

than the number of stages have been proposed in the literature. The Fibonacci charge pump

[12] achieves the highest voltage gain for a given number of capacitors [13]. Another CP

structure with a high voltage gain and based on double implementation is the exponential

charge pump [14] and [15], which has a voltage gain that increases exponentially with the

number of stages. However, it should be pointed out that, as a result the high voltage rise

per stage, the output voltage is limited only by the fabrication process and the constraint on

the minimum oxide thickness of integrated devices forces the use of a high-voltage thick

oxide devices.

The heap charge pump represents a different topology that achieves the same ideal

gain as the Dickson charge pump for a given number of stages [16]. In this topology, the

transfer capacitors are alternately connected in parallel to the input supply voltage and then

connected in series to charge the output terminal to a higher voltage level. The maximum

voltage across any of the transfer capacitors is only equal to the input voltage, regardless


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of the number of stages, which allow the structure to use low-voltage capacitors.

1.3 Contributions

The work presented here provides analysis, design, and implementation guidelines to en-

able successful on-chip integration of charge pumps. Six integrated charge pump circuits

were designed and fabricated in a TSMC 0.18-m CMOS process. The aim of this research

is to develop approaches that reduce power losses with less area than existing conventional

CP circuits. Design trade-offs are discussed, including a test chip design and testing.

The main contributions of this thesis are summarized as:

Determination of an analysis method for evaluating integrated charge pumps perfor-

mance and optimizing their design.

Application of the charge reuse concept to effectively reduce the dynamic power

losses of integrated double charge pumps.

Development of a switch bootstrapping technique for double charge pumps. The

technique prevents short-circuit losses, improves driving capability, and enables efficient

operation at low supply voltages.

Implementation of six integrated circuits in a 0.18-m digital process and comparison

of experimental results.

1.4 Thesis Organization

The rest of the thesis is organized as follows: Chapter 2 introduces an analysis method to

evaluate and optimize the performance of integrated single-sided charge pumps and double

charge pumps, and the application of charge reuse in integrated charge pumps. Chapter

3 examines the design limitations of integrated voltage doublers and provides an overview

on the design procedure of proposed integrated voltage doubler in standard CMOS process.

Chapter 4 presents the implementation of the designed circuits and shows simulation and


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Chapter 2. Charge Pump Analysis

Chapter 2

Charge Pump Analysis

2.1 Method of Analysis

In order to design efficient on-chip charge pumps, a careful analysis must be done. The

method described here is based on the pioneering work on switched-capacitor circuit anal-

ysis [17]. The method is suitable for networks containing switches, capacitors, and voltage

sources as illustrated in Fig. 2.1. The circuit is described effectively by means of switching

matrices, a capacitance matrix, and a voltage source matrix. The MOS switches are mod-

elled as ideal switches with zero on resistance, capacitors as linear elements, and voltage

sources as ideal sources. The analysis is done under the following assumptions. First of

all, each switch changes its state (on, off) instantaneously at each switch event tk, where

tk is an instant of time when at least one switch in the circuit changes state. Furthermore,

slow switching conditions are assumed, where the switching period is much longer than

time constants due to capacitances and resistances of integrated components and intercon-

nects. Each switching period consists ofk consecutive non-overlapping fragments known

as phases, which define the state of the switches in every fragment (tk, tk+1) and, hence,

the charge transfer between capacitors. Finally, the circuit is analyzed in steady-state con-

ditions, where the capacitor voltages are periodic steady-state waveforms.

10


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Chapter 2. Charge Pump Analysis 11

Figure 2.1: Block diagram of a generic charge pump.

C

1

21 2

5

2

1

3

4 6

1 2 3 4 5 6

1 2 3 4 5 6

1

2

Figure 2.2: Generic 2-phase CP building block.


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In each phase, the nodes in the CP circuit are grouped into l separate parts, each part is

either a set of nodes connected by closed switches or an isolated node as shown in Fig. 2.2.

Therefore, a k-phase CP with n nodes is described by kswitching matrices Sk, with n rowsandn columns, to record the CP switching activity. By assigning appropriate numbers to

the nodes, the switching matrix elements are defined according to their connection in the

switching phasek as follows:

Sk(i, j) =

1 ifiis the node with the lowest number in a separate part of

the closed switch network, and node j belongs to that separate part

0 otherwise

(2.1)

where 1 i jand 1 j n.

A nncapacitance matrix C describes the CP capacitors in terms of their values, node

connections, and parasitics, and can be expressed as

C(i, j) =

total capacitance connected permanently to node i ifi= j

negative of the total capacitance betweeni andj ifi =j(2.2)

The CP independent voltage source and ground (i.e. grounded switches are connected

to a zero value voltage source) connections are described by an n 2 matrix G, whose

elements are defined as

G(i, h) =

1 if theh-th voltage source is connected to nodei

0 otherwise(2.3)

where 1 i nand 1 h 2.

The capacitance matrix and the voltage sources matrix do not change as the switches

change states. The node voltages are represented by the (n1) vector v(tk), which defines


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the voltage between thei-th node and ground at switch eventtk. The charges delivered by

the independent voltage sources are represented by the (21) vector qI(tk), which denotes

the charge passed through the h-th voltage source from switch event tkto switch event tk+1.In each phase, the closure of the switches imposes a set of(n l+ 2) KVL equations and

l charge conservation equations, from which we find the corresponding nodes voltage at

timetk and charges delivered by the sources during the interval (tk,tk+1). For a complete

solution, conservation equations can be compactly expressed as:

vI(tk)

SkCv(tk1)

=

GT 0

SkC + STk I SkG

v(tk)

qI(tk)

, (2.4)

where vI(tk)is a(2 1)vector which represents the independent voltage sources, and

I is then nidentity matrix. The (n+ 2) (n+ 2) matrix k in (2.4) can be rearranged

to obtain a solution for the nodes voltage v(tk)and the delivered charges qI(tk)as follows:

v(tk) = AkvI(tk) + BkSkCv(tk1) (2.5)

and

qI(tk) = RkvI(tk) + OkSkCv(tk1), (2.6)

where Akand Bkare the upper-left n2submatrix and the upper-right nn submatrix

of1k , respectively. Rkand Okare the lower-left22submatrix and the lower-right2n

submatrix of1k , respectively. In the case of a CP operating with two phases, in steady-

state v(tk1) = v(tk+1)and v(tk) = v(tk+2), therefore the CP voltage nodes and delivered

charges can be calculated.


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Figure 2.3: Procedure for evaluating CP gain.

2.2 Charge Pump Gain

CPs achieve capacitive voltage conversion by means of transfer capacitors and switches

driven by nonoverlapping clock phases. Each transfer capacitor is charged to a certain

voltage level and then it is boosted by another voltage level resulting in a voltage increase

at the output terminal. Since CP circuits do not use inductors, they are well suited for

integrated implementations in planar conventional technologies.

2.2.1 Ideal Gain

The voltage gain A is defined as the ratio between the maximum open-circuit output voltage

VOand the input voltage VDD (assumed constant). Since no current is delivered to the load,

dependencies on the switching frequency and capacitances values are eliminated. When

ideal capacitors are assumed, the gain depends only on the number of capacitors N, the

number of phases, and the topology, which, in turn, determines how the transfer capacitors

are interconnected in each phase. The procedure for evaluating the voltage gain includes

disconnecting any load at the output and finding the output voltage as shown in Fig. 2.3.


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C

Substrate

CC

TopBottom

Figure 2.4: Integrated capacitor model.

2.2.2 Gain with Parasitic Capacitances

A key reason why the gain of a real integrated CP deviates from the ideal is the unavoidable

presence of parasitic capacitances, which share a portion of each charge packet transferred

between transfer capacitors resulting in reduced gain. Parasitic capacitances are expressed

by the technological parameters and, which give the stray parasitic capacitances C

(between bottom plate and substrate) and C(between top plate and substrate) of any

integrated capacitorCas shown in Fig. 2.4. The value of andare determined by the

process and the type of the integrated capacitors used (integrated capacitors are discussed

in detail in Chapter 3). To assess the impact of parasitic capacitances on the voltage gain

A, their values are included in the capacitance matrix C by modelling the total capacitance

connected permanently to a node as (+ 1)C or (+ 1)C [18]. The gain with parasitic

elements is lower than the ideal gain, because a portion of each charge packet transferred

between stages is shared with the parasitic capacitors and wasted.

2.3 Charge Pump Output Resistance

In the case of ideal linear elements, the procedure for evaluating the output resistance in-

volves turning off the input voltage VDD, applying an ideal sourceVX to the output, and

calculating the ratio between the voltage and the average current of the applied source as

shown in Fig. 2.5. In a two-phase CP the output resistance [19] is given by


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Vx

Ix

=qx

fs

VIN= 0

Charge

pump

Figure 2.5: Procedure for evaluating CP output resistance.

RO = r

f CT, (2.7)

wherefis the switching frequency, CTis the value of the total capacitance defined as

the sum of the capacitances of all transfer capacitorsCT =N

i=1 Ci, andr is a constant

that depends on circuit topology which can be expressed as

r=Ni=1

a2ci, (2.8)

where N is the number of capacitors and aci = qi/qXis the charge multiplier factor,

which is the ratio of the chargeqi, transferred by capacitorCi in a period, and the charge

qXdelivered to the load. The charge multiplier factors are calculated by applying charge

conservation to the circuit in phase 1 and 2, and by considering that, in steady-state, each

capacitor receives and delivers the same charge in each of the two phases.

2.3.1 Analysis of Output Resistance with Parasitic Capacitances

To evaluate the effect of parasitic elements on the output resistance, we include Ci and

Ci in the capacitance matrix, turn offVDD, connect a voltage source at the output, apply

the method above one more time, and find the charge qXdelivered by the voltage source

during the switching period, the corresponding current, and thus the output resistance. The

output resistance with parasitic elements is lower than the ideal, because it is inversely


31/123


proportional to the node capacitances that increase with the parasitics.

2.4 Power Losses in Charge Pumps

Charge pumps transfer charge packets from the power supply at a voltage VDD to an out-

put terminal at a higher voltage VO. In this operation, CPs dissipate a portion of the input

power and may reduce the benefit of scaling the supply voltage down. The energy effi-

ciency is defined as the average power delivered to the load divided by the average of input

power. Power losses arise mainly from capacitor charging and discharging losses, resis-

tive conduction losses, and losses due to parasitic capacitances and short-circuit currents.

The highest efficiency is achieved in slow switching conditions. In such conditions and in

steady-state, the main power losses are described by a simple model and can be divided

into load dependent losses and load independent losses [20].

2.4.1 Load-Dependent Losses

Load-dependent losses are revealed when the charge pump is connected to a load and the

output voltage decreases in the presence of a load currentIO > 0. These losses are mod-

elled through a non-zero equivalent output resistance RO and the corresponding power

dissipation is

PLD= RO I2O. (2.9)

This formula indicates that lower load dependent losses can be achieved by reducing

the output resistance ROgiven in (2.7) which is inversely proportional to the product of the

switching frequencyfand the total capacitanceCT.


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33/123


which is maximum when the output current is equal to

IO =

GIVDD

A A2

GIRO + 1

1

. (2.14)

In this condition, the ratio

PLIPLD

= A2

GIRO

1 A2

GIRO+ 1 1

2 , (2.15)

is larger than one for any acceptable value ofA, GI, and RO. In other words, at peak

efficiency, load-independent losses are larger than load-dependent losses (i.e. PLI > PLD

atIO=IO). In general, load-independent losses dominate at low currents such that

0 IO < VDD

GI/RO, (2.16)

while for higher currents load-dependent losses are larger. Therefore minimizing load

independent losses is a crucial design objective, especially for charge pumps meant to

operate at peak efficiency or at low currents.

2.5 Analysis of Single-Sided Charge Pumps

Several single-sided CP structures have been proposed in the literature, each suited to meet

specific application requirements and address process constrains. Single-sided CPs transfer

charge packets to the load once every switching period. Indeed, the differences between

CPs structures correspond to the configuration of their capacitors and switches in each

phase. Exploring different CPs structures is motivated by choosing the appropriate struc-

ture in order to maximize the efficiency.

In the Dickson CPs in Fig. 2.6(a) [2], MOS switches controlled by non-overlapping

control phases eliminate the voltage drops associated with the diodes used in the classic


34/123


configuration [1]. Each transfer capacitor is charged to the voltage of the preceding stage

and then boosted byVDD to charge the next stage at a higher voltage. Ideally, a circuit with

Nstages has a voltage gainA = N+ 1, an output resistanceRO = N2

/(f CT), and aninput conductanceGI= 0.

In the heap CP in Fig. 2.6(b) [16], the voltage across each capacitor never exceeds VDD

making this type of CPs attractive for implementations in low-voltage processes. A heap CP

with Nstages has an ideal voltage gain A= N+ 1, an output resistanceRO = N2/(f CT),

and an input conductanceGI= 0.

The Fibonacci CP with three capacitors shown in Fig. 2.6(c) [12] has the same ideal

gain as the Dickson and the heap CPs with four capacitors (Figs. 2.6(a) and 2.6(b)). This

two phase CP single-sided structure has the highest attainable gain for a given number of

capacitors [13]. The gain of an ideal Fibonacci CP withNstages isA = FN+1, whereFN

is theN-th Fibonacci number, withF0 =F1 = 1and Fi = Fi1+ Fi2 fori >1. In the

case of equal transfer capacitorsCi = CT/N, the charge multiplier factors areaci =FNi

fori = 1to N, the output resistance of this topology is RO = NfCT

Ni=1(FNi)

2, and the

input conductanceGI= 0.

2.5.1 Optimization of the Output Resistance

To minimize the output resistance of any CP for a constant total capacitance CT, we sub-

stituteC1= CT C2 ... CN in (2.7) and we set the partials with respect to capacitors

Ciequal to zero, which means

ROCi

= 1

f

a2ci

CTC2 ... CN

a2ciC2i

= 0, (2.17)

fori= 2toN [18].

Since the available silicon area is a critical constraint for a designer, the CPs capacitor

sizes, which are the largest portion of an integrated CP, are optimized to improve CPs per-


35/123


0

VDD

12 21

1 12 2 1

C1

C2

C3

C4

0

C2C1 C3 C4

(C1+C3 ) (C2+C4 )

VDD

VDD

VO

Load

0

IO

(a) Four-stage Dickson CP.

1

2

C1

C2

C3

C4

00

2 2 2

1

00

11

2

VDD

1 1 1 1 VO

Load

0

IO

C3C2C1 C4

C1 C2 C3 C4

(b) Four-stage heap CP.

(c) Three-stage Fibonacci CP.

Figure 2.6: Schematic diagrams of conventional charge pumps with parasitic capacitances.

formance. Considering the three structures (i.e. the Dickson, the heap, and the Fibonacci)

and the calculated charge multiplier factors for each structure, the optimal capacitor sizes

are found. The optimal performance of anN-stage CP is not necessarily obtained when

capacitances are equal, but when they scale as a function of the charge multiplier factor.


36/123


C1 C2

C3

C4

C1

C2

C3

C1

C2

C3

C4

Fibonac

ci

Dickson

Heap

A = 5

C1

C2

C3

C4

C1

C2

C3

C4

C5

C6

C7

C1

C2

C3

C4

C5

C6

C7

A = 8

Fibonac

ci

Dickson

Heap

C1

C2

C3

C4

C5

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C12

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

A = 13

Fibonac

ci

Dickson

Heap

C11

Figure 2.7: Sketch of capacitors with optimal size of Dickson, heap, and Fibonacci CPs of

equal area and gain (i.e. leftA= 5, centreA= 8, rightA= 13).

For instance, the optimal performance of anN-stage Fibonacci CP is when capacitors are

scaled as the Fibonacci sequence with the largest capacitor next to VDD and the smallest

next to the load.

When the capacitors are optimized as shown in Fig. 2.7, the three CPs have a simi-

lar performance. In this case, the trade-off between gainA and output resistance can be

expressed as [18]:

RO =(A 1)2

f CT. (2.18)

2.5.2 Single-Sided Charge Pumps with Parasitic Capacitances

The design parameters for the CPs shown in Fig. 2.6 are calculated as a function of and

. For the Dickson CP the gain is

A= N

1 + + 1, (2.19)

the output resistance is

RO= r

f CT, (2.20)

with

r= N2

(1 + ), (2.21)


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0

0.2

0.4

0.6

0.8

1 3 5 7 9 11

g

Voltage Gain A

Dickson

Fibonacci

Heap

Figure 2.8: Normalized input conductanceg of Dickson, heap, and Fibonacci CPs as afunction ofA, when= 0.1and= 0.05.

and the input conductance is

GI=f CT + +

1 + , (2.22)

with

g= + + 1 +

. (2.23)

The analytical expressions for A, r, and g in the case of the optimized heap and the

Fibonacci CPs are collected in Table 2.1 and 2.2. The performance comparison indicates

that the Dickson CP performs the best since bottom plate parasitics does not contribute

to the gain reduction as in other structures where a significant portion of charges delivered

to the output is shared with the parasitic capacitances Ciassociated with the bottom plate

of the transfer capacitors. Also, the input conductance of the Dickson CP is independent

of the number of stages. Accordingly, the load-independent losses of Dickson CPs depend

only on and , the total capacitance, the switching frequency, and V2DD. On the other

hand, the heap CP has the worst performance, exhibiting a much lower gain than other

topologies at large number of stagesN.


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0

4

8

12

16

1 2 3 4 5

r

Voltage Gain A

Dickson

Fibonacci

Heap

Figure 2.9: Normalized output resistance r of Dickson, heap, and Fibonacci CPs as afunction ofA, when= 0.1and= 0.05.

Table 2.1: Heap CP Design Parameters.N Parameters

1 A = 1 + 11+r = 1

1+

g = ++1+2 A = 1 + 2+1++(3+)+2

r = 2(2++)

(1++(3+)+2)

g = (5++2)(++)2(1++(3+)+2

3 A = (2++)(2++(4+)+2)

1+2

(1+)+(2+)(3+)+(3+2(3+))r =

3(1++)(3++)(1+2(1+)+(2+)(3+)+(3+2(3+)))

g = ((++)(14+2+4(2+)+(14+3)))(3(1+2(1+)+(2+)(3+)+(3+2(3+))))

4 A = ((1++(3+)+2)(5+2+(5+)+(5+2)))

(3(1+)+(3+)(2+3(2+))+2(5+3(3+))+(1+)(1+(3+)2))

r = 4(2++)(2+2+2(2+)+(4+))

(3(1+)+(3+)(2+3(2+))+2(5+3(3+))+(1+)(1+(3+)2))

g = ((++)(14+2+4(2+)+(14+3)))(3(1+2(1+)+(2+)(3+)+(3+2(3+))))


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Table 2.2: Fibonacci CP Design Parameters.

N Parameters

1 A= 1 + 11+

r= 11+g= ++

1+

2 A= 1 + 21+r= 41+

g= ++1+

3 A= (1+)+(2+)(5+2(4+))(1+)(2++(5+)+22)

r= 4 2(1+)+((2+)(4+5)(1+)(2++(5+)+2

g= (++)(3(1+)+(2+)(7+8))4(1+)(2++(5+)+22)4 A= 48+(1+)(8+5)+(4+)(35+6(4+))

(3+2)(2+3)(1+(3+))+2 (1+)2+(1+)(7+(16+7))

r= 7 42+22(1+)+(19+3(12+5))+(109+(80+17))

(3+2)(2+3)(1+(3+))+2(1+)2+(1+)(7+(16+7))

g= (++)(108+52(1+)+(49+92+382)+(277+200+422))

(7(1++(3+)+2)(6++(13+)+62))

Examples of numerical values ofgand rfor various values ofA are respectively shown

in Fig. 2.8 and Fig. 2.9, where they are plotted as function of Afor = 0.1 and= 0.05. In

the Dickson CP, the normalized input conductanceg does not change with the number of

stages, while the voltage gainA and the output resistance does not depend on the value of

, because the circuit can be built so that the bottom plates of all capacitors are alternately

connected to ground andVDD without affecting the charge transfer through the CP. For the

Fibonacci and heap CPs, the normalized input conductance g depends on the number of

stages because bottom plate parasitic capacitances share a portion of the charge transferred

to the output and therefore affect performance.

2.6 Analysis of Double Charge Pumps

The output voltage ripple can be reduced by splitting the CP in two parts, each part with half

the total capacitance and feeding the load in a different half period [4]. This configuration,

called double CP, is usually implemented as a parallel connection of stages operating with

opposite phases. Fig. 2.10 shows implementations of double CPs of the circuits seen in the


40/123


last section. The voltage gainA, the output resistance RO, and the input conductance GI

are the same as the single-sided CPs when the total capacitance is the same. On the other

hand, the voltage ripple defined as the peak to peak variations in the DC output voltage, is

halved with respect to the single-sided charge pump and can be expressed as [21]

Vripple= IO

2 f CL, (2.24)

whereCLis the load capacitance.

Another CP structure used to achieve a high voltage gain is the exponential CP shown

in Fig. 2.10(d). The gain of an ideal exponential CP withNstages isA = 2N

. In the case

of equal transfer capacitorsCi = CT/(2N), the charge multiplier factors are aci = 22(Ni)

for i= 1to N, the output resistance is RO= NfCT

Ni=12

2(Ni), and the input conductance

GI = 0. The optimal performance of an exponential CP withNstages is obtained using

(2.17), and the minimum output resistance is when capacitors are sized as

Ci= 2Ni

2N

1

CT. (2.25)

A comparison between the optimal capacitors sizes of an ideal Dickson and an ideal

exponential CPs with the same performance is shown in Fig. 2.11

2.6.1 Double Charge Pumps Performance with Parasitic Capacitances

The analytical expressions forA,r, andg in the case of the optimized exponential CP are

collected in Table 2.3, while A, r, and g for the double Dickson, double Fibonacci, anddouble heap CPs are the same as those of the single-sided implementations. Comparing the

performance of the exponential CP to the double Dickson, again the Dickson CP performs

the better since bottom plate parasitics does not contribute to the gain A reduction as

in other structures where a significant portion of charges delivered to the output is shared

with transfer capacitances bottom plate parasitics and wasted every clock cycle. Also, the


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2

IO

1

0

VDD VO

Charge

pump 2

1

2

1 23

33 30

Charge

pump 1

0

OUTIN

OUTIN

0 0

Figure 2.12: Charge reuse configuration of a generic double CP.

save charges drawn from the power supply), if pairs of such nodes with complementary

voltage swings (i.e. 180 out of phase) are equalized before each switch event. Double CPs

clocked with opposite phases, have pairs of such nodes in each stage. Thus, charge reuse

can be applied to all stages of any double CP [20] as shown in Fig. 2.12.

Fig. 2.13 describes the charge reuse concept where an equalization switch driven by an

appropriate control signal is used to bring the nodes (X and X ) to an intermediate voltage

level. The time required by this operation is much smaller than the time needed for charging

the transfer capacitors, because only a small fraction (e.g. ) of the capacitance is involved.

Therefore, the time allocated for the equalization has a limited impact on the operating

frequency.

The principle of charge reuse is based on equalizing the voltages of the parasitic ca-

pacitances in each stage. The equalization switch controlled by phase 3 brings both ca-

pacitances to an intermediate voltage before each switch event, therefore the amount of

charges drawn from the power supply for charging parasitic capacitances is less than the

amount needed by conventional CPs. As a consequence, charge reusing reduces the load-

independent losses. As design examples, we consider double Dickson CP, double Fibonacci

CP, and a double heap CP. Applying charge reusing requires splitting the circuits into two


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(a) Circuit to describe the charge reuse.

(b) Clock phases and internal

nodes voltage waveforms.

Figure 2.13: Description of charge reuse concept in double charge pumps.

symmetrical parts (double CP) driven by complementary control signals and operating in

parallel, as shown in Fig. 2.12. Examples of charge reuse application to the heap and Fi-

bonacci CPs are shown in Fig. 2.14(a) and 2.14(b), respectively. In these cases, charge

reusing not only reducesGI, it also increasesAandRO.

2.8 Simulation Results with Charge Reuse

Three CP types (i.e. the Dickson, the heap, and the Fibonacci charge pumps) were designed

and simulated with Spectre using MOS switches and poly-diffusion capacitors in a standard

0.18-m technology. Fig. 2.15 shows the normalized input conductanceg versus the gain

A. The reduction ofg (and consequently ofPLI) for the Dickson CP is 50%. On the other


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(a) Three-stage double Fibonacci CP with charge reuse.

(b) Four-stage double heap CP with charge reuse.

Figure 2.14: Schematic diagrams of double charge pumps with charge reuse (parasitic

capacitances are omitted for simplicity).

hand, the improvement for the Fibonacci and heap CPs is less than 50% for gains larger

than two and depends on the number of stages. Fig. 2.16 shows the output characteristics

and the conversion efficiency of the three CP types. The results are obtained when N= 4

for Dickson and heap CPs and when N= 3for the Fibonacci CP. The output characteristics

of the Dickson CP is not changed, while the open-circuit gains of the Fibonacci and heap

CPs with charge reusing are improved (i.e. 1.9% and 8.7% increase, respectively), because

parasitic capacitances draw less charge from the primary charge transfer path. More signif-

icantly, charge reusing substantially improves the overall conversion efficiencyin any CP

type: The maximum efficiency increases from 52.5% to 63% for the Dickson CP and from


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0

0.2

0.4

0.6

0.8

1

1 3 5 7 9 11

g

Voltage Gain A

Dickson

Fibonacci

Heap

Dickson-reuse

Fibonacci-reuse

Heap-reuse

Figure 2.15: Normalized input conductanceg versus voltage gainAfor the three CP typesin standard configuration and with charge reuse, when = 0.1, and= 0.05.

23% to 31% for the heap CP, and from 43% to 53% for the Fibonacci CP. Reusing wasted

charges reduces the current drawn from the power supply and increases the conversion

efficiency.

2.9 Summary

In this chapter, a method of analysis for evaluating integrated charge pumps performance

and optimizing their capacitor sizes is determined. The analysis allows the calculation of

the voltage gain A, the output resistance RO, and the input conductance GI and conse-

quently the major power losses (resistive and dynamic power losses) of any integrated CP

can be evaluated. Moreover, charge reuse is applied to with the result of reducing the dy-

namic power losses and improving the overall conversion efficiency. The technique can

be applied to any double CP. The application of charge reuse results in reduced dynamic

power losses and a significant portion of wasted charges is recovered every clock cycle.

The Dickson CP has the best performance in terms of the voltage gain and power effi-

ciency. When charge reuse is considered the double Dickson (voltage doubler) CP has a


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0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 100 200 300 400 500 600 700 800

ConversionEfficiency

IO

Dickson

Fibonacci

Heap

Dickson-reuse

Fibonacci-reuse

Heap-reuse

( A)

(a) Conversion efficiency.

0

1

2

3

4

5

6

7

8

9

10

0 100 200 300 400 500 600 700 800

VO

IO

Dickson

Fibonacci

Heap

Dickson-reuse

Fibonacci-reuse

Heap-reuse

( A)

(b) Output characteristics.

Figure 2.16: Conversion efficiency and output characteristics of the three CP types as a

function of the output current IO, whenn = 4for Dickson and heap CPs and N = 3forthe Fibonacci CP,VDD = 1.8V,CT= 200pF,f= 10MHz, = 0.1, and= 0.05.

better performance.


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Chapter 3. Design

Chapter 3

Design

3.1 Introduction

The designer of integrated charge pumps has to face the constraints of the fabrication tech-

nology. Typically, integrated CMOS circuits share a single substrate, thus the chip layout

geometry and the proximity of the process layers to the substrate produce parasitic capac-

itive couplings. The existence of such parasitics limits the charge pump performance and

efficiency. Moreover, the performance of a CP depends critically on how its MOS switches

are controlled. First of all, the overdrive voltage applied to turn a switch on determines its

on resistance and drain-to-source voltage drop, which, in turn, affect the conversion effi-

ciency and voltage gain. In addition, the maximum and minimum voltages applied to the

switch gates affect the dynamic power losses and can be constrained by the device voltage

rating. Finally, precision and adjustability in controlling the switch affect the frequency

of operation (which trades off with the silicon area required for meeting design specifica-

tions) and can prevent short-circuit currents from nodes at higher voltages to nodes at lower

voltages during transitions (which affect efficiency).

Switch bootstrapping improves conduction during the on state by connecting a given

voltage between the gate and source terminals, typically by using a capacitor pre-charged

34


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Chapter 3. Design 35

during the off state [22]. Moreover, reusing some of the charges that are normally wasted

for charging and discharging parasitic capacitances at each cycle is a promising approach

for reducing power dissipation in charge pumps [11].

In this chapter, we analyze and discuss the design aspects of integrated voltage doubler.

First, the standard voltage doubler limitations are pointed out. Second, we propose a new

voltage doubler with a switch bootstrapping technique, where the voltages driving the gates

of nMOS and pMOS switches can be controlled both in terms of voltage swing and timing

such that limitations of standard voltage doubler are alleviated. The application of the

technique is demonstrated through the design of various voltage doublers. Also, dynamic

power losses due to parasitic capacitances are addressed and a method for reducing them

through charge reuse is described. Simulations of the various voltage doublers confirm the

effectiveness of the proposed techniques which result in an improved overall performance.

Technology and design constrains are addressed as well, and design trade-offs are discussed

in order to fine tune the circuit components.

3.2 Voltage Doubler

In the bootstrapped Dickson CP [2], switch voltage drop, varying on resistance, and low

conduction are alleviated by using four non-overlapping clock phases, which also prevent

short-circuit currents from nodes at higher voltages to nodes at lower voltages. This imple-

mentation needs the generation of four appropriate clock phases and MOS switches able to

withstand high voltages.

The output voltage ripple can be reduced by splitting the CP in two parts each with

half the total capacitance and feeding the load in a different half period [4] as depicted in

(2.24). This configuration, called double CP, is usually implemented as cascade connection

of voltage doublers [5], [6], which need only two clock phases instead of four. As shown

in Fig. 3.1, each modular stage is made of two latched CMOS pairs (Ni , P

i , Ni, Pi),


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( (

Figure 3.1: Conventional 2-phases cross-coupled voltage doubler stage.

two transfer capacitors (Ci, Ci), and two drivers (N

Di-P

Di, NDi-PDi), and does not need

dedicated bootstrap drivers. Vi is the output voltage of the i-th stage and Vi is the input

voltage. The transfer capacitors of each stage are alternately charged to the voltage of the

previous stage and then boosted byVDD to charge the next stage at a higher voltage. The

complementary voltage swings on the internal nodes are used to control the switches of

opposite branches. Since the maximum voltage rise from Vi1 toVi is VDD, the voltage

across each device is never higher thanVDD and low voltage MOS switches can be used.

In steady state, the operation of the voltage doubler (Fig. 3.1) is as follows; during the

first half cycle, 1= VDDand 2= 0, transistors Ni, NDi, P

i , and P

Diare on, and transistors

Ni, N

Di, P

i,and P

Diare off; transfer capacitorC

iis charged toV

i

1 throughN

iandN

Di,

while transfer capacitor Ciis boosted to Vi1+VDDthrough P

i and P

Di. During the second

half cycle, and transistorsNi , N

Di, Pi, and PDi are turned on, and transistorsNi, NDi, P

i ,

and PDi are off; transfer capacitor C

i is charged to Vi1, while transfer capacitor Ci is

boosted to charge next stage toVi1+ VDD.


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conditions the on resistance of each switch increases and ifV Vt the switches are off.

The CP output resistance given by

RO = N

(1 + ) 2 f Ci coth

1

f CiRON

(3.5)

increases as well, thus making the load-dependent lossesPLD=ROI2O larger. Such losses

are particularly significant at high output currents and lowVDD, the maximum output cur-

rent IOmax in (3.3) is therefore reduced and a new maximum output current limit is ob-

tained. In other words, for the MOS switch to conduct in the triode region, it must satisfy

the relation

V Vt (3.6)

which imposes an upper bound onIO, and the maximum output current becomes

IOmax= (VDD (1 + )Vt) 2f Ci (3.7)

3.3.2 Load-Independent Power Losses

In integrated voltage doublers, load-independent power losses (also called dynamic or

switching losses) can be calculated through the non-zero equivalent input conductance GI

as explained in Chapter 2, so that the corresponding power dissipation is approximated as:

PLI= + +

1 + f CTV2DD (3.8)

Accordingly, the load-independent power losses of a voltage doubler depend only on

and, the switching frequency, the total capacitance, and V2DD, and are independent from

the number of stages.

From the analysis in chapter 2, load-independent losses are the major power losses at


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Figure 3.2: 2-phases cross-coupled voltage doubler stage.

low currents. Therefore, based on the design specifications, minimizing load-independent

losses for voltage doublers meant to operate at maximum efficiency or at low currents is

a critical design consideration. From (2.21), (2.22), and (2.16), a limit condition when

load-independent losses in voltage doublers dominate is found and can be expressed as

IO

+ + f CTVDD

N . (3.9)

3.3.3 Short-Circuit Power Losses

In the conventional cross-coupled voltage doubler Fig. 3.2, each stage is seen as a CMOS

latch, the gates of switches Ni ,P

i andNiPiare driven by the voltage rise on nodesBi

andB i. At this point, three major cases of reversion and short-circuit losses are identified.

First, in the time slot during transitions when the voltage rise across the stage is higher

than the overdrive of pass transistors Ni orN

i (i.e.V Vi1+ Vt), a reversion current

flows from Cior C

i back to nodeVi1. Second, in the time slot during transitions when the


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voltage rise across the stage is lower thanVi Vt (i.e.V Vi Vt), pass transistorsPi

orPi are partially on, causing a reversion current from nodeVi back toCi andC

i . Third,

the short time slot, when the CMOS pairsNi-Piand N

i-P

i are conducting simultaneously,

generates a short-circuit current from the higher-voltage node Vi to the lower-voltage node

Vi1. All these losses can degrade the CP efficiency and the output voltage [24]. The short-

circuit power consumption depends mainly on the voltage rise per stage V, the input

transition time, the threshold voltageVt, and transfer capacitors(Ci, C

i)[25]

PSC=PSC(k, Vt, V , , f , C i). (3.10)

Short-circuit losses are particularly significant at low output currents , whenV is high

compared toVt, while they are negligible when

V 2Vt (3.11)

A limit condition on the output currentIO range where short circuit losses are signifi-

cant, can be obtained from (3.2) and (3.11)

IO 2f Ci(VDD 2 (1 + )Vt) (3.12)

The problem can be alleviated by driving pMOS switches with level shifters generating

nonoverlapping control signals varying from 0 to Vi [6] or by using two parallel stages

generating control signals varying fromVi1toVi[8]. The problem can be solved by using

four nonoverlapping clock phases and bootstrapping the pMOS pairs [9] or by adding series

switches and using five phases [26].


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Figure 3.3: Proposed bootstrapping technique applied to a voltage doubler stage.

3.4 Proposed Switch Bootstrapping Technique

The problem of the increased MOS on resistance (reduced driving capability) can be solved

by boosting the voltage driving the main CMOS switches with a voltage swing that does

not vary withIO [10], a solution that improves the driving capability at low VDD, but does

not alleviate short circuit losses.

In order to prevent short-circuit currents and the reduced current driving capability ob-

served in the conventional voltage doubler, a new modular bootstrapping technique that

allows full control on MOS switches is proposed [27] and [28].

The circuit in Fig. 3.3, provides both control on the timing of the switch transitions

(therefore preventing short-circuit losses) and on the gate voltage swings (therefore im-

proving driving capability).

Having same pass transistors, transfer capacitors, drivers, and nonoverlapping phases as

the conventional one, the proposed circuit includes an nMOS cross-coupled clock booster


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(Nbi, N

bi, Cni, C

ni) driven by 1 and 2 and a pMOS cross-coupled clock booster (Pbi,

Pbi, Cpi, C

pi) driven by 1 and 2. Short-circuit losses are prevented because the volt-

ages applied between the gate and source terminals of pairs Ni -N

i andNDi -N

Di have

nonoverlapping transition times with both voltages low, whereas the gate-to-source volt-

ages of pairsPi-P

i and PDi-P

Dihave complementary transition times with both voltages

high.

The timing of switch transitions and the nonoverlapping slots can be adjusted by con-

trolling the main clock phases. The amplitude of the gate voltage swings does not depend

on output current or number of stages and is controlled by the low and high levels of the

main phases, typically varying from 0 to VH = VDD. The corresponding voltage control-

lingNi andN

i goes fromVi1 (off) toVi1+ VH(on) and the voltage controllingPi and

Pi goes from Vi VH (on) to Vi (off). In steady state, the maximum voltage across any

switch isVDD and internal voltages are within the range from 0 to the maximum CP output

voltage.

3.5 Charge Reuse Technique

Since load-independent losses due to parasitic capacitances have a strong impact on con-

version efficiency. Dynamic power losses can be reduced by reusing some of the charges

wasted in charging or discharging the parasitic capacitances each cycle [11], [20]. In partic-

ular, if we consider those internal nodes of a voltage doubler that are connected to ground

through a switch at every cycle and have complementary voltage swings, the parasitic ca-

pacitances associated with them are charged to a certain voltage and then discharged to

0, therefore a part of that charge can be reused (and therefore the input conductance is

reduced). This can be accomplished if we redirect some of the charges wasted at falling

nodes to charge parasitic capacitances at rising nodes before each switch event.

To that end, switches driven by appropriate control signals are used to equalize the


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voltages of the parasitic capacitances. The time required by this operation is much smaller

than the time needed for charging the transfer capacitors, because only a small fraction

(e.g. , typically 1.5% to20%) of the capacitance is involved and equalization switchesare sized to complete charge reuse within each nonoverlapping time slot. Therefore, the

time allocated for the equalization has a limited impact on the voltage doubler operation.

Furthermore, the control signal can be generated through a NOR gate directly from the

nonoverlapping control phases that are already needed to avoid short-circuit losses.

3.5.1 Charge Reuse Voltage Doubler Design

The design of a voltage doubler stage with charge reuse is shown in Fig. 3.4. The parasitic

capacitancesCi and C

i are alternately charged toVDD and discharged to 0. The equal-

ization switch controlled by a NOR circuit brings both capacitances toVDD/2before each

switch event, therefore the amount of charges drawn from the power supply for charging

parasitic capacitances is half the amount needed by the conventional circuit. As a conse-

quence, charge reusing can reduce the load independent losses by a factor two. Circuit

analysis confirms that the input conductance of the voltage doubler CPs with charge reuse

is half that of conventional voltage doubler CPs:

GI=f CT + +

2 (1 + ) , (3.13)

while the voltage gainAand the output resistanceRO are unchanged.

3.6 Design Constrains

The design of efficient and high performance CPs is usually associated with several design

concerns that need to be addressed. Design considerations on MOS switches and boot-

strapping circuits play an important role in the proper operation of the charge pump.


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Figure 3.4: Bootstrapped voltage doubler stage with charge reuse.

3.6.1 MOS Switches

The use of MOS transistors as switches requires that switches are designed appropriately.

MOS switches with a large aspect ratio are required mainly for three reasons. First, large

switches (i.e. with low on resistances RON) reduce resistive power losses. Second, to ensure

a small time constant (i.e. fast transient) of the charge transfer paths, large switches are

needed. Third, charge pumps require large switches if they have to deliver large currents.

In addition, the maximum switching frequencies at which a charge pump can operate

depend on the time constants of the individual stages. Each stage can be viewed as an

RC network, which needs MOS switches to have a relatively low on resistances so that

capacitor voltages can settle within the clock semi-period. Therefore, a number of time

constants within the half clock cycle are required for a complete charge transfer, and the

following relation must hold:


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TON>> RON Ci (3.14)

A frequency increase requires a reduction in the on-resistance of transfer switches,

which can be obtained by increasing the transistors aspect ratios (W/L), which also re-

quires larger drivers to maintain sharp transitions, and call for longer nonoverlapping time

(due to larger gate capacitance and, hence, transition times). This increases the contribu-

tions of the switches parasitic capacitances that adds to the capacitor parasitics, and, hence,

reduces the voltage gain A, increases the dynamic power losses, and reduces the efficiency.

3.6.2 Bootstrapping Circuit

A key design issue of the proposed circuit involves sizing the boosting capacitor adequately

to bootstrap the gate of the pass transistors with the required overdrive voltage. The boosted

voltage on the gate of the pass transistor is reduced because loading capacitance Cload

(here we refer to MOS pass transistor capacitances and other parasitic capacitances) share

a portion of the charge. The added bootstrapping circuits are not on the primary charge

transfer path. However, these capacitors must be able to supply sufficient voltage swing to

the gate of the pass transistor and other parasitic capacitances. The boosted voltage can be

expressed as

Vg =Vi1+ VDDCN

CN+ Cload. (3.15)

In this design, the values of the bootstrapping capacitors CNare approximately 10 times

Cload. This ensures that corresponding voltages controlling pass transistors are within the

required range. Furthermore, the precharge transistors (Nbi,N

bi,Pbi,P

bi) allow bootstrap-

ping capacitors to be charged to the required voltage level. The time required for such

operation (RCdelay) is much less than the time required for charging transfer capacitors,

because bootstrapping capacitors are small and depend mainly on the gate size of the pass


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the bootstrapping capacitor size. As the bootstrapp

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