TWEPP 2018, 19.9.2018Antwerp, Belgium

TID models for 65nm transistors- PDK integration

Aristeidis Nikolaou, Matthias Bucher, NikosMakris, Alexia Papadopoulou, Loukas Chevas,Technical University of Crete (TUC), Chania, Greece

Giulio Borghello, Henri Koch, KostasKloukinas, Tuomas Poikela, Federico Faccio,CERN

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Introduction● Project participants:

– Technical University of Crete (TUC)– CERN

● The project in 3 phases:– TID measurements from a test device (CERN)

● G. Borghello, H. Koch, F. Faccio

– Modelling the TID effects based on measured data (TUC)● M. Bucher, A. Nikolaou, A. Papadopoulou, L. Chevas

– Integration of the models into an existing Process Design Kit (PDK) (CERN/TUC)

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Measurements● A test chip with single devices designed at

CERN

● Test chip included regular-Vt and enclosed gate layout transistors (EGT/ELT)

● Irradiated at CERN using X-ray source

● TID 100,200,500 Mrad, at -30/0/25 °C

● Annealing effects not taken into account

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Modelling of TID effects

Nikolaou et al, MOCAST 2018

BSIM4.5 models forTID 100, 200, 500 Mrad,and temperatures of-30, 0 and 25 °C

IMPORTANT: Models areonly valid for these characterised conditions

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Project deliverables

-30° 0° 25°

TID 100 OK OK OK

TID 200 OK OK OK

TID 500 OK OK OK

Regular-Vt, standard layout

-30° 0° 25°

TID 100 OK OK OK

TID 200 OK OK OK

TID 500 OK OK OK

Regular-Vt, ELT

To be done: High-Vt + low-Vt transistors (later this year)TSMC 65nm digital library re-characterisations

+ schematic symbols for ELT

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Model integration to PDK

TID models made available as process corners,can be used in simulation sweeps

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ELT schematic symbols

Width estimated viaSKILL callback

Dedicatedsymbolfor ELTs

Symbols made available by INCLUDE library in the cds.lib

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Inverter delay simulation

Delay spread (no TID):4.9ps

Delay spread (with 500 Mrad):8.06ps

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Library char. with Liberate● Trial run of tcbn65_lp

characterisation done (no QRC)

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TID Models availablevia CERN gitlab

(and later as .zip/archive),access by request

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Summary● TID transistor models available for TSMC 65nm PDK● Regular-Vt (including ELT) are provided at the moment● If interested in the models, please contact CERN ASIC

support by email: foundry.services@cern.ch● High/low-Vt models available later this year● Digital library characterisation with Liberate and Liberty

(.lib) file for synthesis/place N route to be done

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Thank you for your attention!

Please refer to the following publications for further technical details:

1. L. Chevas, A. Nikolaou, M. Bucher, N. Makris, A. Papadopoulou, A. Zografou, G. Borghello, H. D. Koch, F. Faccio,

"Investigation of Scaling and Temperature Effects in Total Ionizing Dose (TID) Experiments in 65nm CMOS",

25th Int. Conf. Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia, Poland, June 21-23, 2018.

2. A. Nikolaou, M. Bucher, N. Makris, A. Papadopoulou, L. Chevas, G. Borghello, H. D. Koch, K. Kloukinas, T. S. Poikela, F. Faccio,

"Extending a 65 nm CMOS Process Design Kit for High Total Ionizing Dose Effects",

IEEE Int. Conf. on Modern Circuits and Systems Technologies (MOCAST), pp. 1-4, Thessaloniki, Greece, May 7-9, 2018.

3. M. Bucher, A. Nikolaou, A. Papadopoulou, N. Makris, L. Chevas, G. Borghello, H. D. Koch, F. Faccio,

"Total Ionizing Dose Effects on Analog Performance of 65 nm Bulk CMOS with Enclosed-Gate and Standard Layout",

IEEE Int. Conf. on Microelectronic Test Structures (ICMTS), pp. 1-5, Austin, Texas, Mar. 19-22, 2018.