ISSN 1292-862

TIMA Lab. Research Reports

CNRS INPG UJF

TIMA Laboratory, 46 avenue Félix Viallet, 38000 Grenoble France

A DIGITAL CMOS CIRCUIT FOR REFLECTANCE THERMOGRAPHY

Benoît CHARLOT1, Kholdoun TORKI1, Gilles TESSIER2, Céline FILLOY2 and Danièle FOURNIER2

1TIMA, 46 Avenue Félix VIALLET, 38031 Grenoble, France.

2ESPCI, Laboratoire d’Optique Physique, 75005, Paris, France.

ABSTRACT We present the design, fabrication and measurement results of a digital CMOS integrated circuit dedicated to specific thermographic measurements. The goal of this measurement will be to evaluate the temperature map on the chip during specific computing cycles and to compare different temperature map measurement techniques. A method called thermoreflectance will be used to measure the temperature increase at the surface of the chip. This method is an optical measurement of the temperature of a surface by means of the measurement of variations of the reflection coefficient with temperature.

1. INTRODUCTION

In its continuous progression toward higher integration levels, VLSI technologies are now reaching several problems. One of the majors concerns is that the power dissipation is continuously rising as the technologies get higher in complexity, even with the lowering of transistor power consumption. This fact is illustrated in Figure1 that states according to the ITRS roadmap the estimated integrated circuit (IC) power dissipation for the years to come. Figure 1 gives the power dissipation for chips designed for standard packages and for packages with heat sinks. Even if new techniques for extracting the heat out of these chips are now in development [1], the temperature as well as the temperature gradients on the surface of the IC are now raising to important levels. These temperature levels are a problem since they can be the cause of an abnormal failure rate (the relationship between temperature of a device and its failure rate is exponential) or the signal integrity deterioration (the temperature rises the switching time of a logic cell).

Thermography and electrothermal simulations [2] [3] of integrated circuits could help prevent these problems by acting at the design level and on the place and route schemes.

On the other hand, IC designers are in the need of a measurement system that enables them to locate thermal hot spots on operating devices quickly and easily and provide them with high spatial resolution thermal maps of the device.

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Figure 1. Estimated IC power consumption for IC chips (ITRS roadmap 2003).

A specific integrated circuit has been designed and fabricated to be used as a benchmark for the evaluation of several thermographic measurement systems. Some thermographic techniques use lock-in detection and are sensitive to temperature variations, not to the continuous component of the temperature. In circuits working at high frequency, the temperature variations occurring within a single period can become very small, even though the CW component of the temperature increases. For these reasons, we have developed a chip which can work at high frequencies (a few hundreds of MHz), but can also be reset periodically to a zero power consumption. If this reset is triggered at a low frequency (a few hertz), even temperature variation-sensitive techniques can obtain quasi-CW temperature fields. The chip has been

Benoît CHARLOT, Kholdoun TORKI, Gilles TESSIER, Céline FILLOY and Danièle FOURNIER A Digital CMOS Circuit For Reflectance Thermography

implemented in a standard 0.35µm CMOS technology with an automatic synthesis/place/route technique with standard library cells in order to be representative of a large amount of ASICs that surrounds us in our everyday life. It is a purely digital circuit that performs several calculations such as multiplications and divisions. The main specificity is that it has a programmable deterministic and repetitive computing cycle in order to fit specific requirements of the thermographic measurement techniques.

The thermographic measurement techniques will have to produce temperature maps at the surface of the chip for a given internal computation cycle, a given frequency and with the best spatial and time resolution. Infrared-based techniques, being limited by diffraction to resolutions of the order of 10 µm, cannot be used for these measurements. Scanning thermal probe techniques offer excellent resolutions for surface temperature measurement, but this resolution is severely degraded when measuring through several micrometers of encapsulation or intermetal dielectric. Optical methods operating in the visible range offer excellent spatial and time-resolutions.

In the near future, we plan to test interferometric and time-resolved techniques [7]. This paper will focus on a first technique called thermoreflectance. This promising technique allows a non contact measurement of temperature variations with high spatial resolution. A section dedicated to the chip design will describe all the features of this specific device. Then a section will give the first results made on this chip.

2. CHIP DESIGN

The chip has been designed following several specifications: - the circuit must be representative of a large amount of

ASIC chips manufactured nowadays to be used as a benchmark for thermography techniques.

- the circuit must have a repetitive, determinist and controllable working cycle.

- the circuit must be easily testable, and not require the use of an IC tester. In order to fit all these requirements we use some

design techniques that were originally developed for the testing of ICs. The Built-In Self Test (BIST) technique consists in integrating a stimuli generator and a signature analyzer on the chip. A test vector sequence is generated by the stimuli generator and applied to the circuit. Results are then analyzed on chip by the signature analyzer. These chips are able to be tested without the need of a test equipment. In our case the designed circuit is composed

of a digital core performing logic operations designed with a BIST architecture. The IC has no other functions than being used for thermographic measurements.

The digital core of the circuit contains several blocs: adder/subtracter and multiplier/divisor that works on 8 and 16 bits. The chip embeds a stimuli generator that is composed of two programmable Linear Feedback Shift Resisters (LFSR). A schematic of this circuit is shown in Figure 2.

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Figure 2. Schematic of an 8 bits programmable Linear Feedback Shift Register made with scan path flip flops. This circuit produces repetitive pseudo random sequences (A and B) that will be computed in the chip (addition, multiplication) in a repetitive and determinist way.

A LFSR is composed of a set of D gates connected in

serial in a ring structure. Some logic cells (XNOR) are placed in a feedback scheme along the register. Following the feedback structure, the LFSR will produce pseudo random sequences of different length. In our case the D cells of the LFSR are replaced with scan path specific cells in order to program from the outside the feedback structure. By this way it is possible to tune the sequences. Two 8-bit LFSRs have been implemented. They will generate determinist sequences of 256 bytes: A and B. These two logic words will next be sent to logic blocs that will perform addition/subtraction (A+B)–A and multiplication/division (AxB)/A. The results are then compared with the initial value (B) to create an observable bit.

The circuit has been designed with a standard synthesis/place/route technique using standard cell library. The logic core has been synthesized with two different congestion levels resulting in two sizes of cores with different cell density. This has been done in order to analyze the effect of cell density on the temperature map. The ICs are shown in Figure 3 and they both have the same functionality and pin diagram.

The chip contains also an integrated clock generator. It is composed of a programmable ring oscillator that can

Benoît CHARLOT, Kholdoun TORKI, Gilles TESSIER, Céline FILLOY and Danièle FOURNIER A Digital CMOS Circuit For Reflectance Thermography

generate an on chip clock with 8 possible selectable frequencies ranging from 1.4 MHz to 225 MHz. It also can be driven by an external clock signal. The chips can be easily controlled with only 4 digital pins (Reset, Clock, VDD, and GND).

Figure 3. Optical photographs of the two chips with different congestion levels.

3. THERMOREFLECTANCE

Since the optical index is temperature-dependent, the reflectivity of most surfaces shows temperature dependence in the range of 10-3 to 10-5 K-1. Thermoreflectance microscopy [4]- [10] is based on the measurement of the reflectivity of the surface of a sample, from which a temperature mapping can be deduced.

This technique can deliver thermal images with high spatial resolutions since it is only limited by the illumination wavelength and numerical aperture of the microscope optics. Resolutions of 350 nm have been obtained recently with visible illumination and could be improved with an UV illumination. It is far better in comparison with infrared emission technique, for example. Here, we have used a CCD-based setup, in which the optical signal is sampled by acquiring 4 images during each period of the modulated phenomenon. As in a lock-in technique, simple calculation delivers a phase and an amplitude image, the latter being linearly related to the temperature, on a given material. For most cameras, f is limited to a few tens of Hertz. If the circuit works at high frequency, two methods can be used.

Using a heterodyne setup (Figure 4), the thermally induced optical modulation at the high frequency F can be brought to a lower frequency f, simply by illuminated the circuit with a light modulated at F+f. Although F can be as high as necessary, the synchronisation system limits this frequency due to its increasing complexity. Our synchronisation system is now able to image thermal phenomena up to 25 MHz.

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Figure 4. Schematic of the optical setup for thermo reflectance measurement.

Benoît CHARLOT, Kholdoun TORKI, Gilles TESSIER, Céline FILLOY and Danièle FOURNIER A Digital CMOS Circuit For Reflectance Thermography

Another method is to use a low frequency modulation (f) of the high frequency carrier supplied to the circuit. This can be achieved by periodically shutting on and off the high frequency operation of the circuit (reset). The camera is synchronized with this low frequency (4f), and the reflectivity variations which are measured are related to the low frequency component of the temperature.

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Figure 5. CCD Thermoreflectance measurement of the temperature rise on a meander shaped polysilicon dissipator implemented on a 0.8µ CMOS technology. Optical image (a) and thermal image (b) (arbitrary units).

Previous measurements [5] made on specific circuits have shown the interest of these techniques. Figure 5 shows a thermoreflectance measurement obtained on a meander shaped polysilicon dissipator implemented on a 0.8µm CMOS technology. The dissipator, as shown on the optical image (Figure 5(a)) is driven by an AC signal (25MHz) that is used to trig the measurement setup. The

dissipator is 0.3µm thick and 20µm wide. It is connected to bond pads by metal lines. The Figure 5(b) shows the thermal image. We can notice that the temperature rise is linked as expected with the current density in the dissipator. The color scale is in arbitrary units. In order to link the measurement with a temperature, a calibration step is required.

4. THERMOREFLECTANCE MEASUREMENTS ON DIGITAL IC

Thermoreflectance measurements have been made on

the digital IC described in the previous section. The circuit has been powered with two voltage references, 5V for the I/O pads and 3V for the digital core. The on-chip oscillator has been used for the clock. The chip has been illuminated at a wavelength of 614.5 nm with LEDs.

The circuit is commuted with the reset pin at a frequency of 7.5 Hz with a duty cycle of 50%. Images have been captured with a CCD camera (30 fps) using objectives ranging from X5 to X100.

Figure 6 shows the first thermoreflectance measurements on the digital chip. The images have been taken for three different clock frequencies: 40, 80 and 235 MHz. As expected, the temperature rise is more important with higher clock frequencies. In CMOS technologies the power consumption is driven both by the switching of the transistors (dynamic part) and by the gate leakage currents (static part).

Since this first measurement records the low frequency component of the temperature, thermal images show a quasi uniform distribution of the temperature on the surface of the digital core of the IC. However, the images show a slightly stronger signal at the bottom of the images. This can be explained by the fact that the lower part in the image correspond to final stages (close to outputs) on the computing process that have more switching activity than the first stages.

We can notice on the images the presence of vertical and horizontal lines that correspond to interconnection metal layers. This is visible also on Figure 7 that shows a zoomed view (X100) of the center of the digital core. A relatively strong thermoreflectance signal is visible in the interconnection layers, indicating higher temperatures. This is interpreted as follows.

First, thermoreflectance signals are driven by the derivative of the reflection coefficient with temperature dR/dT, which is material-dependent. Metals usually have a relatively high dR/dT coefficient compared to transparent dielectrics like SiO2 [11]. Stronger thermoreflectance are therefore obtained on metals even if the temperature is homogeneous.

Benoît CHARLOT, Kholdoun TORKI, Gilles TESSIER, Céline FILLOY and Danièle FOURNIER A Digital CMOS Circuit For Reflectance Thermography

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Figure 6. Thermoreflectance measurement of the temperature rise on the core of a digital IC. The vertical color bar indicates the relative reflectivity variations ∆R/R for three different values of clock frequency 40 MHz(a), 80 MHz(b) and 235 MHz(c). The images represent 250x250 µm on the sample.

Secondly, the power consumed by the chip is dissipated mainly in the transistors channels and in the metallic interconnection layer. The aluminium of the interconnection layers have a much higher thermal conductivity than SiO2, respectively ~230 W.m-1.K-1 and ~1.25 W.m-1.K-1, this leads to a more important temperature rise in the connection layers rather than in the oxides.

Further works are needed to evaluate the temperature both in the interconnection layer and in the isolation layers. An illumination wavelength outside of the absorption window of the Si3N4 passivation layer can prevent such problems by measuring the reflection variation only at the surface of the IC.

Figure 7. Thermoreflectance measurement of the temperature rise on the core of a digital IC, zoom view in the center of the core (image size 100x100 µm).

5. CONCLUSIONS

We present the design, fabrication and test results of a digital CMOS integrated circuit dedicated to thermal evaluation by thermography. Some results of thermoreflectance measurement on the digital IC have shown a static thermal map of the device, with a strong frequency dependence of the thermal dissipation.

Further work will concern the calibration of the measurements in order to obtain quantitative images, which is an interesting challenge since the chip is composed of different layers with different optical index and thermal conductivities. Next some experiments will be set up in order to see the temperature map along the computing cycle of the IC.

6. ACKNOWLEDGEMENT This work has been funded by the Groupement De Recherche (GDR 2503) “micro et nanothermique” of the Centre National de la Recherche Scientifique (CNRS).

Benoît CHARLOT, Kholdoun TORKI, Gilles TESSIER, Céline FILLOY and Danièle FOURNIER A Digital CMOS Circuit For Reflectance Thermography

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