timesquare : a multiform time simulation environment · december 3rd, 2008 safa 9 from constraints...

December 3rd, 2008 SAFA

TimeSquareTimeSquare ::A A multiformmultiform time simulation time simulation environmentenvironment

C. André, B. Ferrero, F. MalletAOSTE - I3S/Inria

Université de Nice Sophia AntipolisINRIA Sophia Antipolis Méditerranée

December 3rd, 2008 SAFA 2

OutlineOutline

• MARTE Time model• CCSL• TimeSquare• Examples


MARTE motivationMARTE motivation

• In the real world, SW and RTE designers– Use UML to draw graphs, vertices and edges, with fancy

adornments– Perform model transformations to their proprietary language that

makes its own assumptions and give its own semantics� Models are not merged but only stored in the same bundle

• MARTE defines a common ground (and semantics?) for building RTE models with UML– The MARTE Time model relies on CCSL to define interactions

among clocks (processes, actors, …)– MARTE should be extended for domain-specific purposes

Where to put the semantics itself ? In the OMG specification ?


Time model Time model -- ClocksClocks

• Any event (start/end of actions; send/receive of messages; transition being fired; …) is a Clock– When the distance between two successive occurrences of the event is

meaningful (like in Physical time) => Chronometric clocks– Otherwise => Logical clocks => Multiform time

• More formally, a clock is a five-tuple ⟨I, ≺, D, λ, u⟩– I is a set of instants (possibly infinite);– ≺ is a strict quasi-order relation on I;– D is as set of labels;– λ : I→D is a labeling function ;

– u is the unit.

• Clocks can be – discrete (I is a discrete set) - idx : I→ℕ*, idx is order-preserving

– or dense.Today, focus on discrete logical clocks


Time model Time model –– Time structureTime structure

• Several interdependent clocks are gathered within a time structure

• A time structure is a pair ⟨C, �⟩– C is a finite set of clocks;– � is a partial order relation on Uc∈C Ic

• From � we derive four instant relations:– Coincidence: ≡ ≜ � ∩ �– Strict precedence: ≺ ≜ � \ ≡– Independence: ‖ ≜ � ∪ �– Exclusion: # ≜ ≺ ∪ ≻


Time model Time model –– Clock relationsClock relations

• Clock relations define (infinitely) many instant relations

• Four categories of clock relations– Coincidence-based (synchronous)

• isSubClock, discretizedBy, isPeriodicOn , filteredBy …

– Precedence-based (asynchronous)• isFasterThan (precedes), alternatesWith …

– Mixed (asynchronous => synchronous)• sampledOn , delayedFor, timer, inf, sup …

– Quantitative (related to chronometric clocks)• hasStability, hasOffset, hasJitter, hasDrift …

• Clock Constraint Specification Language = concrete syntax– Non-normative annex of MARTE


TimeSquareTimeSquare purposepurpose

• Modeling and Analysis of timed systems

• Fully supports MARTE Time model – UML Profile for Modeling and Analysis of RTE systems– Logical and multiform time

• Clock Constraint Specification Language– Formal Timed extension to OCL

• Detects requirement inconsistencies• Exhibits one valid behavior (simulation)


TimeSquareTimeSquare functionalityfunctionality

1. Interactive clock-related specifications2. Clock constraint checking3. Generation of sequences of steps4. Displaying & exploring waveforms

VCD-compliant


From constraints to behavior (1/2)From constraints to behavior (1/2)

• At each simulation step, three phases:1. For each constraint determine the set of implied

“Boolean equations”

2. When all constraints are analyzed, determine the set of enabled clocks (E)

3. Select the set of clocks to fire (F)

Phase 3 is not necessarily deterministic => simulation policy (random, min, max/asap, …)

C


From constraints to behavior (2/2)From constraints to behavior (2/2)C S

Solver: Determine Enabled clocks

E

Select TBs to fire

F

Policy

declarative

Automated

transformation

configuration

:c →C N

behavior

SObjective: build sequences of steps that respect

Solution: SOS for a Kernel of CCSL.

User’s viewpoint: standard CCSL library provided

+ facility for user’s defined constraints + stochastic parameters

', , 'Fc c→S S


CCSL kernel (1/2)CCSL kernel (1/2)

0// forcing

// inhibition

// waiting next nth

// (strict) sampling

// non-strict sampling

// upto

:: !

!

^

1

| 0

|

|

|

|

t

t t

t n

t t

t t

t t

τ

•

=

o

�

�

�

( )

1// simple time base reference

// concatenation

// union = coarsest finer Sup

// intersection

// d

*

:

|

:

|

|

| ,

t

t t

t t

t t

t t

τ

σ

⊆

•+

=

⇝ efer

( )( )

2// sup = fastest slower Sup

// inf = slowest faster Inf

::

|

t t

t t

τ∧

= ∨ �

�

Clock & Instant Expressions

th// instant of

// last instant of a finite time base

::

| @ end

@ n tt n

t

ι =

0 1 2// simple clock expressions

// conditional clock expressionif then el

se

:: | |

| b

τ τ τ ττ τ

=

Terminating CExpr Non-terminating CExpr, c-independent

Non-terminating CExpr, c-dependent IExpr

CExpr


CCSL kernel (2/2)CCSL kernel (2/2)

( )1// basic constraints on clocks, cnt-independent:: | | # t tρ = ⊂ ⊸

( )( )

2// basic constraints on clocks, cnt-dependent

// basic constraints on instants

:: | |

| #| | | |

t tρ

ι ι

= =

≡

p

p

�

�⊸

Definition CRel

Basic CExpr, c-independent

Clock Constraint

// clock standard definition

// clock recursive definition

|

:

:d t

t t t

ρ τ•

= �

≗

Basic CExpr, c-dependent

1 2

// constraint conjunction

// simple relation

// conditional relation

|

if

::

| | |

|

d

b

γ γ γρ ρ ρρ

=

Clock & Instant Relations


Example of semantics ruleExample of semantics rule

( )( )1

1

1

(next)

, ,

1

, ite , ,^ ,

t c b a

n

c bt t n t t t a

ββ

=∧ =≅ ¬�

⊢

⊢

Boolean equationsimplied by t1 under c

Boolean equationsimplied by t under c

behaves like

Structure →Boolean Eqn System⇒ E

1

1 (RWnext 1) 0 ^1t F

t t t∈ ≅→≅

( )1

1

1 2

1 2(RWnext 2)

^ 1

1

^

t F

t Ft t

n

n t n

t

t

t∈

∈≅ ≅ −> →→ Conditional

rewriting rules

F ⇒ Rewritten Structure

1


ImplementationImplementation

• Plug-in developed with Ganymede Eclipse Modeling Tools

• CCSL parser: ANTLR 2.7

• Solver: JavaBDD• Waveforms: VCD compliant (IEEE Std1364)

• Available at: http://www-sop.inria.fr/aoste/dev/time_square/


Example 1: Example 1: EasterEaster


Example 2: Example 2: AADLAADL

t1 t2 t3

50 Hz 25 Hz

c_100 = IdealClk discretizedBy 0.01

Visual representation ?

50 Hz 25 Hz


Example 3: ABS and Example 3: ABS and EastEast--ADL2ADL2

Clocks associated with ports

Stochastic durations for communications and executions


Example 3: ABS and Example 3: ABS and EastEast--ADL2ADL2

• Gives a formal semantics to East-ADL2 timing requirements– Make the requirements executable


Example 4: Example 4: Digital FilterDigital Filter (1/2)(1/2)

( )_ 10 .1

/ _ _

/ _ _ / _

LINE LENGTH

Ready InWord

EndOfLine OutPixel

InWord OutPixe PIXELS PER WORD

WORDS PE

l

InWord OutPixelR LINE LINE LENGTH

ω−

≡

=

�

p

><

▼


Example 4: Example 4: Digital FilterDigital Filter (2/2)(2/2)

{

( )( )

( )( )

( )

3

3

8 2

8 2

9

Clock , , , ,

1

1.0

0 .1

1 .0

0 .1

0 .1

delayedFor 2 on

InPixel Pad EndOfWord FirstInstant

FirstInstant

InPixel

EndOfWord InPixe

Pixel

Pixel

Pixel

Pixe

sclk

InWord

EndOfLine

Ou

l

InPixel

Pad

InPi

l

PitPixel xel x

ω

ω

ω

ω

ω

=

=

=

=

=

=

=

▼

▼

▼

▼

▼

▼

}sustain upto

FirstInstant EndOfWordReady

SReady Re

el

ady InWord

= +=

WaitForWord

Splitter

WaitForWord

# / SReady

/ InPixel(bin2u(?InWord.b1))

/ InPixel(bin2u(?InWord.b3)),

EndOfWord,Ready

/ InPixel(bin2u(?InWord.b2))

WORDS_PER_LINE

EndOfWord /

/ Pad(0)

LATENCY tick /

EndOfLine

Feeder

EndOfWord

InPixel

Pad

syncChart =

« timedBehavior » Feeder { on = sclk }

InWord /

InPixel(bin2u(?InWord.b0))

sustain {

?Pixel <= ?InPixel if InPixel,

?Pixel <= ?Pad if Pad and not InPixel

}

/ Ready

Glitch detected

timesquare : a multiform time simulation environment · december 3rd, 2008 safa 9 from constraints...

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