timing ii - faculty-web.msoe.edu€¦ · 7476 dual j-k flip-flop, asynchronous preset and clear...
TRANSCRIPT
![Page 1: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/1.jpg)
Timing II
Last updated 3/14/19
![Page 2: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/2.jpg)
2 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
• CD54HC174F
• SN54LS174J
• SN74LVC2G80DCUR
![Page 3: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/3.jpg)
3 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
HD 54 LS 10
SN 74 HCT 2G 04 N
Manufacturer Prefix
Specs/Temp Indicator
Technology Indicator
Gates Count
Device Number
Package Designation
AD; Analog Devices
AM; Advanced Micro Devices
AT; Atmel
bq; Benchmarq
CA; RCA (analog)
CD; RCA (digital)
CLC; Comlinear Corp.
CS; Crystal Semiconductor
CS; Cherry Semiconductor
CY; Cypress Semiconductor
DG; Siliconix
DS; Dallas Semiconductor
DM; National Semiconductor (digital)
EDI; Electronic Designs Inc, EDI
EL; Elantec
EP; Altera (Classic series)
EPC; Altera (EPROM)
EPF; Altera (Flex series)
EPM; Altera (MAX series)
GM; Goldstar
HA; Hitachi (analog)
HAT; Hitachi
HD; Hitachi (digital)
HEF; Philips
HI; Harris
HM; Harris Microwave
HM; Hitachi
HY; Hyundai
HYB; Siemens
IDT; Integrated Devices Technology, IDT
IRF; International Rectifier
IP; Integrated Power
IT; Micron
HI; Intersil [Harris]
LGS; Goldstar
LM; National
M; Mitsubishi
MACH; Vantis (MACH, PLD)
MAX; Maxim
MB; Fujitsu
MC; Motorola
MN; Micro Networks
MT; Micron Technology
NDS; National Semiconductor
NE; Signetics
NEC; NEC
OKI; Oki Data
MC; ON Semiconductor [Motorola]
PI; Pericom
PM; PMI "Analog Devices"
PWM; Siliconix
QL; Quick Logic
QSI; Quality Semiconductor
SA; Signetics
SD; SGS Thomson
SE; Signetics
SEC; Samsung Electronics
SG; Silcon General
SI; Siliconix
SN; Texas Instruments, TI (Standard commercial grade parts)
SNJ; Texas Instruments, TI (MIL/QML Qualified)
SPT; Signal Processing Technologies, SPT
SSD; Samsung Electronics
SU; Signetics
SY; Synergy Semiconductor
TA; Toshiba
TC; Toshiba
TD; Pro-Electronics
TL; Texas Instruments (analog, Linear)
TMS; Texas Instruments
X; Xicor
XC; Xilinx
XR; Exar Corp.
uA; Fairchild
UC; Unitrode Integrated Circuits
Z; Zilog
ZD; Zeltex
![Page 4: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/4.jpg)
4 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
HD 54 LS 10
SN 74 HCT 2G 04 N
Manufacturer Prefix
Specs/Temp Indicator
Technology Indicator
Gates Count
Device Number
Package Designation
Technology Indicator
None - When no indicator is found, this implies it's the original TTL
Bipolar
S - Schottky logic.
LS - Low-power Schottky. Same as L series but with reduced power consumption and switching speed.
CMOS
C - CMOS
AC / ACT - Advanced CMOS (T version for TTL-compatible inputs)
HC / HCT - High-speed CMOS, similar to LS (T version for TTL-compatible inputs)
AHC / AHCT - Advanced high-speed CMOS (T version for TTL-compatible inputs)
LV / LVC' - Low-Voltage CMOS
BiCMOS
BCT - BiCMOS
ABT - Advanced BiCMOS
Specs/Temp Indicator:
75 - Interface device
74 - Commercial Grade
64 - Industrial
54 - Military/Airspace Grade
0°C - 85 °C
-40°C - 100 °C
-55°C - 125 °C
![Page 5: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/5.jpg)
5 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
HD 54 LS 10
SN 74 HCT 2G 04 N
Manufacturer Prefix
Specs/Temp Indicator
Technology Indicator
Gates Count
Device Number
Package Designation
7400 quad 2-input NAND gate
7401quad 2-input NAND gate, open collector outputs
7402 quad 2-input NOR gate
7403quad 2-input NAND gate, open collector outputs
7404 hex inverter
7405 hex inverter, open collector outputs
7406hex inverter buffer/driver, 30 V open collector outputs
7407 hex buffer/driver, 30 V open collector outputs
7408 quad 2-input AND gate
7409 quad 2-input AND gate, open collector outputs
7410 triple 3-input NAND gate
7411 triple 3-input AND gate
7412triple 3-input NAND gate, open collector outputs
7468 dual 4-bit decade counters
7469 dual 4-bit binary counters
7473 dual J-K flip-flop, asynchronous clear
7474 dual D positive edge triggered flip-flop, asynchronous preset and clear
7475 4-bit bistable latch
7476 dual J-K flip-flop, asynchronous preset and clear
7477 4-bit bistable latch
74H78 dual positive pulse triggered J-K flip-flop, preset, common clock and common clear
74L78 dual positive pulse triggered J-K flip-flop, preset, common clock and common clear
74LS78 dual negative edge triggered J-K flip-flop, preset, common clock and common clear
7479 dual D flip-flop
![Page 6: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/6.jpg)
6 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
HD 54 LS 10
SN 74 HCT 2G 04 N
Manufacturer Prefix
Specs/Temp Indicator
Technology Indicator
Gates Count
Device Number
Package Designation
D - DIP
DB - SSOP
FK - LCCC
J - CDIP
N - Plastic DIP
NS - SOP
PS - SOP
T - Flat package
W - CFP
Many more …
![Page 7: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/7.jpg)
7 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• Packages
src: Harris & Harris
![Page 8: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/8.jpg)
8 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
• SN 74 LS 74 Data Sheet
TI com low power DFFSchottky
![Page 9: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/9.jpg)
9 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
• SN 74 LS 74 Data Sheet
![Page 10: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/10.jpg)
10 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• SN74S74 TI com Schottky DFF
![Page 11: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/11.jpg)
11 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• SN7474
![Page 12: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/12.jpg)
12 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• SN74LS74
![Page 13: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/13.jpg)
13 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• Fanout
• Fanout: 6-12 depending on inputs being driven
D Q
>
D Q
>
Iout max 20mA
Iin max 1.6mA
![Page 14: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/14.jpg)
14 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
• SN 74 HC 74 Data Sheet
![Page 15: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/15.jpg)
15 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• SN74HC74
![Page 16: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/16.jpg)
16 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• SN74HC74
![Page 17: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/17.jpg)
17 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• SN74HC74
![Page 18: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/18.jpg)
18 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• SN74HC74 – fanout
• Fanout = 5
![Page 19: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/19.jpg)
19 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• Connections between types
TTL -> CMOS
![Page 20: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/20.jpg)
20 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• Connections between types
CMOS -> TTL
![Page 21: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/21.jpg)
21 © tjCE 1911
Digital Circuit Timing
• Discrete Logic Families
src: Harris & Harris
![Page 22: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/22.jpg)
22 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations• Power Considerations (CMOS)• 2 major power components
• Static• Current used when not switching
• Pstatic = VCC * I static
• Dynamic• Current used when switching
• Idynamic = C * dv/dt ≈ C * VCC / T = C * VCC * F
• P = VCC * Idynamic = VCC * C * VCC * F = C * VCC2 * F
• Note – ½ time sourcing current, ½ time sinking current
• P = ½ C * VCC2 * F
![Page 23: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/23.jpg)
23 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
![Page 24: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/24.jpg)
24 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
![Page 25: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/25.jpg)
25 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
![Page 26: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/26.jpg)
26 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
![Page 27: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/27.jpg)
27 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
![Page 28: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/28.jpg)
28 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
![Page 29: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/29.jpg)
29 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations
![Page 30: Timing II - faculty-web.msoe.edu€¦ · 7476 dual J-K flip-flop, asynchronous preset and clear 7477 4-bit bistable latch 74H78 dual positive pulse triggered J-K flip-flop, preset,](https://reader030.vdocument.in/reader030/viewer/2022040717/5e221aa060fd1618c755ec2d/html5/thumbnails/30.jpg)
30 © tjCE 1911
Digital Circuit Timing
• Discrete Implementations