tlk2201 serdes evm kit setup and usage,evm user's guide

July 2000 Mixed Signal DSP Solutions

User’s Guide

SLLU011

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgment, including thosepertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 2000, Texas Instruments Incorporated

How to Use This Manual

iii Read This First

Preface

Read This First

About This Manual

The Texas Instruments TLK2201 Serdes evaluation module (EVM) board isused to evaluate the TLK2201 device(VQFP) and associated optical interface(GBIC Module) for point-to-point data transmission applications.

The board enables the designer to connect 50-Ω parallel buses to bothtransmitter and receiver connectors. Using high speed PLL technology, theTLK2201 serializes and transmits data along one differential pair. The receiverpart of the device deserializes and presents data on the parallel bus. The high-speed (up to 1.6 Gbps) data lines interface to four 50-Ω controlled-impedanceSMA connectors. The designer can either use this copper interface or, withsmall solder modifications, send the high-speed data to a GBIC-compatiblelaser module for an optical interface (not provided).

How to Use This Manual

This document contains the following chapters:

Chapter 1 – Introduction

Chapter 2 –Typical Test and Setup Configurations

Appendix A – Schematics, Board Layouts, and GBIC Configuration

Running Title—Attribute Reference

v Contents

Contents

1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 TLK2201 EVM Kit Contents 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 TLK2201 EVM Board Configuration 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Test and Setup Configurations 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Typical Test and Setup Configurations 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 PCB Construction and Characteristics 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Schematics, Board Layouts, and GBIC Configurations A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures

2–1 TLK2201 External Serial Loopback Test Configuration 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 TLK2201EVM Serial PRBS Self-Test Configuration 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 TLK2201EVM Serial PRBS BERT Test Configuration 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 TLK2201EVM Layer Construction 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 TLK2201EVM Transceiver Schematic A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2 Optical Transceiver Configuration A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3 Top Layer 1 A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4 GND Layers 2 and 5 A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–5 Power Plane Layer 3 A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–6 GBIC and JTAG Layer 4 A-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–7 Bottom Layer 6 A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

1–1 Default Transceiver-Board Configuration as Shipped 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Configuration Changes Necessary for DC Coupling of the High-Speed Signals 1-4. . . . . . . . A–1 TLK2201EVM Transceiver Bill of Materials A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1Introduction

Introduction

The Texas Instruments (TI) TLK2201 Serdes evaluation module (EVM) boardis used to evaluate the TLK2201 device (VQFP) and associated optical inter-face (gigabit interface connector (GBIC) optics module) for point-to-point datatransmission applications.

The board enables the designer to connect 50-Ω parallel buses to both thetransmitter and receiver parallel connectors. Using high speed PLL technolo-gy, the TLK2201 serializes data and transmits this data along a differential pair.The receiver part of the device deserializes and presents the data on the paral-lel bus. For proper use of this device, users must provide dc-balanced en-coded data on the parallel bus (that is, 8b/10b). The high-speed (up to 1.6Gbps) data lines interface to four 50-Ω controlled-impedance SMA connec-tors. The designer can either use this copper interface directly or use steeringresistors to direct the high-speed side to the 75-Ω GBIC-compatible optical in-terface.

The board can be used to evaluate device parameters while acting as a guidefor high-speed board layout. The evaluation board can be used as daughter-boards that are plugged into new or existing designs. Since the TLK2201 oper-ates over a wide range of frequencies, the designer will need to optimize thedesign for the frequency of interest. Additionally, the designer may wish to useburied transmission lines and provide additional noise attenuation and EMIsuppression to optimize the end product.

Topic Page

1.1 TLK2201 EVM Kit Contents 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 TLK2201 EVM Board Configuration 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 1

TLK2201 EVM Kit Contents

1-2

As the frequency of operation increases, the board designer must take specialcare to ensure that the highest signal integrity is maintained. To achieve this,the board’s impedance is controlled to 50 Ω (75 Ω for the GBIC interface) forboth the high-speed differential serial and parallel data connections. In addi-tion, board impedance mismatches are reduced by designing the componentpad size to be as close as possible to the width of the connecting transmissionlines. Vias are minimized and, when necessary, placed as close as possibleto the device drivers. Since the board contains both serial and parallel trans-mission lines, care was taken to control both impedance and trace-length mis-match (board skew).

Overall, the board layout is designed and optimized to support high-speed op-eration. Thus, understanding impedance control and transmission-line effectsis crucial when designing high-speed boards.

Some of the advanced features offered by this board include:

PCB (printed-circuit board) is designed for high-speed signal integrity.

Flexibility–the PCB can be configured for copper or optical interfaces.

SMA and parallel fixtures are easily connected to test equipment.

All input/output signals are accessible for rapid prototyping.

Analog and digital power planes can be supplied through separate bananajacks for isolation, or can be combined using ferrite bridging networks.

Series termination resistors provide parallel RD outputs.

Onboard capacitors provide ac coupling of high-speed signals.

1.1 TLK2201 EVM Kit Contents

TLK2201 EVM board (TLK2201 Rev 1.0)

TLK2201 EVM kit documentation (this document)

1.2 TLK2201 EVM Board Configuration

The TLK2201 EVM board gives the developer various options for operation,many of which are jumper-selectable. Other options can be either solderedinto the EVM or connected through input connectors.

The TX and RX parallel connectors, P3 and P5 of Figures A–8 and A–10 inAppendix A, provide a connection for both transmitted and received parallel-data busing. The reference clock is supplied through SMA connector J11, andjumper J10 must be installed between pins 1 and 2. A direct clock connectioncan also be made to J10 between the center and ground pins. The high-speedserial data is transmitted through SMA connectors J1 and J2. The receivedrecovered clock (RBC0 and RBC1) is output through header P5. Receiveddata connects through SMA connectors J3 and J4 on the RX side of the board.Header J9 provides static signals (normally pulled high) to configure thedevice for different modes of operation. Header J7 is for the opticaltransceiver’s configuration and error checking. Refer to your specificGBIC-module documentation for proper configuration of this header.

TLK2201 EVM Board Configuration

1-3Introduction

The power planes are split three ways to provide power to different parts of theboard. This prevents coupling of switching noise between the analog anddigital sections of the TLK2201, and provides voltage isolation for the lasersection. The laser section of the board requires 5 V (GBIC-dependent) and isenergized through the VCC connector. The VDD and VDDA connectors require2.5 V and are joined together by removable jumpers TP1 and TP3 that areinstalled in the default configuration. Thus, only the VDD connection isnecessary to energize the TLK2201 device in the default configuration. In allsections of the board, the ground planes are common and each ground planeis tied together at every component ground connection. See Appendix A,Schematics, Board Layouts, and BGIC Configurations, for detailed schematicand layout.

The board is normally delivered in a default configuration that requires externalclock and data inputs. The TLK2201 is shipped with jumpers for default opera-tion. Table 1–1 shows the default configuration for sending data.

Table 1–1.Default Transceiver-Board Configuration as Shipped

Designator Function Condition

J10 REF CLK SEL Jumper installed – provides a method of supplying a input clock to theboard

J9 RBCMODE Jumper not installed (logic 1) – for a 1/10 baud-rate clock on RBC0 (anon-DDR mode)

J9 ENABLE Jumper not installed (logic 1) – this pulls up the enable pin for normaloperation

J9 SYNC_EN Jumper installed (logic 0) – disables the TLK2201 comma-detectioncircuitry

J9 LOOPEN Jumper installed (logic 0) – disables the TLK2201 internal loopback mode

J9 TEST_EN Jumper installed (logic 0) – disables the TLK2201 test mode

J9 PRBSEN Jumper installed (logic 0) – disables the TLK2201 PRBS internalproduction test mode

J9 MODESEL Jumper installed (logic 0) – puts the parallel buses in a 10-bit mode(disables the DDR mode)

TP1, TP3 VDD– bridge –VDDA Joins the VDD and VDDA power planes

C14, C15 TX ac-couplingcapacitors

These capacitors (normally installed) are provided to ac-couple thetransmitted signal.

C22, C23 RX ac-couplingcapacitors

These capacitors (normally installed) are provided to ac-couple thereceived signal.

C18, C19 TX ac-coupling toGBIC

These capacitors (normally not installed) are provided to ac-couple theTLK2201 transmitted data to the 75-Ω GBIC interface.

C20, 21 RX ac-coupling toGBIC

These capacitors (normally not installed) are provided to ac-couple the75-Ω GBIC receiver data to the TLK2201.

TLK2201 EVM Board Configuration

1-4

Table 1–2.Configuration Changes Necessary for DC Coupling of the High-Speed Signals

Designator Function Condition or Changes Necessary for DC Coupling

C14, C15 TX AC coupling capacitors Install zero-ohm resistors

C16, C17 RX AC coupling capacitors Install zero-ohm resistors

2-1Test and Setup Configurations

Test and Setup Configurations

This chapter presents the typical test and setup configurations used toevaluate and test the transceiver. The printed-circuit board construction andcharacteristics are included in the second section of this chapter.

Topic Page

2.1 Typical Test and Setup Configurations 2-2. . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 PCB Construction and Characteristics 2-5. . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2

Typical Test and Setup Configurations

2-2

2.1 Typical Test and Setup Configurations

The following configurations are used to evaluate and test the TLK2201 trans-ceiver. The first configuration is an external serial loopback of the high-speedsignals shown in Figure 2–1. The serial loopback allows the designer to evalu-ate most of the functions of the transmitter and receiver sections of theTLK2201 device. To test a system, a parallel-bit error-rate tester (BERT) gen-erates a predefined dc-balanced parallel-bit pattern. The pattern is connectedto the transmitter through parallel connectors TD0–TD9 (TD0–TD4 for DDRmode). The TLK2201 device serializes and presents the data on the high-speed serial pair. The serial TX data is then looped back to the receiver sideand the device deserializes and presents the data on the receive sideRD0–RD9 (RD0–RD4 for DDR mode). The data is received by the BERT andcompared against the transmitted pattern and monitored for valid data and er-rors. If any bit errors are received, a bit-error rate is evaluated at the parallel-re-ceive BERT.

Figure 2–1. TLK2201 External Serial Loopback Test Configuration

MODESEL

TX Data Out 0-910 bits

Parallel BERT

CLK IN

RX Data In 0-910 bits

Receiver BERT

REF_CLK

TD 0-9

RD 0-9

RBC_CLK

TX+

RX–

RX+

TX–

EXT INPUT

HP8133APulse Generator

Channel 1O/P

GND

PRBS_EN

TEST_EN

LOOP_EN

SYNC_EN

ENABLE

RBCMODE

GND

J9

TLK2201EVMEvaluation Board

Jumper Selection

Transmitter BERT

CLK OUT



If a parallel BERT is not available, the designer can take advantage of thebuilt-in-test mode of the device, see Figure 2–2. If the designer asserts thePRBSEN pin high, a pseudo random bit pattern will be transmitted. This pinalso puts the receiver in a mode to detect a valid PRBS pattern. A valid patternis indicated by the SYNC_PASS pin indicating high. This test only validates thehigh-speed serial portion of the device and system interconnects. The PRBSpattern is compatible with most serial BERT test equipment. This functionallows the operator to isolate and test the transmitter and receiverindependently. A typical configuration is shown in Figure 2–3. The dashedlines represent optional connections that can be made for monitoring eyepatterns and measuring jitter.

Figure 2–2. TLK2201EVM Serial PRBS Self-Test Configuration

Channel 1

TDS820 DigitalOscilloscope

MODESEL

REF_CLK

PRBS2^7-1

TX–

RX–

RX+

TX+

GND

PRBS_EN

TEST_EN

LOOP_EN

SYNC_EN

ENABLE

RBCMODE

GND

J9


RD 0-9(4)

SYNC_PASS

PRBS 2^7-1

CH1

HP83480 orTek 11801

TriggerCH2

DigitalOscilloscopeEXT

INPUT


Channel 1O/P

TRIGGEROUT

Jumper Selection


2-4

Figure 2–3. TLK2201EVM Serial PRBS BERT Test Configuration

Channel 1

TDS820 DigitalOscilloscope

REF_CLK

PRBS2^7-1

TX–

RX–

RX+

TX+


RD 0-9(4)

SYNC_PASS

PRBS 2^7-1

CH1

HP83480 orTek 11801

TriggerCH2

DigitalOscilloscopeEXT

INPUT


Channel 1O/P

TRIGGEROUT

Data In

Serial BERTHP7004A 3 Gbps

CLK OUT

Transmitter BERT

Receiver BERT

Data Out

Data Out

CLK/10

MODESEL

GND

PRBS_EN

TEST_EN

LOOP_EN

SYNC_EN

ENABLE

RBCMODE

GND

J9

Jumper Selection

PCB Construction and Characteristics


2.2 PCB Construction and Characteristics

The PCB characteristics are calculated and based on the layer constructionand trace width of the board.

Figure 2–4. TLK2201EVM Layer Construction

Layer 1 Top 50 Ω

GND114 Mil

Layer 25.5 Mil

Layer 3 VDD1

75 Ω21 Mil

Layer 49.5 Mil

Layer 5

Solder 50 Ω

GND2

6 MilLayer 6

Notes:1) All cores consist of 1 oz Cu.2) Trace width A) 25 mils (for 50- Ω layer 1) B) 11.8 mils (for 75- Ω layer 4) C) 11.8 mils (for 50- Ω layer 6)3) Overall board thickness is 62 mils ±5 mil4) Copper and solder mask adds approximately 10 mils to the overall board thickness5) Impedance is 50 Ω ±10%6) Material is G-Tek. Dielectric constant = 3.97) For overall thickness: add 1.2 to 1.4 mils for each metal layer in the stack

A-1Schematics, Board Layouts, and GBIC Configurations

Schematics, Board Layouts, and GBICConfigurations

This appendix contains the schematics, bill of materials, and board layouts forthe TLK2201EVM transceiver board.

Appendix A

A-2

Figure A–1.TLK2201EVM Transceiver Schematic

100p

C12

VD

D

0.01

C13

C224.7u

100p

C23

L3V

DD

J6V

DD

R9

1k

D1 10

0p

C27

100p

C28

R13

0

VD

D

VD

D

J8G

ND

100p

C32

100p

C29

C31

100p

C30

100p

10k

R2410k

R23

10k

R2110k

R20

10k

R25

10k

R22

10k

R17

10k

R18

10k

R19

R14

open

10k

R16

TD

1

TD

3

TD

0

TD

2

19

2 41 3

121086

11 13 15 17

14 16 18 20

5 7 9

P3

TD

8

14121086

975 13113142

J9M

OD

ES

EL

TE

ST

_EN

LOO

P_E

NS

YN

C_E

N

VD

D

R36

0

TD

7

TD

5T

D6

TD

4

TD

9

PR

BS

ENR37

open

RB

CM

OD

EE

NA

BLE

VD

DA

2

0.01

C10

0.01

C11

2 31

TP

1

Spl

it po

wer

pla

ne

L2

VD

DA

1S

plit

pow

er p

lane

C2

0.01

C1

0.01

VD

DA

1 J3

VD

DA

1

GBIC_TXN

GBIC_TXP

0.01

C14

0.01

C18

0.01

C19

J1J2 C15

0.01

C16

0.01

C3

0.01

C20 0.01 49

.9

R11

VD

DA

1

C43

100p

C40

0.01

VD

DV

DD

A1

VD

DA

1

0.01 C41

0.01C42

0.01

C39

TRST

TMS

2 31

TP

3

0.01

C34

C35

0.01

C33

0.01

0.01

C36

L4

C24

0.01

0.01

C25

10uF

C37

C38

0.01

32RBCMODE

27TDO

18VDDPLL

16P

RB

SE

N

17TEN

43R

D2

42V

DD

41R

D3

40R

D4

39R

D5

38R

D6

37V

DD

36R

D7

35R

D8

34R

D9

31RBC0

30RBC1

29VDD

28ENABLE

26LOS

25GND

24SYNCEN

23VDD

22REFCLK

21GND

20VDD

19LOOPEN

15M

OD

ES

EL

14G

ND

13T

D9

12T

D8

11T

D7

10V

DD

9T

D6

8T

D5

7T

D4

33G

ND

60 VDDA

61 TXN

62 TXP

63 VDD

1G

ND

2T

D0

3T

D1

4T

D2

5V

DD

6T

D3

64 GNDPLL

44R

D1

51 GNDA

52RXN

59 VDDA58 GNDA57 VDDA

54 RXP53 VDDA

45R

D0

46G

ND

48T

DI

47S

YN

C/P

AS

S

49 TCLK

55 TMS

56 TRSTN

50 VDD

U1

TLK

2201

0.01

C45

VD

D

TD

4

TD

3

TD

2

TD

0

TD

1

R2

open

C4

0.01

C5

0.01

J5V

CC

VD

DA

1V

DD

A1

J4

VD

DA

1

0.01

C17

C21

0.01

R1

open

TP

2

100p

C6

GBIC_RXN

GBIC_RXP

C9

100p

C8

0.01

C7

0.01

VC

CL1

Spl

it po

wer

pla

ne

4.7k

R6

R3

4.7k

4.7k

R44.7k

R5

4.7k

R74.7k

R8

VC

C

TR

ST

TX

_FA

ULT

RX

_LO

SM

OD

_DE

F(0

)

MO

D_D

EF

(2)

MO

D_D

EF

(1)

KE

Y

TX

_DIS

AB

LE

GB

IC_R

XP

TR

ST

GB

IC_R

XN

GB

IC C

ON

NE

CT

OR

VCC

171812 14 16

151311

2 4 6 8751 3

109

1920

P1

1 9 113 5 7

122 1064 8 16

2317 19 2113 15

14 24222018 26

3129272528 30 32

P5

RD

0S

YN

C/P

AS

S

RD

3R

D2

RD

1

RD

4A

RS

V

RD

2

RD

0

RD

3

RD

1

SY

NC

/PA

SS

GB

IC_T

XN

GB

IC_T

XP

R10

open

49.9

R12

0.01

C26

0.01

C44

VD

DT

DO

TM

S

TC

LK_R

ET

2 41 3 5

6

7 9

8 10

1112

J7

TM

S

TD

OR

SV

P2

TD

I

R15

35.7

CLK

RS

V

R28

35.7

R27

35.7

VD

D35

.7R

29

35.7

R26

0.01

C46

R35

35.7

VD

D0.01C51

35.7

R38

35.7

R45

R33

35.7

R34

35.7

C48

0.01

R32

35.7

R30

35.7

VD

D

R31

35.7

RD

8

RD

9

RD

4A

RD

5

RB

C0

RD

6

RD

7

RD

8

RD

6R

D7

RD

9

RB

C1

RB

C0

LOS

RD

5

LOS

RB

C1

VD

D0.

01C

47

TD

7

TD

8

TD

5

TD

6

TD

9

4.7k

R44

4.7k

R43

4.7k

R40

4.7k

R51

4.7k

R39

4.7k

R414.7k

R42

VD

DC49

0.01

0.01

C50

VD

D

VD

DA

2

R4635.7TDO

C520.01

VD

D

0R

50

R47

open

VD

D

J112

31

J10

49.9

R48

0R

49


Figure A–2.Optical Transceiver Configuration

50-Ω high-speeddata lines to SMA

50-Ω high-speeddata lines to SMA

75-Ω GBIC high-speeddata lines

Install or redirect steeringcapacitors for GBIC usage

Note: Simultaneous GBIC and SMA operation is notpossible. Steering capacitors can either be directed to theGBIC or the SMA connectors but not to both simultaneously.

A-4

Table A–1.TLK2201EVM Transceiver Bill of Materials

1 1 Digi-Key S2011–12–ND J7 2X12 Header 0.1x0.1 Centers

2 1 Digi-Key S2011–14–ND J9 2X14 Header 0.1x0.1 Centers

3 1 Digi-Key S2011–20–ND P3 2X20 Header 0.1x0.1 Centers

4 1 Digi-Key S1111–32–ND P5 2X32 Jumper 0.1x0.1 Centers

5 3 Newark 39N867 J5,J6,J8 Banana jack

6 39 Digi-Key PCC1784CT–ND C1–C5, C7, C8,C10, C11, C13,C14–C21,C24–C26,C33–C36,C38–C42,C44–C52

Capacitor, SMT603 10 V, 10%, 0.01 µF

7 1 Digi-Key PCC1842CT–ND C22 Capacitor, SMT0805 10 V, 20%, 4.7 µF

8 1 Digi-Key PCC1894CT–ND C37 Capacitor, SMT1210 10 V, 10%, 10 µF

9 4 Digi-Key 240–1018–1ND L1–L4 Ferrite bead 805 500 mA 600 Ω at 100 MHz

10 1 Digi-Key S1111–02–ND TP2 1x2 Header Header, 1x2, 0.1 cen-ter

11 1 AMP 787653 P1 GBIC Connector N/A

12 4 Digi-Key P0.0JCT–ND R13, R36, R49,R50

Resistor, SMT, 0402 0.0 Ω

13 13 Digi-Key P4.75KLCT–ND R3–R8,R39–R44, R51

Resistor, SMT, 0402 4.7 kΩ

14 10 Digi-Key P10.0KLCT–ND R16–R25 Resistor, SMT, 0402 10.0 kΩ

15 3 Digi-Key P49.9LCT–ND R11, R12, R48 Resistor, SMT, 0402, 1%1/16W 50 V

49.9 Ω

16 6 N/A N/A R1, R2, R10,R37, R14, R47

Resistor, SMT, 04021% 1/16W 50 V

Open

17 14 Digi-Key P35.7LCT–ND R15, R26–R35,R38, R45, R46

Resistor, SMT, 04021% 1/16W 50 V

35.7 Ω

18 5 Newark 142–0711–821 J11, J1–J4 SMA end launch

19 4 Newark 92N4922 STANDOFF Standoff 0.5’ 4–40 thread

20 4 Newark 30F082 Machine screw 4–40 x 3/8’

21 1 TI TLK2201 U1 TI TLK2201 DUT 64 pin VQFP

22 1 Digi-Key P1kLCT–ND R9 Resistor, SMT, 04021% 1/16W 50 V

1 kΩ

23 1 3M 3M2514–6002UB P2 IDC14M 2x14 header 0.1x0.1 centers

24 1 Digi-Key L62711CT–ND D1 SMT LED red

25 11 Digi-Key PCC101ACVCT–ND C6, C9, C12,C23, C27–C32,C43

Capacitor, SMT 0603 50 V, 5%, 100 pF


Figure A–3.Top Layer 1

C1

C2

J1

TXP

J2

TXN

J3

RXP

J7

R6

R8

R5

R7

R4

R3

4.7k

R130

C19C20

C15C14

C18

C16

C17

C21

R38

R35

35.7

R46

35.7

R45

J10

C11L2

C10

C13

L3

C22

4.7u

100p

C23

C12

100p

D1

R9

1k

C37

10uF

TP1

VDD

P3

R14open

1

2

1112

919

1020

P1

C3

C4

L1

C7

C9

100p

C5

100p

C6

C8

VCC

J4

RXN

P2

P5

R26

R27

R28

R29

R30

R31

R32

R33

R34

R15

TP2

R37

open0

R36

C25

L4C24

TP3

GND

C52

REFCLK

J11

J9

TEXAS

INSTRUMENTS

PIN 1

Notes:

*All Capacitors are .01uf unless otherwise marked

*All Resistor are 49.9 ohm unless otherwise marked

GND GND

TD

9

TD

8

TD

7

TD

6

TD

5

TD

4

TD

3

TD

2

TD

0

TD

1

VDDGND

GND

TD

0

TD

1

TD

2

TD

7

TD

6

TD

5

TD

4

TD

3

TD

9

TD

8

GND

LOS

GN

D

RB

C0

RB

C1

GN

D

RD

9

RD

8

RD

7

RD

6

RD

5

RD

4

RD

3

RD

2

RD

1

RD

0

SY

NC

P13

P14

P5

P6

JTAG

GND

TX

_FA

ULT

TX

_DIS

AB

LE

MO

D_D

EF

(2)

MO

D_D

EF

(1)

MO

D_D

EF

(0)

RX

_LO

S

GND

RBCMODE

GND

GND

VDDGND

PRBSEN

TEST_EN

LOOP_EN

SYNC_EN

ENABLE

MODESEL

PIN 1

1.25Gbps Transceiver Evaluation Board (EVM)TLK2201 Serial Gigabit CMOS 04–OCT–1999 Rev 1.0

A-6

Figure A–4.GND Layers 2 and 5


Figure A–5.Power Plane Layer 3

A-8

Figure A–6.GBIC and JTAG Layer 4

C1

C2

J1

TXP

J2

TXN

J3

RXP

J7

R6

R8

R5

R7

R4

R3

4.7k

R130

C19C20

C15C14

C18

C16

C17

C21

R38

R35

35.7

R46

35.7

R45

J10

C11L2

C10

C13

L3

C22

4.7u

100p

C23

C12

100p

D1

R9

1k

C37

10uF

TP1

VDD

P3

R14open

1

2

1112

919

1020

P1

C3

C4

L1

C7

C9

100p

C5

100p

C6

C8

VCC

J4

RXN

P2

P5

R26

R27

R28

R29

R30

R31

R32

R33

R34

R15

TP2

R37

open0

R36

C25

L4C24

TP3

GND

C52

REFCLK

J11

J9

PIN 1

Notes:

*All Capacitors are .01uf unless otherwise marked

*All Resistor are 49.9 ohm unless otherwise marked

GND GNDT

D9

TD

8

TD

7

TD

6

TD

5

TD

4

TD

3

TD

2

TD

0

TD

1

VDDGND

GND

TD

0

TD

1

TD

2

TD

7

TD

6

TD

5

TD

4

TD

3

TD

9

TD

8

GND

LOS

GN

D

RB

C0

RB

C1

GN

D

RD

9

RD

8

RD

7

RD

6

RD

5

RD

4

RD

3

RD

2

RD

1

RD

0

SY

NC

P13

P14

P5

P6

JTAG

GNDT

X_F

AU

LT

TX

_DIS

AB

LE

MO

D_D

EF

(2)

MO

D_D

EF

(1)

MO

D_D

EF

(0)

RX

_LO

S

GND

RBCMODE

GND

GND

VDDGND

PRBSEN

TEST_EN

LOOP_EN

SYNC_EN

ENABLE

MODESEL

PIN 1

1.25Gbps Transceiver Evaluation Board (EVM)TLK2201 Serial Gigabit CMOS 04–OCT–1999 Rev 1.0


Figure A–7.Bottom Layer 6

R22

R23

R24

10k

R25

openR2

openR1

R12

C26

C44

C32

100p

R11

C42C43

C40

C39

R10[open]

C41

C38

C36

C30

100p

[0] R50

[0] R49

[open] R47

C31100p

C51

C50

C49

R48

C46

C48

C47C45

R20

R19

R18

R17

R16

R21

C28

100p

C34

C27

100p

C33

C29

100p

C35

R39

4.7k

R51

R40

R41

R42

R43

R44

tlk2201 serdes evm kit setup and usage,evm user's guide

Documents