tm5500/tm5800 system design guide
TRANSCRIPT
TM5500/TM5800 System Design Guide
July 17, 2002
Property of:
Transmeta Corporation 3940 Freedom CircleSanta Clara, CA 95054USA(408) 919-3000http://www.transmeta.com
The information contained in this document is provided solely for use in connection with Transmeta products, and Transmeta reserves all rights in and to such information and the products discussed herein. This document should not be construed as transferring or granting a license to any intellectual property rights, whether express, implied, arising through estoppel or otherwise. Except as may be agreed in writing by Transmeta, all Transmeta products are provided “as is” and without a warranty of any kind, and Transmeta hereby disclaims all warranties, express or implied, relating to Transmeta’s products, including, but not limited to, the implied warranties of merchantability, fitness for a particular purpose and non-infringement of third party intellectual property. Transmeta products may contain design defects or errors which may cause the products to deviate from published specifications, and Transmeta documents may contain inaccurate information. Transmeta makes no representations or warranties with respect to the accuracy or completeness of the information contained in this document, and Transmeta reserves the right to change product descriptions and product specifications at any time, without notice.
Transmeta products have not been designed, tested, or manufactured for use in any application where failure, malfunction, or inaccuracy carries a risk of death, bodily injury, or damage to tangible property, including, but not limited to, use in factory control systems, medical devices or facilities, nuclear facilities, aircraft, watercraft or automobile navigation or communication, emergency systems, or other applications with a similar degree of potential hazard.
Transmeta reserves the right to discontinue any product or product document at any time without notice, or to change any feature or function of any Transmeta product or product document at any time without notice.
Trademarks: Transmeta, the Transmeta logo, Crusoe, the Crusoe logo, Code Morphing, LongRun, and combinations thereof are trademarks of Transmeta Corporation in the USA and other countries. Other product names and brands used in this document are for identification purposes only, and are the property of their respective owners.
Copyright © 2001-2002 Transmeta Corporation. All rights reserved.
July 17, 2002
2
TM5500/TM5800 System Design Guide
Crusoe™ Processor Model TM5500/TM5800System Design GuideRevision 1.3
Revision History:
1.0 July 2, 2001 - first release
1.1 December 6, 2001 - updated schematics, reorganized and added new information, misc corrections
1.2 June 17, 2002 - changed DDR interface spec to one bank only, removed “Preliminary” mark
1.3 July 17, 2002 - updated MAX1718 core power supply example, removed ISL6211 and FAN5250 examples
July 17, 2002
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Table of Contents
List of Tables .......................................................................................................................................... 5
List of Figures ......................................................................................................................................... 7
Chapter 1 Introduction and Naming Conventions ................................................................................................ 91.1 Overview ..................................................................................................................................... 91.2 Reference Documents .............................................................................................................. 101.3 Naming Conventions................................................................................................................. 10
1.3.1 Power Management Mode Terms .............................................................................. 111.3.2 Power Network Names ............................................................................................... 121.3.3 Signal Names ............................................................................................................. 12
Chapter 2 Example System Block Diagram and Schematics ............................................................................ 132.1 System Block Diagram.............................................................................................................. 132.2 Processor Schematics .............................................................................................................. 15
Chapter 3 Processor Power Supplies and Power Management ........................................................................ 213.1 Power Supplies ......................................................................................................................... 21
3.1.1 Core Power Supply Requirements ............................................................................ 223.1.2 VRM Core Power Supply Example............................................................................. 253.1.3 PLL Power Supply ..................................................................................................... 303.1.4 I/O Power Supplies ..................................................................................................... 333.1.5 Decoupling Capacitors................................................................................................ 34
3.2 Power Supply Sequencing ....................................................................................................... 353.2.1 Power Sequencing Requirements .............................................................................. 353.2.2 Power Sequencing Circuit Examples.......................................................................... 36
3.3 Power Supply Voltage Supervisor............................................................................................. 383.4 POWERGOOD Block Diagram Example .................................................................................. 403.5 State Transition Timing Requirements ...................................................................................... 42
Chapter 4 DDR Memory Design ............................................................................................................................ 514.1 DDR Memory Interface ............................................................................................................. 514.2 Clock Enable Isolation............................................................................................................... 524.3 Signal Termination .................................................................................................................... 524.4 DDR Reference Voltage............................................................................................................ 53
4.4.1 DDR Reference Voltage Noise Filter Circuit ............................................................... 534.5 DDR Memory Interface Design Guidelines ............................................................................... 544.6 PCB Placement and Routing Example ..................................................................................... 554.7 DDR SDRAM Schematics......................................................................................................... 59
Chapter 5 SDR Memory Design ............................................................................................................................ 655.1 SDR Memory Interface.............................................................................................................. 65
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Table of Contents
5.2 SDR Memory Interface Design Guidelines................................................................................665.2.1 Bank Selection ............................................................................................................665.2.2 Clock Enable Isolation During Power-down States.....................................................675.2.3 Signal Termination ......................................................................................................675.2.4 Miscellaneous Notes ...................................................................................................67
5.3 SDR SDRAM Layout Notes.......................................................................................................675.3.1 SDR SDRAM Memory Interface Timing......................................................................675.3.2 Example Design Strategy............................................................................................685.3.3 Write Timing ...............................................................................................................695.3.4 Read Timing................................................................................................................705.3.5 Uncertainty in the Feedback Calculation.....................................................................715.3.6 Using Soldered-down Memory....................................................................................715.3.7 Recommended Design Procedure ..............................................................................765.3.8 Design Example ..........................................................................................................77
5.4 SDR SDRAM Schematics .........................................................................................................77
Chapter 6 System Design Considerations ...........................................................................................................836.1 Clocking ....................................................................................................................................836.2 System Reset ............................................................................................................................866.3 Signal Pull-ups and Pull-downs .................................................................................................876.4 Mode-bit ROM ..........................................................................................................................896.5 Code Morphing Software ROM .................................................................................................91
6.5.1 Serial Flash ROM Interface.........................................................................................916.5.2 Serial Flash ROM Write Protection Circuit ..................................................................936.5.3 Combined BIOS/CMS Parallel ROM Interface............................................................96
6.6 Southbridge ...............................................................................................................................986.6.1 Qualified Southbridge Devices....................................................................................986.6.2 Using CLKRUN ...........................................................................................................986.6.3 Southbridge Schematics .............................................................................................98
6.7 Thermal Design .......................................................................................................................1036.8 Thermal Diode and Thermal Sensor ......................................................................................103
6.8.1 Thermal Sensor Circuit .............................................................................................1036.8.2 Thermal Sensor Issues .............................................................................................1046.8.3 Thermal Sensor Layout .............................................................................................1046.8.4 Thermal Sensor Example Schematic........................................................................105
6.9 TDM Debug Interface Connection ...........................................................................................107
Chapter 7 PCB Layout Guidelines ......................................................................................................................1117.1 PCB Design Layout .................................................................................................................1117.2 Example PCB Fabrication Notes .............................................................................................1127.3 Board Design Guidelines.........................................................................................................113
7.3.1 Printed Circuit Board Stackup ..................................................................................1137.3.2 Allegro Standard Spacing Constraints .....................................................................1137.3.3 Allegro Extended Spacing Constraints .....................................................................1147.3.4 Allegro Extended Physical (Lines/Vias) Constraints ................................................1157.3.5 Allegro Extended Electrical (Lines/Vias) Constraints ...............................................115
7.4 Footprint and Pin Escape Diagram .........................................................................................116
Appendix A System Design Checklists .................................................................................................................117
Appendix B Serial Write-protection PLD Data .......................................................................................................123
Index .....................................................................................................................................................129
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List of Tables
Table 1: Supported ACPI Processor States ......................................................................11Table 2: Supported ACPI System States...........................................................................11Table 3: Power Net Naming Conventions..........................................................................12Table 4: Signal Naming Conventions ................................................................................12Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors ..................22Table 6: Default Power-on Start Voltage VRDA (VID) Output Codes................................23Table 7: VID/VRDA Values and Output Voltages for MAX1718 VRM ...............................24Table 8: MAX1718 Core Power Supply Output Control Selector ......................................25Table 9: MAX1718 DSX Voltage Configuration .................................................................26Table 10: Power Supply Sequencing Timing Specifications................................................35Table 11: DDR SDRAM Memory Configurations.................................................................51Table 12: SDR SDRAM Memory Configurations .................................................................65Table 13: SDR SDRAM Interface Device Specifications .....................................................68Table 14: Write Timing Compensation ................................................................................69Table 15: Signal Pull-up/Pull-down Requirements ..............................................................87Table 16: PLD Pinout...........................................................................................................94Table 17: Recommended Eight Layer PCB Stackup.........................................................113Table 18: Standard Spacing/Line/Via Constraints ............................................................113Table 19: Extended Global Spacing/Line/Via Constraints ................................................114Table 20: Extended Physical Constraints .........................................................................115Table 21: Extended Electrical Constraints ........................................................................115
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List of Tables
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List of Figures
Figure 1: Example Schematic Naming System...................................................................11Figure 2: Example System Block Diagram .........................................................................13Figure 3: PLL / Processor Core Voltage Tracking Requirement .........................................30Figure 4: Power Supply Sequencing...................................................................................35Figure 5: Recommended DDR Reference Voltage Circuit with Ferrite Bead Noise Filter ..53Figure 6: Recommended 4-Device DDR Memory Chip Placement ....................................55Figure 7: Recommended 4-Device DDR Memory Signal Routing - Top Layer...................56Figure 8: Recommended 4-Device DDR Memory Signal Routing - Internal Layer .............57Figure 9: Recommended 4-Device DDR Memory Signal Routing - Bottom Layer..............58Figure 10: Physical SDRAM Configurations .........................................................................68Figure 11: Read Timing Compensation ................................................................................70Figure 12: Adjustment of CLKIN Delay .................................................................................71Figure 13: Optimum Placement and Routing........................................................................72Figure 14: Sub-optimal Placement........................................................................................72Figure 15: Data Structure Diagram .......................................................................................73Figure 16: Address Line Structure Diagram..........................................................................74Figure 17: Clock Line Structure Diagram..............................................................................74Figure 18: Data Mask Structure Diagram .............................................................................75Figure 19: Clock Enable Structure Diagram .........................................................................75Figure 20: System Reset Diagram........................................................................................86Figure 21: Schematic Diagram of Serial Flash Write-protection PLD in System ..................95Figure 22: Recommended CLKRUN Circuit .........................................................................98Figure 23: Transmeta Debug Connector (TDCA) ...............................................................108Figure 24: Mechanical Footprint .........................................................................................116Figure 25: Write Protection TSSOP-24 JEDEC Fuse Map .................................................124Figure 26: Write Protection TSSOP-24 CUPL Source Code ..............................................125
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List of Figures
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C h a p t e r 1
Introduction and NamingConventions
1.1 Overview This design guide is organized into the following sections:
• Introduction and Naming Conventions (this chapter) introduces the conventions used in this document, including possible differences between hardware names for power supplies, pins, etc. and the reference schematics used throughout the document.
• Chapter 2, Example System Block Diagram and Schematics presents the Crusoe TM5500/TM5800 processor in the context of a block diagram that shows necessary components and their connections. The reference schematic for the processor itself is also provided.
• Chapter 3, Processor Power Supplies and Power Management describes the power supply network in detail.
• Chapter 4, DDR Memory Design provides design guidelines and layout requirements for incorporating DDR SDRAM memory into a design.
• Chapter 5, SDR Memory Design provides design guidelines and layout requirements for incorporating SDR SDRAM memory into a design.
• Chapter 6, System Design Considerations describes a variety of design issues, including clocking, reset, ROM interfaces, signal pull-up/pull-down requirements, thermal sensor, and southbridge interfaces.
• Chapter 7, PCB Layout Guidelines discusses physical issues related to memory and component interfaces, power supplies, signal integrity, mounting and spacing constraints, tolerances and fabrication guidelines, and footprint and pin escape diagrams.
• Appendix A, System Design Checklists includes cross-referenced checklists to follow while designing a system.
• Appendix B, Serial Write-protection PLD Data includes the JEDEC fuse map and CUPL source code for the write-protection PLD required for serial-ROM Code Morphing software placement. This issue is described in Serial Flash ROM Write Protection Circuit on page 93 in Chapter 6, System Design Considerations.
• An Index is also included.
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Introduction and Naming Conventions
1.2 Reference Documents The following documents are available from Transmeta for use in conjunction with this design guide. Some of these documents are extensively referenced in the design guide, and should be consulted as specified in the text.
• TM5500/TM5800 Data Book
• TM5500/TM5800 Package Specifications and Manufacturing Guide
• TM5500/TM5800 Thermal Design Guide
• TM5500/TM5800 Development and Manufacturing Guide
• TM5500/TM5800 BIOS Programmer’s Guide
• TM5500/TM5800 IBIS Models
• TM5500/TM5800 BSDL file
• TM5500/TM5800 Code Morphing Software Release Notes
• TM5500/TM5800 Technical Bulletins and Errata documents
1.3 Naming Conventions Power supply and signal names used in the Data Book and other hardware-specific materials can be different from those used on the reference schematics. This section shows the terms used in the System Design Guide and the reference schematics, and correlates them with the hardware-specific names used elsewhere.
In general, the hardware symbols in the schematics show the hardware names for each item (signal or power line). The alphanumeric marker at the connection between symbol and line is the ball number, described in detail in the Data Book. The line itself shows the schematic net name, i.e. the name that is used throughout this document to refer to that net/signal/line.
NoteThe block diagram and reference schematics included in this book offer general guidelines for integrating TM5500/TM5800 processors into product designs. For detailed processor-specific information, consult the reference documents listed below.
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Introduction and Naming Conventions
The following diagram shows how to locate the various schematic names:
1.3.1 Power Management Mode Terms The power management modes supported by TM5500/TM5800 processors are discussed in detail in Chapter 1, Functional Interface Description, in the Data Book. The following tables show the ACPI power and sleep states supported by TM5500/TM5800 processors and referenced in this document.
Figure 1: Example Schematic Naming System
Table 1: Supported ACPI Processor States
ACPI State ACPI State Name DescriptionC0 Normal Active power state with processor executing instructions.C1 Auto Halt Sleep state entered by processor executing HALT instruction.C2 Quick Start Sleep state requiring chipset/hardware support. This state is lower
power than C1.C3 Deep Sleep Sleep state requiring chipset/hardware support. This state is lower
power than C2.
Table 2: Supported ACPI System States
ACPI State ACPI State Name DescriptionS0 Working Normal active state (not sleeping).S1 Power-on Suspend Processor not executing instructions. Processor state and RAM
context maintained.S3 Suspend-to-RAM
(STR)Current processor state is suspended and stored in volatile RAM (that is kept powered). Only _STR and _ALWAYS power supplies are active.
pin name
ball number
schematic name
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Introduction and Naming Conventions
Note that some terms must be combined for a full description of system state (e.g. Working/Auto Halt vs. Working/Quick Start). For more details on ACPI states, see the ACPI specification.
For information on timing requirements between states, see State Transition Timing Requirements on page 42. Power specifications for each of the supported power management modes are provided in Chapter 3, Electrical Specifications in the Data Book.
1.3.2 Power Network Names Transmeta’s reference schematics use a standard naming convention for power supply nets, provided in the table below.
1.3.3 Signal Names Transmeta’s reference schematics call out many signals which may be named slightly differently in hardware-oriented documents such as the Data Book. The following table illustrates the character conventions used in the schematics:
S4 Suspend-to-Disk (STD)
Current processor state is suspended and saved to non-volatile disk. All power supplies except _ALWAYS are off.
S5 Soft Off System is turned off. All power supplies except _ALWAYS are off.
Table 3: Power Net Naming Conventions
Convention DescriptionV_name A switched voltage such as V_CPU_CORE, off during S3, S4, and S5Vn_d_STR A voltage present in S3 (STR), off during S4 and S5Vn_d A switched voltage at n.d volts, off during S3, S4, and S5 V_Nn_d A negative voltage at n.d volts, off during S3, S4, and S5 Vn_d_ALWAYS An always-on voltage, i.e. present in all ACPI sleep states
Table 4: Signal Naming Conventions
Character Description Example# Denotes asserted low signals. Signal names without this suffix are
assumed to assert high.LOWSIG#
.., : Used to separate elements in a list. EIGHTBITBUS[7..0]D[7:0]
/ Can be used to separate multiple uses of a pin. USEA/USEB[ ] Delineates bus name from element list. EIGHTBITBUS[7..0]
Table 2: Supported ACPI System States (Continued)
ACPI State ACPI State Name Description
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C h a p t e r 2
Example System Block Diagramand Schematics
2.1 System Block DiagramThe block diagram below shows major elements of a TM5500/TM5800 processor-based system design. Signals and bus interconnections are also shown. For detailed circuit design information, see the reference schematics throughout this document (also available in OrCAD format from your Transmeta representative).
Figure 2: Example System Block Diagram
To Rest Of Motherboard
Crusoe ProcessorV2_5, V3_3,
V_CPU_CORE, V_CPU_PLL
CPU CorePower Supply
V_CPU_CORE
MemoryPower Supply
V2_5_STR, V3_3_STR
Transmeta Debug Connector A(30-pin)
TemperatureSensor
V3_3
8Mbit SerialFlash forCMS
2kbit SerialMode-BitROM
Serie
s Te
rmin
atio
n
SUSPEND#
DDR_CKE[1:0]
Serie
s Te
rmin
atio
n
SUSPEND#
SDR_CKE[3:0]
SUSP
END
#
EPR
OM
A[2:
1] (o
ptio
nal)
PCI_
C/B
E#[3
:0]
PCI_
CLK
RU
N#,
PC
I_D
EVSE
L#, P
CI_
FRAM
E#PC
I_IR
DY#
, PC
I_LO
CK#
, PC
I_PA
R
CPU
_RST
#
CLK
_PC
I_TM
PCI_
PER
R#,
PC
I_ST
OP#
, PC
I_TR
DY#
PCI_
REQ
#[5:
0]
PCI_
SER
R#
SUSC#
SUSB#
PWRGOOD
PCI_
FER
R#
CPU
_IG
NN
E#, I
NIT
#, IN
TR, N
MI,
SMI#
CPU
_CLK
, CPU
_STP
CLK
#, S
USP
END
#
PCI_
RST
#
CPU_RST#
SYS_RST#connect to system-level reset
Temp Alertto
southbridge
all S
yste
m P
OW
ERG
OO
D s
igna
ls(w
ire O
Red
)POWERGOOD
VRDA[4:0]
DDR Interface Signals
SDR Interface Signals
PCI_
AD[3
1:0]
PCI_
GN
T#[5
:0]
PCI_
HLD
A#PC
I_H
LD#
TDM_TCK,TDO,TDI,TMS,TRST#
SRCLK, SRDATA
SROM_SCLK,SROM_SOUT,SROM_SIN,SROM_CS[1:0]
TDM_SCLTDM_SDA(Serial Debug Bus interface)
DDR SDRAM
V2_5_STR
SDR SDRAM
V3_3_STR
SDR_DQ[63:0], SDR_A[12:0],SDR_DQMB[7:0],SDR_CS#[3:0],
SDR_BA[1:0], SDR_CAS#,SDR_RAS#,SDR_WE#, SDR_CLK[3:0]
DDR_DQ[63:0], DDR_A[12:0],DDR_DQS[7:0],DDR_BA[1:0], DDR_CS#[3:0],
DDR_DQM[7:0]DDR_CLKA/A#, DDR_CLKB/B#,DDR_RAS#,DDR_CAS#, DDR_WE#
DIODE_CATHODEDIODE_ANODE
Transmeta Corp.Confidential
NDA Required06/04/2001
DEBUG_INIT NM_DEBUG_INIT
High-Speed Bi-Directional Level-Translator Isolation
V5_0_ALWAYS
V3_3
V3_3
SDR SDRAMDelay Loop
(SDR_CLKIN,SDR_CLKOUT)
V5_0_ALWAYS
High-Speed Bi-Directional Level-Translator Isolation
1
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Example System Block Diagram and Schematics
TM5500/TM5800 processors include both core processor and northbridge functionality. For a motherboard designer, this means the processor looks very much like a northbridge. TM5500/TM5800 processors support two DRAM interfaces, one for Double Data Rate (DDR) SDRAMs and the other for Single Data Rate (SDR) SDRAMs. Designers can choose to use either or both SDRAM interfaces, depending on their system cost and performance requirements.
In the block diagram, note that power signals that feed each component are listed in the component’s block. This helps to identify suspend and switched power distribution to each component. Descriptions of each supply are described in Chapter 3, Processor Power Supplies and Power Management.
The major elements shown in the block diagram are outlined below:
• Processor Core Power Supply. The processor core high-efficiency switched-mode power supply. See Chapter 3, Processor Power Supplies and Power Management.
• Memory Power Supplies. The power supplies for SDR and DDR SDRAM memory. See Chapter 3, Processor Power Supplies and Power Management.
• DDR SDRAM Interface. The processor can support up to two identical banks of DDR SDRAMs in various configurations of 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit devices. See Chapter 4, DDR Memory Design.
• SDR SDRAM Interface. The processor can support up to four banks of SDR SDRAMs in various configurations of 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit devices. See Chapter 5, SDR Memory Design.
• SDRAM High-speed Bidirectional Level-translator Isolation. Signal isolation is used to ensure that CKE signals to the SDRAMs remain stable during processor power transitions. Since the processor does not have a suspend power well, output signals are undefined during power transitions and subject to glitching.
• PCI Interface and PCC Signals. The PCI interface is 33 MHz, 3.3 V. The arbiter supports five REQ/GNT pairs. CLKRUN is supported (see Using CLKRUN on page 98). PCC (PC compatibility) signals are used for communication with the southbridge. See Southbridge on page 98.
• Code Morphing Software Serial Flash ROM. Code Morphing software is stored in this optional (but recommended) 1 Mbyte device. See Serial Flash ROM Interface on page 91. Other options for Code Morphing software code storage (such as sharing the BIOS ROM) are also described. See Combined BIOS/CMS Parallel ROM Interface on page 96.
• Serial Flash Write-protection Circuit. If a serial flash ROM is used for Code Morphing software, a PLD (programmable logic device) write-protection device must be added to the serial flash ROM circuit. See Serial Flash ROM Write Protection Circuit on page 93.
• Mode-bit ROM (required). System-dependent configuration options vital to proper processor operation are stored in this required 2 Kbit device and read by the processor at boot time. See Mode-bit ROM on page 89.
• Thermal Sensor. An external thermal sensor is used in conjunction with a thermal sensing diode built into the processor. See Thermal Diode and Thermal Sensor on page 103.
• Transmeta Debug Module (TDM) Interface. This adds some low-level debug support to facilitate in-design bring-up, as well as connectivity to the Transmeta Virtual In-Circuit Emulator CE (TMVICE) for software development. See TDM Debug Interface Connection on page 107.
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Example System Block Diagram andSchematics
2.2 Processor Schematics The following pages show TM5500/TM5800 processor reference schematics.
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilThursday, November 29, 2001 1 5
TM5800 DDR Interface3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
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Title:
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Project:
DDR_A6
DDR_DQ32
DDR_DQM6
DDR_DQ59DDR_DQM2
DDR_DQ26
DDR_DQ60
DDR_DQ50
DDR_DQ28
DDR_DQ41
DDR_DQS1
DDR_DQ16
DDR_A5
DDR_DQ7
DDR_DQM5
DDR_DQS7
DDR_DQ48
DDR_DQ36
DDR_DQ13
DDR_DQS2
DDR_DQ42
DDR_DQ51
DDR_DQ6
DDR_A2
DDR_DQ10
DDR_A4
DDR_DQ52
DDR_DQ14
DDR_A1
DDR_DQ23
DDR_DQ0
DDR_DQ56
DDR_DQS6
DDR_DQ44DDR_DQ43 DDR_A10
DDR_DQ15
DDR_A8
DDR_DQ57
DDR_DQ1
DDR_DQ24
DDR_DQ29DDR_DQ30
DDR_A9
DDR_DQ35
DDR_DQ8
DDR_DQ27
DDR_A11
DDR_DQ47
DDR_DQM4
DDR_A0
DDR_DQ46
DDR_DQ33
DDR_DQ11
DDR_DQM7
DDR_DQ34
DDR_DQS3
DDR_DQ54
DDR_DQM3
DDR_DQ5DDR_DQ4
DDR_DQ9
DDR_DQM0DDR_DQ55
DDR_DQ45
DDR_DQ25
DDR_DQ12DDR_DQS4
DDR_DQ58
DDR_DQ38
DDR_A3
C_VREF
DDR_DQS0
DDR_DQ21
DDR_A12
DDR_DQ31
DDR_DQ61
DDR_DQ39
DDR_DQ19DDR_DQ18
DDR_DQ20
DDR_DQ53
DDR_DQ17
DDR_A7
DDR_DQ3
DDR_DQ63
DDR_DQ37
DDR_DQ2
DDR_DQM1
DDR_DQ62
DDR_DQ49
DDR_DQ22
DDR_DQS5
DDR_DQ40
DDR_DQ4_R
DDR_DQ41_R
DDR_DQ11_R
DDR_DQ48_R
DDR_DQ42_R
DDR_DQ10_R
DDR_DQ52_R
DDR_DQ28_R
DDR_DQ16_R
DDR_DQ61_R
DDR_DQ17_R
DDR_DQ9_R
DDR_DQ37_R
DDR_DQ27_R
DDR_DQ20_R
DDR_DQ53_RDDR_DQ54_R
DDR_DQ56_R
DDR_DQ26_R
DDR_DQ32_R
DDR_DQ6_RDDR_DQ5_R
DDR_DQ34_R
DDR_DQ36_R
DDR_DQ24_R
DDR_DQ58_R
DDR_DQ43_R
DDR_DQ57_R
DDR_DQ12_R
DDR_DQ40_RDDR_DQ39_R
DDR_DQ1_R
DDR_DQ25_R
DDR_DQ63_R
DDR_DQ55_R
DDR_DQ13_R
DDR_DQ49_R
DDR_DQ33_R
DDR_DQ18_R
DDR_DQ44_R
DDR_DQ30_R
DDR_DQ62_R
DDR_DQ7_R
DDR_DQ29_R
DDR_DQ21_R
DDR_DQ46_R
DDR_DQ50_R
DDR_DQ59_R
DDR_DQ15_R
DDR_DQ23_RDDR_DQ22_R
DDR_DQ31_R
DDR_DQ3_R
DDR_DQ14_R
DDR_DQ45_R
DDR_DQ35_R
DDR_DQ8_R
DDR_DQ19_R
DDR_DQ47_R
DDR_DQ38_R
DDR_DQ51_R
DDR_DQ0_R
DDR_DQ2_R
DDR_DQ60_R
CLK_DDRA_R
DDR_A11_R
DDR_A9_R
DDR_BA0_R
DDR_DQM3_R
DDR_CS0_R#
DDR_A10_R
DDR_DQS5_R
DDR_A0_R
DDR_A8_R
DDR_A5_R
DDR_A2_R
DDR_MWE_R#
DDR_DQS1_R
DDR_DQM5_R
DDR_A7_R
DDR_CS3_R#
DDR_A12_R
DDR_RAS_R#
DDR_A3_R
DDR_DQS0_R
DDR_DQS6_R
DDR_DQM7_R
DDR_BA1_R
DDR_DQM6_R
DDR_CAS_R#
DDR_DQS3_R
DDR_CKE_MUX1_R
DDR_A6_R
DDR_DQS7_R
DDR_CS2_R#
DDR_A1_R
DDR_DQM0_RDDR_DQM1_R
DDR_DQM4_R
DDR_DQM2_R
DDR_DQS4_R
DDR_A4_R
DDR_CS1_R#
DDR_DQS2_R
DDR_CKE_MUX0_R
CLK_DDRB_RCLK_DDRB_R#
CLK_DDRA_R#
DDR_RAS#
CLK_DDRB#
CLK_DDRADDR_DQ[63..0]
DDR_BA0DDR_BA1
DDR_CAS#
DDR_DQS[7..0]
DDR_A[12..0]
DDR_CS2#
DDR_CKE_MUX0
CLK_DDRA#
DDR_CS1#DDR_CS0#
DDR_MWE#
DDR_CKE_MUX1
CLK_DDRB
DDR_DQM[7..0]
DDR_CS3#
V2_5
RN12A 241 8
RN17B 242 7
RN1A 101 8
RN7C 243 6
RN22C 243 6
RN9B 242 7
RN14A 101 8
RN20C 243 6
RN3C 243 6
RN7B 242 7
RN22B 242 7
RN10B 242 7
RN18A 101 8
R9 101 2
RN6C 243 6
RN1B 102 7
RN17C 243 6
RN16D 104 5
RN20D 244 5
RN11D 104 5
RN14B 102 7
RN7D 244 5
RN20A 241 8
RN3A 241 8
RN6B 242 7
RN1D 244 5
RN13D 244 5
RN19C 243 6
RN25D 244 5
R8 101 2
RN2A 101 8
RN17D 244 5
RN11B 102 7
RN14C 103 6
RN16C 103 6
RN22A 241 8
RN9A 241 8
R3 101 2
RN5A 241 8
(PART 1 OF 5)
DDR
U1ACrusoe BGA474
AD14AE15AD15AE16
AC19
AB18AB19
AA18AA19
AA17
Y19Y18W19W18V19V18U19U18
AB11
P18N19N18M19
L19L18K16M15M16M17N15N16
P16T16T17U15U16
V16V17W15W16Y15Y16Y17
AA15
AA16
AB14AA13AB13AC13AA12
AE13AD13AE14
AD19
AB16
AA11
AD18
AC18
P19
AB12
AD12
M18
P15
V15
K19
AE12
AE11AD11
Y7AE6
AB10AA9
AC11AA10
Y11Y9Y8AD10
AD16AE18T19R18P17T15AC16AA14
AD8AE8AD7AE7AD6AC7AB7AA7AB8AA8AE9AC9AB9
AE17AD17T18R19R15R16AB15AC15
AE10AD9
C_DQ4C_DQ5C_DQ6C_DQ7
C_DQ10
C_DQ13C_DQ12
C_DQ15C_DQ14
C_DQ53
C_DQ16C_DQ17C_DQ18C_DQ19C_DQ20C_DQ21C_DQ22C_DQ23
C_DQ63
C_DQ25C_DQ26C_DQ27C_DQ28
C_DQ30C_DQ31C_DQ32C_DQ33C_DQ34C_DQ35C_DQ36C_DQ37
C_DQ39C_DQ40C_DQ41C_DQ42C_DQ43
C_DQ45C_DQ46C_DQ47C_DQ48C_DQ49C_DQ50C_DQ51C_DQ52
C_DQ54
C_DQ56C_DQ57C_DQ58C_DQ59C_DQ60
C_DQ1C_DQ2C_DQ3
C_DQ8
C_DQ55
C_DQ62
C_DQ9
C_DQ11
C_DQ24
C_DQ61
C_DQ0
C_DQ29
C_DQ38
C_DQ44
C_VREF
C_WE#
C_RAS#C_CAS#
C_CKE1C_CKE0
C_CLKB#C_CLKB
C_CLKA#C_CLKA
C_CS3#C_CS2#C_CS1#C_CS0#
C_DQS0C_DQS1C_DQS2C_DQS3C_DQS4C_DQS5C_DQS6C_DQS7
C_A0C_A1C_A2C_A3C_A4C_A5C_A6C_A7C_A8C_A9
C_A10C_A11C_A12
C_DQMB0C_DQMB1C_DQMB2C_DQMB3C_DQMB4C_DQMB5C_DQMB6C_DQMB7
C_BA0C_BA1
RN2B 242 7
RN21A 241 8
RN8A 241 8
RN11C 103 6RN12B 242 7
RN5D 244 5
RN19B 242 7
RN24D 244 5
RN2C 103 6
RN14D 104 5
RN11A 101 8
RN15C 243 6 RN16B 102 7
RN20B 242 7
RN6D 244 5
R4 101 2
RN2D 244 5
RN4A 241 8
RN1C 243 6
RN12C 243 6
RN4D 244 5
C10.1uF
12
RN15D 244 5
R10 101 2
R22.80K1%
12
RN25B 242 7
RN15A 241 8
RN23C 243 6
R5 101 2
RN16A 101 8
RN5C 243 6
RN9D 244 5
RN25A 241 8
RN13C 243 6
RN12D 244 5
RN5B 242 7
RN19A 241 8
RN24B 242 7
R12.15K1%
12
RN17A 241 8
RN4C 243 6
R6 101 2
RN21B 242 7
RN8B 242 7
RN23D 244 5
RN25C 243 6
RN13B 242 7
RN18C 103 6
RN10C 243 6
RN4B 242 7
RN15B 242 7
R7 101 2
RN7A 241 8
RN3D 244 5
RN21C 243 6
RN8C 243 6
RN24C 243 6
RN22D 244 5
RN10D 244 5
RN18D 104 5
RN10A 241 8
RN19D 244 5
RN23A 241 8
RN6A 241 8
RN9C 243 6
RN21D 244 5
RN3B 242 7
RN8D 244 5
RN23B 242 7
RN24A 241 8
RN13A 241 8
RN18B 102 7
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
PLACE R11 CLOSE TO SOURCE, PROCESSOR BALL V6
TM5800 Design Guide
Custom
ABasilThursday, November 29, 2001 2 5
TM5800 SDR Interface3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
SDR_CLKOUT
SDR_CLKIN
SDR_DQ62_R
SDR_DQ1_R
SDR_DQ46_R
SDR_DQ20_RSDR_DQ21_R
SDR_DQ24_R
SDR_DQ63_R
SDR_DQ53_R
SDR_DQ55_R
SDR_DQ41_R
SDR_DQ31_R
SDR_DQ0_R
SDR_DQ42_R
SDR_DQ12_R
SDR_DQ5_R
SDR_DQ39_R
SDR_DQ52_R
SDR_DQ47_R
SDR_DQ61_R
SDR_DQ7_R
SDR_DQ28_R
SDR_DQ48_R
SDR_DQ36_R
SDR_DQ18_R
SDR_DQ8_R
SDR_DQ23_R
SDR_DQ57_R
SDR_DQ50_R
SDR_DQ59_RSDR_DQ60_R
SDR_DQ51_R
SDR_DQ15_R
SDR_DQ45_R
SDR_DQ26_R
SDR_DQ4_R
SDR_DQ34_R
SDR_DQ40_R
SDR_DQ17_R
SDR_DQ56_R
SDR_DQ38_R
SDR_DQ6_R
SDR_DQ10_R
SDR_DQ32_R
SDR_DQ54_R
SDR_DQ35_R
SDR_DQ37_R
SDR_DQ9_R
SDR_DQ29_R
SDR_DQ16_R
SDR_DQ14_R
SDR_DQ44_R
SDR_DQ33_R
SDR_DQ25_R
SDR_DQ43_R
SDR_DQ19_R
SDR_DQ49_R
SDR_DQ13_R
SDR_DQ30_R
SDR_DQ27_R
SDR_DQ11_R
SDR_DQ3_RSDR_DQ2_R
SDR_DQ58_R
SDR_DQ22_R
SDR_CKE_MUX1_R
SDR_BA1_R
SDR_CS2_R#
SDR_A8_R
SDR_A10_R
SDR_CS0_R#
SDR_A5_R
SDR_A1_R
SDR_BA0_R
SDR_DQM2_R
SDR_DQM5_R
SDR_A0_R
CLK_SDR1_R
SDR_MWE_R#
NC_U1_K4
SDR_CAS_R#
NC_U1_K3NC_U1_L5
SDR_A12_R
SDR_DQM6_R
SDR_DQM3_R
SDR_DQM1_R
CLK_SDR0_R
SDR_CS1_R#
CLK_SDR2_R
SDR_A3_RSDR_A2_R
SDR_A4_R
SDR_RAS_R#
SDR_A9_R
SDR_DQM0_R
SDR_A11_R
NC_U1_K5
SDR_A7_RSDR_A6_R
CLK_SDR3_R
SDR_CKE_MUX0_R
SDR_DQM4_R
SDR_DQM7_R
SDR_CS3_R#
SDR_MWE#
SDR_DQ14
SDR_DQ57
SDR_DQ37
SDR_DQ41
SDR_DQ3
SDR_DQ59
SDR_DQ34
SDR_DQ51
SDR_CAS#
SDR_DQ22
SDR_DQ58
SDR_A4SDR_DQ35
SDR_BA0
SDR_DQM0
SDR_DQ38
SDR_CS2#
SDR_DQ8
SDR_RAS#
SDR_DQ39
SDR_DQ45
SDR_DQ42
SDR_DQ33
SDR_DQ63
SDR_A5
SDR_A12
SDR_DQ20
CLK_SDR2
SDR_DQM6
SDR_DQ27
SDR_DQM1
SDR_DQ25
SDR_A7
SDR_DQ9
SDR_DQ31
SDR_DQ48
SDR_A11
SDR_DQ2
SDR_DQ62
SDR_DQ24
SDR_DQ26
SDR_DQ32
SDR_DQ0
SDR_DQ60
SDR_DQ4
SDR_DQ40
SDR_DQM5
SDR_DQ43
SDR_DQ52
SDR_DQM3
SDR_A6
SDR_DQ50
SDR_DQ47
SDR_DQ12
SDR_CS3#
SDR_DQM7
SDR_DQ15
SDR_DQ55
SDR_DQ46
SDR_DQ23
SDR_DQ53SDR_DQ54
CLK_SDR3
SDR_A1
SDR_DQ11
SDR_DQ36
SDR_DQ44
SDR_DQ30
SDR_DQ21
CLK_SDR1
SDR_DQ7
SDR_DQ17
CLK_SDR0
SDR_DQM4
SDR_DQ49
SDR_DQ61
SDR_DQ18
SDR_A0
SDR_DQ1
SDR_CS1#
SDR_DQ56
SDR_DQM2
SDR_CKE_MUX0
SDR_DQ29
SDR_A8
SDR_DQ16
SDR_DQ5
SDR_DQ19
SDR_DQ28
SDR_DQ10
SDR_A2
SDR_DQ13
SDR_CS0#
SDR_A10
SDR_DQ6
SDR_CKE_MUX1
SDR_BA1
SDR_A3
SDR_A9
RN47A 331 8
RN45B 332 7
RN36A 338 1
RN43B 332 7
RN28A 331 8
RN31D 104 5
RN32B 332 7
RN36C 333 6
RN39B 102 7
RN33B 102 7
RN48B 332 7
RN27C 333 6
RN48C 333 6
RN45D 334 5
RN35B 332 7
RN44C 103 6
RN29C 333 6
RN40C 333 6
RN31C 333 6
RN39C 333 6
RN38B 102 7
RN33D 104 5
RN48D 334 5
RN27A 331 8
RN49C 333 6
RN43C 333 6
RN34C 333 6
RN47D 334 5
RN29B 332 7
RN42B 102 7
RN43A 331 8
RN30C 333 6
RN38A 331 8RN38D 104 5
R13 221 2
RN46A 338 1
RN31B 102 7
RN28B 332 7
RN37D 104 5
RN45C 333 6
SDR
(PART 2 OF 5)
U1BCrusoe BGA474
P3N4V5P4N5M1P1N1P2N2M2K1
W5AB4AB5AA5Y5
AC4AD3AD2AC2AC1AD1AA4AA3Y4Y3W4G4G6G5E6F5D5E5D6F4F3E3E4D4B5C5C4
AA6AC5AD5AD4AE3AE5AE4AE2AB2AB1AA2AA1Y2Y1W2W1F1F2E1D1E2C1D2
B1B2B3A4A2B4A3A5C2
U1U4H4H3U5U2H2H1
T4T3T1T2
M3M4M5L4L5K3K4K5
J2J1
L2L1
V4
AB6 V6
R5
P5
K2
S_A0S_A1S_A2S_A3S_A4S_A5S_A6S_A7S_A8S_A9
S_A10S_A11
S_DQ0S_DQ1S_DQ2S_DQ3S_DQ4S_DQ5S_DQ6S_DQ7S_DQ8S_DQ9S_DQ10S_DQ11S_DQ12S_DQ13S_DQ14S_DQ15S_DQ16S_DQ17S_DQ18S_DQ19S_DQ20S_DQ21S_DQ22S_DQ23S_DQ24S_DQ25S_DQ26S_DQ27S_DQ28S_DQ29S_DQ30S_DQ31S_DQ32S_DQ33S_DQ34S_DQ35S_DQ36S_DQ37S_DQ38S_DQ39S_DQ40S_DQ41S_DQ42S_DQ43S_DQ44S_DQ45S_DQ46S_DQ47S_DQ48S_DQ49S_DQ50S_DQ51S_DQ52S_DQ53S_DQ54
S_DQ63S_DQ62S_DQ61S_DQ60S_DQ59S_DQ58S_DQ57S_DQ56S_DQ55
S_DQMB0S_DQMB1S_DQMB2S_DQMB3S_DQMB4S_DQMB5S_DQMB6S_DQMB7
S_CS0#S_CS1#S_CS2#S_CS3#
S_CLK0S_CLK1S_CLK2S_CLK3S_CLK4S_CLK5S_CLK6S_CLK7
S_CKE0S_CKE1
S_BA0S_BA1
S_CAS#
S_CLKIN S_CLKOUT
S_RAS#
S_WE#
S_A12
RN44A 101 8
RN47B 332 7
RN33C 333 6
RN42A 331 8
RN32D 334 5
RN38C 333 6
R14 221 2
RN41D 104 5
R11 331 2
RN26A 338 1
RN30D 104 5
RN49A 331 8
RN37B 102 7
RN28D 334 5
RN44D 334 5
RN35D 334 5
RN46B 332 7
RN37A 331 8
RN42C 333 6
RN32C 333 6
R15 221 2
RN41B 102 7
RN47C 333 6
RN29D 104 5RN30A 331 8
RN41A 338 1
RN36B 102 7
RN31A 338 1
RN45A 338 1
RN35C 333 6
RN37C 333 6
RN46D 334 5
RN43D 334 5
RN40B 102 7
RN26B 332 7
RN34A 338 1
RN30B 102 7
RN48A 331 8
RN29A 331 8
RN41C 333 6
RN36D 104 5
RN32A 331 8
RN39A 338 1
RN34D 104 5
RN49D 334 5
RN27B 332 7
RN26C 333 6
RN46C 333 6
RN40D 104 5
RN44B 332 7
RN35A 338 1
RN42D 334 5
RN28C 333 6
RN33A 331 8
R12 221 2
RN40A 331 8RN39D 104 5
RN34B 102 7
RN27D 334 5
RN49B 332 7
RN26D 334 5
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilThursday, November 29, 2001 3 5
TM5800 PCI Interface3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
PCI_AD4
RSVD_G1_PU
PCI_AD14 RSVD_H6_PU
PCI_AD22
PCI_AD19
PCI_AD17
PCI_AD23 NC_RSVD_J4
RSVD_V3_PU
RSVD_F7_PU
PCI_AD21
RSVD_V2_PU
PCI_AD12
PCI_AD31
PCI_AD20
NC_RSVD_R4
PCI_AD26
RSVD_W6_PU
PCI_AD15
RSVD_E7_PD
PCI_AD25
PCI_AD18
PCI_AD5
NC_SNIFF_VCORE
PCI_AD10
NC_SNIFF_GND
RSVD_V1_PU
PCI_AD28
PCI_AD6
NC_RSVD_T5NC_RSVD_J5
PCI_AD27
RSVD_G13_PD
PCI_AD2
NC_RSVD_D7
PCI_AD1
PCI_AD11
PCI_AD16NC_RSVD_R2
PCI_AD3
PCI_AD7
PCI_AD0
NC_RSVD_G11
PCI_AD13
RSVD_H5_PU
PCI_AD8
PCI_AD30
PCI_AD9
PCI_AD29
PCI_AD24
PCI_SERR#
PCI_CBE3#
PCI_GNT4#
PCI_FRAME#PCI_IRDY#
PCI_AD[31..0]
PCI_CBE2#
PCI_TRDY#
UNPROTECT
CLK_PCI_TM
PCI_GNT3#
PCI_CBE1#
PCI_PAR
PCI_GNT2#
PCI_HLDA#
PCI_GNT5#
PCI_GNT0#
PCI_CBE0#
PCI_RST#PCI_CLKRUN#
PCI_GNT1#
PCI_DEVSEL#PCI_STOP#
PCI_REQ0#
PCI_REQ5#PCI_REQ4#
PCI_REQ1#PCI_REQ2#PCI_REQ3#
PCI_HLD#
V3_3V3_3 V3_3 V3_3V3_3V3_3
R?10K
12
RN50C
10K
36
RN54C
10K
36
RN52D
10K
45
RN51B
10K
27
RN51C
10K
36
RN53A
10K
18
RN55A
10K
18
RN50D
10K
45
RN51D
10K
45
RN54B
10K
27
(PART 3 OF 5)
PCI
RESERVED
U1CCrusoe BGA474
B19C18B18B17D16E16E17C16F16E15D15F15C15E14D14B15E12F11E11D11D12C11E10D10F9E9D9B8C9B9A9
A10
A12B11A11B10
D19D18E19E18F19F18
G15A16F13A15G16F17
J18
A17
A13B12
E13C19
A14B14
F8
F12
E8
D13C13B13
G13
G2
W6H5G1
V2
D7
AE19
V1V3H6
E7
F7
G11R1
R2
T5
R4
J4J5
P_AD0P_AD1P_AD2P_AD3P_AD4P_AD5P_AD6P_AD7P_AD8P_AD9P_AD10P_AD11P_AD12P_AD13P_AD14P_AD15P_AD16P_AD17P_AD18P_AD19P_AD20P_AD21P_AD22P_AD23P_AD24P_AD25P_AD26P_AD27P_AD28P_AD29P_AD30P_AD31
P_C/BE0#P_C/BE1#P_C/BE2#P_C/BE3#
P_REQ0#P_REQ1#P_REQ2#P_REQ3#P_REQ4#P_REQ5#
P_GNT0#P_GNT1#P_GNT2#P_GNT3#P_GNT4#P_GNT5#
P_CLKRUN#
P_DEVSEL#
P_FRAME#P_IRDY#
P_HLDA#P_HOLD#
P_LOCK#P_PAR
P_PCLK
P_PERR#
P_PCI_RST#
P_SERR#P_STOP#P_TRDY#
RSVD_G13
RSVD_G2
RSVD_W6RSVD_H5RSVD_G1
RSVD_V2
RSVD_D7
RSVD_AE19
RSVD_V1RSVD_V3RSVD_H6
RSVD_E7
RSVD_F7
RSVD_G11RSVD_R1
RSVD_R2
RSVD_T5
RSVD_R4
RSVD_J4RSVD_J5
R174.7K
12
RN52A
10K
18
RN52B
10K
27
RN55D
10K
45
RN54A
10K
18
RN52C
10K
36
R16 10K1 2
RN51A
10K
18
RN50B
10K
27
RN55C
10K
36
R184.7K
12
RN54D
10K
45
RN53B
10K
27
RN50A
10K
18
RN53C
10K
36
RN55B
10K
27
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
SYSTEMS THAT DO NOT INSTALL MODE BIT ROM:INSTALL PU WHEN CMS IS IN THE SERIAL ROMINSTALL PD WHEN CMS IS IN THE PARALLEL ROM
TM5800 Design Guide
Custom
ABasilTuesday, December 04, 2001 4 5
TM5800 Sideband3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
NC_EPROMA0
VRDA0
VRDA3VRDA2VRDA1
VRDA4
NM_DEBUG_INT
PWRGOOD
SROM_CS0#
CLK_CPU
EPROMA1
SROM_SIN
CPU_INIT#
SROM_SCLK
TDM_TMS
CPU_STPCLK#DIODE_CATHODE
SRCLK
CPU_IGNNE#
TDM_SROM_CS1#
CPU_FERR#
TDM_TRST#
DEBUG_INT
CPU_SMI#
TDM_TCK
TDM_SDA
TDM_TDO
TDM_RST#
DIODE_ANODE
PCI_RST#
TDM_TDI
CPU_NMI
TDM_SCL
CPU_INTR
SRDATA
EPROMA2
SROM_SOUT
SUSPEND#
VRDA[4..0]
V3_3V3_3
R21
10K
12
R25 1.2K1 2
R30
3.3K
12
R22
10K
12
R294.7K
NI
12
R20
10K
12
R19
4.7K
NI1
2
R23
1.2K
12
R2710K
12
R31
3.3K
12
R32
3.3K
12
R2810K
12
R26 4.7K1 2 R33
3.3K
12
R24
1.2K
12
(PART 4 OF 5)
U1DCrusoe BGA474
C7G7
H19G18G19H17G14H15H18D8
A8
K17
H14W11
G9W7
A19W9
Y12Y13V14W14W13
A18B16
H16
J16J15J19
B7
K15L15L16K18
A6B6
AE1
CLKINPWRGOODRESET#INIT#INTRNMISMI#IGNNE#STPCLK#SLEEP#
CFG_SDATA
SROM_SIN
DEBUG_INTNM_DEBUG_INT
TRST#TCKTMSTDI
VRDA0VRDA1VRDA2VRDA3VRDA4
DIODE_ANODEDIODE_CATHODE
FERR#
EPROMA0EPROMA1EPROMA2
CFG_SCLK
SROM_CS0#SROM_CS1#SROM_SCLKSROM_SOUT
S_SCLKS_SDATA
TDO
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TANT TANT
TANT
POLYPOLY POLY POLY POLY
NOTE: C2 IS NOT INSTALLED, HOWEVER,IT IS STRONGLY RECOMMENDED THATDESIGNS INCLUDE FABRICATION PADS(FOOTPRINTS) FOR THESE PARTS.
TM5800 Design Guide
Custom
ABasilThursday, November 29, 2001 5 5
TM5800 PWR & GND3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
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U1_A7V2_5
V_CPU_PLLV3_3
V_CPU_CORE
C401uFCC0805
12
C451uFCC0805
12
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Processor Power Supplies and PowerManagement
C h a p t e r 3
Processor Power Supplies andPower Management
This section provides design guidelines for TM5500/TM5800 processor power supplies, power sequencing, and power management circuits. This section also describes processor power supply requirements that must be implemented.
See the Data Book for peak current and other power-related processor specifications. The current requirements of each supply should be calculated on a per-design basis.
3.1 Power Supplies The block diagram in Chapter 2, System Block Diagram, shows the power supplies for each of the major components. The power source for all notebook computers is either a battery (< 20 V) or a DC wall adapter of a comparable voltage. An intelligent switching mechanism is needed to create a stable V_DC or V_SOURCE that is used to supply the regulators that generate system voltages.
There are four power supplies required for TM5500/TM5800 processors:
• Core power supply (V_CPU_CORE)
• PLL power supply (V_CPU_PLL)
• 3.3 V I/O power supply (V3_3)
• 2.5 V I/O power supply (V2_5)
It is important to follow the design recommendations and meet the requirements provided below for TM5500/TM5800 power supply designs.
NoteFollow the power supply sequencing requirements described in Power Supply Sequencing on page 35.
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Processor Power Supplies and Power Management
3.1.1 Core Power Supply Requirements
Information on low-range VRMs (voltage regulator modules), strongly recommended for new system designs, is available from qualified VRM vendors as indicated in this document.
Care must be taken to assure the core power supply voltage, V_CPU_CORE, supplied to TM5500/TM5800 processors does not exceed the absolute maximum limit of 1.5 V when evaluating TM5500/TM5800 processor in systems designed for TM5400/TM5600 processors (designed to operate up to 1.6 V).
The table below provides the most significant core power supply requirements for TM5500/TM5800 processors
NoteSee the Data Book for TM5500/TM5800 voltage and current requirements for this and all power supplies.
NoteThe only VRM qualified by Transmeta for TM5500/TM5800 processors is the Maxim MAX1718. Refer to the manufacturers VRM data sheet for detailed design information.
WARNINGCORE POWER SUPPLY VOLTAGE (V_CPU_CORE) TO TM5500/TM5800 PROCESSORS MUST NOT EXCEED 1.5 V OR PERMANENT DEVICE DAMAGE MAY RESULT.
Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors
Specification Value NotesCore voltage range 0.95 - 1.30 V (nominal) See LongRun™ specificationsCore voltage static regulation +/- 2% maximum at all voltage
settings, across all set points, line, load and temperature
Voltage tolerance for DC load changes
Core voltage dynamic regulation +/- 5% maximum excursion; return to within 1% of static regulation band for a +/- 6 A load step
Voltage tolerance for dynamic current changes, i.e. short-term voltage excursions that quickly return to the static regulation band described above
Core voltage recovery time 20 µS maximum to return to within 1% of static regulation band for a +/- 6 A load step
Pulse width of voltage spikes
Core voltage periodic and random deviation (PARD), including ripple
+/- 1% maximum Includes other voltage changes not included above
Core voltage supply slew rate 4.0 mV/µS minimum Minimum voltage change rate required for LongRun™ power management transitions
Core supply current 10.0 A maximum For 1 GHz SKUVRM voltage control mode Remote sense operation Using processor core voltage
feedback signal (SNIFF_CVDD), processor ball number AE19
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Processor Power Supplies and PowerManagement
3.1.1.1 Default Power-on VRDA (VRM VID) Output Codes
TM5500/TM5800 processors have a default power-on VRDA code of 0x0E. This code corresponds to 1.050 V output for a Maxim MAX1718 VRM.
The table below shows the default power-on VRDA code values for TM5x00 processors.
Source voltage 10.0 V minimum Required for this particular reference design to meet specifications above
Combined ESR of bulk capacitors 5 mΩ maximumCombined capacitance of bulk capacitors
800 µF minimum (nominal)1100 µF maximum (nominal)
Distribution resistance from bulk capacitors to processor
2 mΩ maximum
Inductor inductance 1.8 µH nominal2.2 µH maximum
Inductor RMS current 14 A minimumInductor saturation current 20 A minimum
Table 6: Default Power-on Start Voltage VRDA (VID) Output Codes
Processor Model
VID/VRDA Value Default Startup VoltageVRDA [4]
VRDA [3]
VRDA [2]
VRDA [1]
VRDA [0] Hex VRM Output
TM5500/TM5800 0 1 1 1 0 0x0E 1.05 VTM5400/TM5600 0 1 0 1 0 0x0A 1.25 V
Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors (Continued)
Specification Value Notes
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Processor Power Supplies and Power Management
3.1.1.2 VID/VRDA Code Table
The VID/VRDA codes for the Maxim MAX1718 VRM are shown in the table below.
Table 7: VID/VRDA Values and Output Voltages for MAX1718 VRM
VID/VRDA ValueVRM OutputVRDA [4] VRDA [3] VRDA [2] VRDA [1] VRDA [0] Hex
0 0 0 0 0 0x00 1.75 V0 0 0 0 1 0x01 1.70 V0 0 0 1 0 0x02 1.65 V0 0 0 1 1 0x03 1.60 V0 0 1 0 0 0x04 1.55 V0 0 1 0 1 0x05 1.50 V0 0 1 1 0 0x06 1.45 V0 0 1 1 1 0x07 1.40 V0 1 0 0 0 0x08 1.35 V0 1 0 0 1 0x09 1.30 V0 1 0 1 0 0x0A 1.25 V0 1 0 1 1 0x0B 1.20 V0 1 1 0 0 0x0C 1.15 V0 1 1 0 1 0x0D 1.10 V0 1 1 1 0 0x0E 1.05 V0 1 1 1 1 0x0F 1.00 V1 0 0 0 0 0x10 0.975 V1 0 0 0 1 0x11 0.950 V1 0 0 1 0 0x12 0.925 V1 0 0 1 1 0x13 0.900 V1 0 1 0 0 0x14 0.875 V1 0 1 0 1 0x15 0.850 V1 0 1 1 0 0x16 0.825 V1 0 1 1 1 0x17 0.800 V1 1 0 0 0 0x18 0.775 V1 1 0 0 1 0x19 0.750 V1 1 0 1 0 0x1A 0.725 V1 1 0 1 1 0x1B 0.700 V1 1 1 0 0 0x1C 0.675 V1 1 1 0 1 0x1D 0.650 V1 1 1 1 0 0x1E 0.625 V1 1 1 1 1 0x1F 0.600 V
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Processor Power Supplies and PowerManagement
3.1.2 VRM Core Power Supply Example The sections below provide an example core power supply design using the Maxim MAX1718 VRM. This reference design is recommended by Transmeta for TM5500/TM5800 processor-based system designs.
3.1.2.1 Maxim MAX1718 Regulator
Maxim provides a VRM that is well-suited for TM5500/TM5800 core power supply designs. This VRM is described below. A reference design, adapted from example circuits in the Maxim MAX1718 data sheet, is provided at the end of this section. Detailed design information for the MAX1718 low-range VRM is available from Maxim in the MAX1718 data sheet, and should be referenced whenever possible.
3.1.2.2 Output Voltage Control
The MAX1718 has three different methods that can be used to program the output voltage by means of three internal resisters:
• Normal Operating Mode voltage is determined by the logic levels of the VID inputs.
• Startup Mode voltage is determined by series resistors connected to the VID inputs.
• Deep Sleep Extension (DSX) Mode voltage is determined by the logic levels on the S0 and S1 inputs.
Which of the three methods is used to control the output voltage is determined by the ZMODE and SUS input signals. These inputs control internal multiplexers that select which register is presented to the DAC to set the output voltage. When high, the SUS input overrides the ZMODE input, forcing the output voltage to the DSX value. The table below describes this selection logic.
Normal Operating Mode
Normal operating mode output voltage is programmed directly by the five VID input signals according to Table 7. There are no internal VID pull-ups to 5 V in the MAX1718 (as there were in the MAX1711), so there is no need for a quickswitch to protect the processor VRDA outputs from the VRM VID inputs. However, because there are no internal pull-ups, external pull-up resistors are required.
NoteVendor part-specific information provided in this System Design Guide may be incorrect or out of date. Please consult with the manufacturer for the latest specifications and design information for the VRM and related components used in the design.
Table 8: MAX1718 Core Power Supply Output Control Selector
Core Power SupplyOperating Mode
Output VoltageDetermined By
Control SignalZMODE SUS CPU_STP#
Normal Operating Mode 1
1. Used for LongRun power management.
Logic level of D0-D4 Low Low High
Startup Mode Impedance of D0-D4 High Low HighDSX Mode Logic level of S0 and S1 Don’t care High Low
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Processor Power Supplies and Power Management
Startup Mode
Startup mode is selected when the ZMODE signal is high. In this mode the output voltage is determined by the internal impedance mode resister whose value is set on the rising edge of the ZMODE signal. The device looks at the impedance on the VID inputs. If it is > 90 KΩ it is considered a logic high, and if it is < 1.1 KΩ it is considered a logic low. This process is initiated by the rising edge of the ZMODE signal. During this time the device tries to move its VID inputs by alternately trying to pull the VID inputs high with a pull-up resistor to 5 V, and low through a pull-down resistor to ground. This happens over the period of a few µS. To make the VID input a logic 1 (high), insert a 100 KΩ resistor in series with the VID input. To make the VID input a logic 0 (low), make the series resistor zero Ω. In addition to the series resistors, a pull-up resistor of 1 KΩ must be added to each VID input. If pull-up resistors of > 1 KΩ are used to limit supply current, then a 4.7 nF capacitor must be added across each pull-up resistor to keep the AC impedance < 1 KΩ.
Deep Sleep Extension (DSX) Mode
The MAX1718 VRM supports a Deep Sleep extension (DSX) mode that can provide a very low output voltage to the TM5500/TM5800 processor core during extended Deep Sleep periods, significantly reducing processor leakage power during long intervals of sustained system inactivity. The reference design example provided at the end of this section shows the DSX mode configured for 0.9 V operation. This can be reconfigured to a lower TM5500/TM5800 DSX voltage specification when it becomes available. See Table 9 for DSX voltage programming information.
Driving the SUS signal high overrides the ZMODE control and sets the output voltage to one of thirteen preset values between 0.600 V and 0.900 V, depending on the state of the S0 and S1 inputs. The S0 and S1 inputs are each effectively quad-state / four-level logic, and can be set by connecting them to either the VRM VCC (+5 V), REF, or GND signals, or leaving the input open. Since each input has four states and there are two inputs, there are 24 = 16 possible combinations, of which only thirteen are used here.
The table below provides DSX mode output voltage configuration information for the full range of DSX voltages.
NoteAlthough this feature is incorporated in the MAX1718 VRM, it is not yet qualified for the TM5500/TM5800 processor.
Table 9: MAX1718 DSX Voltage Configuration
DSX Voltage S0 S10.900 V VCC GND0.875 V GND REF0.850 V REF REF0.825 V OPEN REF0.800 V VCC REF0.775 V GND OPEN0.750 V REF OPEN0.725 V OPEN OPEN0.700 V VCC OPEN0.675 V GND VCC0.650 V REF VCC0.625 V OPEN VCC0.600 V VCC VCC
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Processor Power Supplies and PowerManagement
3.1.2.3 Current Limit Adjustment (ILIM)
Resistors in the example circuit are used to adjust the output current limit. The values are selected based on the maximum VRM current and the RDSon of the lower switching FET being used. See the MAX1718 data sheet for detailed information on adjusting the output current limit.
3.1.2.4 Output Voltage Offset Control (POS, NEG)
The MAX1718 has a provision to adjust the output voltage a little higher or lower than the programmed value. This is accomplished by means of a differential input amplifier that adds an offset voltage to the programmed value. Since voltage positioning is used in the reference design example, the output will droop below the set value by a negative tolerance. The output voltage offset control feature is used to shift the output voltage up to yield the required +5%, -2% output voltage tolerance.
The actual output offset voltage is the voltage applied between the POS and NEG inputs multiplied by a variable factor that depends on the output voltage, which in the reference design example is approximately 0.85. See the MAX1718 data sheet for detailed information on adjusting the output voltage offset.
3.1.2.5 Switching Frequency/On-time Selection Control (TON)
The VRM switching frequency is selected by means of the TON input. The reference design example shows the MAX1718 configured for 300 KHz operation. The MAX1718 has been tested to operate at 300 KHz only.
3.1.2.6 Output Voltage Slew-rate Adjustment (TIME)
The resistor connected to the TIME input on the device (RTIME) is used to set the slew-rate of the output voltage change when transitioning between programmed output values (see MAX1718 data sheet for details). The recommended range for RTIME is 47 KΩ for a 380 KHz slew-rate clock to 470 KΩ for a 38 KHz slew-rate clock. Slew-rate clock frequency = 150 KHz x (120K / RTIME). The slew rate given by:
The slew rate is in mV per µS and the resistor, RTIME, is in KΩ.
3.1.2.7 DH Pull-up Current/Turn-on Time Adjustment (BST)
A resistor connected to the BST input in the reference design example is used when necessary to slow down the turn-on time of the upper FET to minimize ringing.
NoteThe MAX1718 VRM has only been tested for TM5500/TM5800 designs at 300 KHz operation.
dVdT------- 450
RTIME----------------=
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Processor Power Supplies and Power Management
3.1.2.8 VRM Shutdown Control (SKP/SDN#)
When the SKP/SDN# input is low, the VRM is shut down. When this signal is pulled high to VCC, the VRM operates in skip mode. When this signal is left floating, the VRM operates in PWM mode. The reference design example operates in skip mode to take advantage of the high efficiency of skip mode at low currents.
3.1.2.9 POWERGOOD Status (VGATE)
VGATE is an open-drain output which is high (floating) when the output voltage is in regulation. This output thus indicates a POWERGOOD status, and is used during power-up in the reference design example to enable the processor I/O power supplies (V3_3_STR and V2_5_STR) to begin ramping up, as required by TM5500/TM5800 power sequencing specifications. VGATE has an internal sense circuit to force it high during programmed transitions such as normal LongRun voltage step transitions, without the need for an external deglitching circuit.
3.1.2.10 Voltage Positioning
TM5500/TM5800 processors should not be used with voltage positioning core power supplies. The MAX1718 VRM in this reference design is configured for remote sense operation.
3.1.2.11 MAX1718 Core Supply Reference Design Schematic
A MAX1718 core power supply reference design schematic, recommended for TM5500/TM5800 processors, is provided on the following page.
Note that the output from this reference design power supply is labeled V_CPU_CORE. This output is connected to the processor core supply (CVDD) balls. The SNIFF_VCORE voltage sense signal in the reference design is connected to the processor SNIFF_CVDD signal (ball number AE19).
A
A
B
B
C
C
D
D
1 1
2 2
Note: Settings shownare for: DSX = 0.900V Start Voltage = 1.05V
1) Output Capacitor Requirements o Total Capacitance: >650 uF, <1100uF o Combined ESR = 5 milliOhm max o Example: - 3, 270uF, 15 milliohm, Panasonic EEFUE0E271R2) Inductor Requirements (for 10A) o 1.8uH, Irms >10A, Isat > 15A o Example: Panasonic ETQP6F1R8BFA
Install 0 ohm resistor(or jumper) to defeatDSX function.
Connect CPU_STP# to ALI1535 Pin C10 or equivilent signal
DSX Voltage SelectionResistors or Jumpers.Setting shown is for0.900V
Note: R12 is optional to measurecurrent for test purposes only and is not required in productionboards.
Note: Special attention needs to be taken with theetch run from the processor SNIFF_VCORE pin to R26of the VRM circuit to minimize noise. The preferredmethod is to add a ground etch on both sides of theVSNIFF_VCORE signal to reduce crosstalk noise.Also R12 and R31 should be located as close the theVRM circuit as possible.
TM5800 Design Guide
Custom
CRonMonday, July 15, 2002 1 1
Maxim 1718 VRM, 10A3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
Copyright (C) 1995-2000 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
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Date: Author:
Project:
SUSB#
VRDA2
VRDA4
VRDA3
VRDA0
VRDA1
CPU_STP#
SNIFF_VCORE
FORCE_STARTUP_V
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V5_0
V_BATT
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Processor Power Supplies and Power Management
3.1.3 PLL Power Supply
For all system designs, V_CPU_PLL for TM5500/TM5800 processors must track the core voltage from the maximum V_CPU_CORE value down to 1.0 V. The lower bound for V_CPU_PLL is 1.0 V. As the core voltage drops below 1.0 V, V_CPU_PLL must remain at 1.0 V.
V_CPU_PLL should be routed on the same side of the PCB that the processor is mounted on.
3.1.3.1 PLL Supply Core Voltage Tracking Requirement
V_CPU_PLL must track the core supply voltage, V_CPU_CORE, within ± 50 mV across a nominal core operating voltage range of 1.0 V to 1.3 V, while staying within the minimum/maximum voltage limits of each supply. V_CPU_PLL must remain at 1.0 V ± 50 mV across a nominal core operating voltage range of 0.9 V to 1.0 V.
For transitions in the core voltage (e.g. during LongRun power management voltage steps), V_CPU_PLL must settle to within the ± 50 mV V_CPU_CORE voltage tracking specification within ± 25 µS.
The figure below graphically shows the TM5500/TM5800 processor PLL power supply tracking requirement.
3.1.3.2 PLL Power Supply Example
A PLL power supply design example is provided below that meets the requirements shown above, providing proper V_CPU_PLL vs. V_CPU_CORE tracking. The circuit includes an enable switch, output buffer, and a low-pass noise filter.
NoteSee the Data Book for the voltage and current requirements for this and all power supplies.
Figure 3: PLL / Processor Core Voltage Tracking Requirement
0.9 V
1.0 V
1.1 V
1.2 V
1.3 V
0.9 V 1.0 V 1.1 V 1.2 V 1.3 VProcessor Core Voltage (CVDD)
PLL
Volta
ge (P
LLVD
D) 1.4 V
1.4 V 1.5 V
1.5 V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PLL_VDD, 1V Minimum Clamping Circuit
Bead is required only ifnoise on V5_0 is creatingnoise on V_CPU_PLL
TM5500/5800 System Design Guide
Custom
B<Author>Monday, July 15, 2002 1 1
PLL_VDD, 1V Min Clamp Circuit3940 Freedom CircleSanta Clara, CA 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
SUSB#
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July 17, 2002
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Processor Power Supplies and Power Management
Example PLL Power Supply Circuit Description
R1/Q2 and R2 form a voltage divider to create a 1.0 V reference for the minimum V_CPU_PLL operating voltage. A high on START_SEQ (typically connected to the POWERGOOD output of the V_CPU_CORE regulator) turns on the PLL supply via FET Q2. U1A and Q1 are connected as a unity-gain voltage follower so that V_CPU_PLL will equal the positive input of the opamp U1A at pin 3. U1A pin 3 is then connected to V_CPU_CORE through resistor R3. The purpose of R3 is to separate the U1A input node from V_CPU_CORE. The circuit described so far is an accurate voltage follower, where V_CPU_PLL tracks V_CPU_CORE. U1B is also connected as a voltage follower for the 1.0 V reference circuit, and D6 allows U1B to take control of the loop if V_CPU_PLL goes below 1.0 V. R4 provides a load for the U1A-Q1 follower. The PLL power supply circuit should be located as close to the processor V_CPU_PLL pin as possible, and the V_CPU_PLL/GND loop length should be minimized.
Circuit Operation
During operation, the V5_0 (5.0 V) supply to the opamp and V2_5 (2.5 V) supply to Q1 must be on whenever the processor core voltage (V_CPU_CORE) is on. Normal circuit operation is as follows:
Operation above 1.0 V: U1A regulates the V_CPU_PLL output to the voltage on its positive input (pin 3). If V_CPU_CORE is higher than 1.0 V, then V_CPU_PLL follows it. This makes the negative input of U1B (pin 6) greater than the 1.0 V reference on its positive input (pin 5), driving its output (pin 7) low. When pin 7 goes low it back-biases D6, disconnecting the U1B output from the U1A positive input and allowing V_CPU_PLL to track V_CPU_CORE.
Operation below 1.0 V: When V_CPU_CORE goes below 1.0 V, V_CPU_PLL attempts to track it, causing the negative input (pin 6) of U1B to fall below the 1.0 V reference on the U1B positive input (pin 5). This in turn causes the U1B output (pin 7) to increase, which forward biases D6 and allows it to take control of the loop. U1B now regulates V_CPU_PLL to its 1.0 V reference value as long as V_CPU_CORE is below the 1.0 V reference.
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Processor Power Supplies and PowerManagement
3.1.4 I/O Power Supplies TM5500/TM5800 processors require a 3.3 V power supply (V3_3) and a 2.5 V power supply (V2_5) to power the I/O sections of the processor. If these supplies are derived from V3_3_STR and V2_5_STR, care must be taken to ensure the voltages are not glitched when these supplies are turned on. Glitching can be minimized by controlling the turn-on rise-time of the V3_3 and V2_5 supplies.
NoteSee the Data Book for the voltage and current requirements for this and all power supplies.
NotePower supply sequencing recommendations provided in Power Supply Sequencing on page 35 must be followed.
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Processor Power Supplies and Power Management
3.1.5 Decoupling Capacitors V_CPU_CORE decoupling capacitors (8 x 0.1 µF X7R 0603) should be placed directly underneath the processor on the opposite PCB side (shown below). The V_CPU_CORE plane shown in the diagram below should extend significantly beyond the processor for connection to other peripheral decoupling capacitors.
V_CPU_CORE Underside BGA Decoupling Example
BOTTOM SIDE (AS SEEN FROM TOP SIDE)
SHARED VIA TO GNDY10 & W10
SHARED VIATO V_CPU_COREV11 & U10
SHARED VIA TO GNDU9 & T10
SHARED VIATO V_CPU_CORET11, R10 & P11
SHARED VIA TO V_CPU_CORER8 & R9
SHARED VIA TO GNDP8 & N7
SHARED VIATO GNDP10 & N9
SHARED VIA TO GNDM10 & L9
SHARED VIA TO V_CPU_COREM9 & L8
SHARED VIA TO GNDK8 & L7
SHARED VIATO V_CPU_COREM11 & L10
SHARED VIA TOV_CPU_COREK11 & L2
SHARED VIA TOV_CPU_COREH11 & J10
V_CPU_CORE PLANE
EXTEND TO POWER SUPPLY
EXTE
ND
TO C
APS
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Processor Power Supplies and PowerManagement
3.2 Power Supply Sequencing
3.2.1 Power Sequencing Requirements In order to prevent a high startup current condition on the processor I/O power supplies, it is required that the processor core power supply (V_CPU_CORE) be turned on first and reach a level of V_CPU_COREMIN or greater, prior to applying the processor 2.5 V and 3.3 V I/O voltages (V2_5 and V3_3, respectively). After V_CPU_CORE has reached V_CPU_COREMIN or greater, V3_3 and V2_5 can be supplied to the processor in any order.
A diagram of the power supply sequencing required for TM5500/TM5800 processors is shown in the figure below. System designs for TM5500/TM5800 processors must also meet the power-on requirements specified in the Data Book.
The table below provides timing specifications for the power supply sequencing figure above.
NoteSee the Data Book for more information on power sequencing requirements for TM5500/TM5800 processors.
Figure 4: Power Supply Sequencing
Table 10: Power Supply Sequencing Timing Specifications
Timing Value Description Min MaxT1 Time from V_CPU_CORE valid to beginning ramp of V3_3 and V2_5 0 mS 50 mST2 Time from V_CPU_PLL valid to PCI_RST# deassertion 20 mS -T3 Time from V_CPU_CORE valid to PCI_RST# deassertion 20 mS -T4 Time from V3_3 and V2_5 valid to PCI_RST# deassertion 1 mS -
V_CPU_PLL
V_CPU_CORE
V3_3 and V2_5
V_CPU_PLL valid
V_CPU_CORE valid
V3_3 and V2_5 valid
PCI_RST#
PCI_RST# deasserted
T2
T3
T1
T4
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Processor Power Supplies and Power Management
Under the above startup conditions the processor VDRA signals (that go to the VRM VID inputs) are not valid until the processor I/O voltages are present. Therefore, another method must be provided to supply valid VID signals to the VRM from the time the V_CPU_CORE core supply is enabled to the time the processor I/O voltages are within specifications. Once the processor I/O voltages are valid, the processor-suppled VDRA signals are valid and can be used to control the V_CPU_CORE core supply voltage.
When using TM5500/TM5800 processors with existing TM5400/TM5600 system designs, the existing power supply sequencing should not be used unless it meets the TM5500/TM5800 sequencing requirements described above, due to the likelihood for current surges on the I/O power supplies if the I/O voltages are applied to the processor prior to the V_CPU_CORE core supply reaching V_CPU_COREMIN.
With the previously recommended TM5400/TM5600 power supply circuit, a high current on the I/O power supply circuits has been observed for about 3-10 ms, and its magnitude can be up to the current limit of the particular 3.3 V or 2.5 V regulator used (testing has shown up to 3.5 A). The excess current is not due to I/O contention, but rather current flow through the power supply pins of the processor.
This could possibly have the following negative effects for the system:
• DDR SDRAM data corruption when exiting STR (suspend-to-RAM).• The 2.5 V or 3.3 V regulator may go into under-voltage shutdown or over-current protection, in which
case system operation may only be recoverable if power-cycled. • The 2.5 V or 3.3 V supply voltage may dip enough to cause memory corruption and power supply latch-
off. • The current spike may trigger other system-level protection circuits or result in I/O contention.
3.2.2 Power Sequencing Circuit Examples As explained above in Power Sequencing Requirements on page 35, TM5500/TM5800 processors must have the core voltage (V_CPU_CORE) turned on prior to the I/O voltages (V3_3 and V2_5). However, the processor VRDA output code presented to the VRM VID inputs is not valid until the I/O voltages reach regulation. The processor core VRM must rely on another method for setting the VRM output voltage during processor power-up.
The fundamental requirement is to force the processor core VRM to a fixed startup supply voltage by a means other than the VID inputs, and then use the VRDA outputs from the processor to control the core VRM output only when these VRDA signals are valid.
The processor core VRM designs shown in this document each have the ability to force the startup supply voltage (FORCE_STARTUP_V) without having a valid VID input code available from the processor. Two methods for using this capability are provided in the power supply sequencing reference design schematics below. Only one method is necessary for any system design, at the option of the designer. These two methods are described below:
Method 1 (Delay): This method uses a delay to drive the FORCE_STARTUP_V signal long enough for the I/O voltages to reach regulation. The advantage of this solution is lower cost and fewer components than Method 2.
Method 2 (Monitor): This method measures the I/O voltages to insure they are in regulation before releasing the FORCE_STARTUP_V signal. The advantage of this method over Method 1 is that it relies on actual voltage levels for control and is not susceptible to potential delay timing variability issues.
Power Supply Sequencing Reference Design Schematic
Two possible power supply sequencing circuits, as described above, are shown in the reference design schematic on the following page.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1
3
SOT-143
Voltage Sequence Option 2- VI/O Monitoring
2
4
Voltage Trip PointV2_5 2.25VV3_3 3.10V
Voltage Sequence Option 1 - Delayed
See note below
NOTE:Use either Voltage Sequence, Option 1 or Option 2, to generatethe "FORCE_STARTUP_V" signal.Do not use both.
(From Core VRM)
(To voltage supervisor)
See note below
TM55/5800 switched powerwith miller effect risetime control.
Note: Make sure that delay (C2+R1+R3)is long enough to ensure that V3_3 andV2_5 are in regulation beforeFORCE_STARTUP_V goes low.
TM5500/5800 System Design Guide
Custom
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MANUAL_RST#
V5_0-STR V3_3_ALWAYS
V3_3_ALWAYS
V3_3_ALWAYS
V2_5
V3_3_ALWAYS V3_3_STR
V3_3
V2_5_STR
V2_5
V3_3_STR
V3_3
V3_3_ALWAYS
R110k
R410K
1 2
NC7S14SOT23-5_12345
U12 4
53
U3
7SZ04SOT23-5_12345
2 4
53
1
C10.1uF
U2
MAX836EUS-Tsot143_1234
4
1
2
3
In Good
GND
Vcc
IN
U4
MAX836EUS-Tsot143_1234
4
1
2
3
In Good
GND
Vcc
IN
NC7S14SOT23-5
U12 4
53
R510K
12
Q2
SI4465
D1
1N4148
Q12N7002
C30.1uF
12
C20.1uF
R7174k
12
R310k
R210k
R9316k
12
C5.01u
12
C5.01u
12
R8200k
12
C40.1uF
12
R10200k
12
Q2
SI4465
R410K
1 2
SUSB#
FORCE_STARTUP_V
ENABLE_VIO
ENABLE_VIO
FORCE_STARTUP_V
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Processor Power Supplies and Power Management
3.3 Power Supply Voltage Supervisor The following page shows a power supply voltage supervisor reference design schematic.
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TRIP POINT FOR2_5V RAIL IS 2.19V
TM5800 Design Guide
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VOL_SPR_2_5
MANUAL_RST#
PWRGOOD
V3_3
V5_0V3_3
V3_3
V2_5
R410K
12
C30.1uF
12
C20.1uF
12
U1MAX6355SOT23-6
1
2
3
4
6
5
RST#
GND
MR#
VCC3
VCC5
RSTIN
R19.09k1%
12
C10.1uF
12
R310.0K
NI
12
R211.5k1%
12
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Processor Power Supplies and Power Management
3.4 POWERGOOD Block Diagram Example The following page shows an example block diagram for possible system POWERGOOD circuits.
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 CPU
SOUTHBRIDGE
VOLTAGESUPERVISOR
THIS IS THE RST# OUTPUT OF THESUPERVISOR AND IS THE PWRGOOD NETUSED IN THE REFERENCE SCHEMATICS
PWRGOOD
PWRGOOD
RST#
CORE VOLTAGEREGULATOR
MR#
VOLTAGESEQUENCING
THIS IS THE CPU COREVOLTAGE REGULATOR
THIS CIRCUIT ENSURES THAT THECORE VOLTAGE IS AT LEVEL PRIORTO ENABLING THE I/O VOLTAGES TOTHE CPU
PWRGOOD
THE PWRGOOD OUTPUT OF THE CORE VOLTAGEREGULATOR IS USED TO ENABLE THE I/OVOLTAGES TO THE CPU *AND* CONTROL THEVOLTAGE SUPERVISOR
I/O VOLTAGES
PWRGOODMANUAL_RST#
I/O VOLTAGEREGULATORSORFET SWITCHESTO ENABLEI/O VOLTAGES
(V2_5, V3_3, V5_0)
THIS CAN BE SYSTEM IMPLEMENTATION SPECIFIC, HOWEVER,CUSTOMERS ARE ENCOURAGED TO USE A SINGLE SYSTEM LEVELPOWERGOOD TO THE TM5800 CPU AND SOUTHBRIDGE
NOTE:
ENABLE_VIO
MANUAL_RST#
WHEN ENABLE_VIO/MANUAL_RST# IS HIGH,THE CORE VOLTAGE IS AT LEVEL.
ENABLE_VIO IS THEN USED WITH THEVOLTAGE SEQUENCING CIRCUITRY TO ENABLETHE I/O VOLTAGES TO THE PROCESSOR.
MANUAL_RST# IS THEN USED TO CONTROLTHE VOLTAGE SUPERVISOR.
SUSB#
Section 3.2
Section 3.1 Section 3.3
THIS SUPERVISOR MONITORS THE I/OVOLTAGES TO THE PROCESSOR
TM5800 Design Guide
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Processor Power Supplies and Power Management
3.5 State Transition Timing Requirements This section describes the state transition timing requirements for TM5500/TM5800 processors. Note that the various signal names used in this document are typically written from the perspective of the processor. For example, STPCLK# and SLEEP# refer to the processor input signals for Stop Clock and Sleep.
ACPI Active State (C0)
The details of the TM5500/TM5800 processor power-on sequence are described in the Data Book and associated references. Only the timing diagram and critical latencies for the power-on sequence are provided here.
Parameter Description Min Max Diagram Notetvdd_rise Supply delay and rise time 1
1. Refer to Figure 4 and Table 10 for details on power supply sequencing timing.
- 250 mS T1
tvdd_pg POWERGOOD asserted after supplies reach 95% of final value
0 S - T2
tvdd_prst Supplies stable prior to PCI_RST# deasserted
1 mS - T3
tpclk_prst PCI_CLK stable prior to PCI_RST# deasserted
100 µS - T4
tclk_prst CLKIN stable prior to PCI_RST# deasserted
1 mS - T5
tprst_rst PCI_RST# deasserted to RESET# deasserted
0 S - T6
tpg_rst POWERGOOD asserted to RESET#, PCI_RST# deasserted
1 mS - T7
tpg_low POWERGOOD inactive pulse width 10 CLKINs - not shown
- Clocks off to POWERGOOD deassertion 0 nS - T9- POWERGOOD deassertion to
PCI_RST# and RESET# assertion0 nS - T10
- POWERGOOD to all voltages off 0 nS - T11
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Processor Power Supplies and PowerManagement
Refer to the above table for a description of the notes in the diagrams below. Refer to Figure 4 and Table 10 for details on power supply sequencing timing.
Power On (C0)PCI_RST#
RESET#
POWERGOOD
CPU_CLK
PCI_CLK
V_CPU_CORE,V_CPU_PLL,V3_3,V2_5
T1
T2T3
T5
T4
T7
Power Off (C0)PCI_RST#
RESET#
POWERGOOD
CLKIN
PCI_CLK
V_CPU_CORE,V_CPU_PLL,V3_3,V2_5 T9
T10
T11
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Processor Power Supplies and Power Management
ACPI Quick Start State (C2)
The C0 to C2 transition is caused by the assertion of the STPCLK# signal. The processor issues a Stop Grant cycle in response to the STPCLK# assertion, then enters the C2 state. The C2 to C0 transition is caused by the deassertion of the STPCLK# signal.
Refer to the above table for a description of the notes in the diagram below:
ACPI Deep Sleep State (C3)
The C0 to C3 transition is caused by an I/O cycle to the power management controller, followed by the assertion of the STPCLK# signal, followed by the assertion of the SLEEP# signal, and then the shutdown of the host clock. The C3 to C0 transition is accomplished by the opposite sequence of signals (restart processor clock, deassert SLEEP#, deassert STPCLK#).
The I/O cycle that initiates the C3 power state is typically snooped by the processor. The processor integrated northbridge must be properly configured to snoop this I/O cycle, and the power management software must not use or employ any other means aside from this I/O cycle to trigger a state transition to C3. The power management controller must allow the I/O cycle to complete before asserting STPCLK#.
State Transition Timing Information/Requirements Diagram NoteSTPCLK# assertion to Stop Grant cycle 3.5 µS typical
8 µS maximumT1
STPCLK# deassertion to C0 3 µS typical5 µS maximum
T2
State Transition Timing Information/Requirements Diagram NoteSTPCLK# assertion to Stop Grant cycle 3.5 µS typical
8 µS maximumT1
Stop Grant to SLEEP# assertion latency 2 µS minimum T2SLEEP# hold time 100 nS minimum required T3SLEEP# assertion to host clock shutdown 17 nS minimum required T4Host clock restart to SLEEP# deassertion 20 µS minimum required T5
Quick Start (C2)CPU_CLK
STPCLK#
Stop Grant
x86execution
T1 T2
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Processor Power Supplies and PowerManagement
Refer to the above table for a description of the notes in the diagram below:
ACPI System Sleep State (S1)
The S1 signaling is like C3, except that in S1 the PCI clock is typically shut down while SLEEP# is asserted.
All the C3 requirements also apply for S1. The PCI clocks should be running any time SLEEP# is not asserted.
SLEEP# deassertion to STPCLK# deassertion
320 nS minimum recommended T6
STPCLK# deassertion to C0 3 µS typical5 µS maximum
T7
State Transition Timing Information/Requirements Diagram Note
STPCLK# assertion to Stop Grant cycle 3.5 µS typical8 µS maximum
T1
Stop Grant to SLEEP# assertion 2 µS minimum T2SLEEP# hold time, PCI clock typically shut down 100 nS minimum required T3SLEEP# assertion to host clock shut down 17 nS minimum required T4Host clock restart to SLEEP# deassertion 20 µS minimum required T5SLEEP# deassertion to STPCLK# deassertion 320 nS minimum recommended T6STPCLK# deassertion to C0 3 µS typical
5 µS maximumT7
State Transition Timing Information/Requirements Diagram Note
Deep Sleep (C3)
STPCLK#
Stop Grant
x86execution
SLEEP#
CPU_CLK
T1
T2
T4 T5
T6
T7
T3
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Processor Power Supplies and Power Management
Refer to the above table for a description of the notes in the diagram below:
ACPI Suspend-to-RAM State (S3)
The C0 to S3 transition is typically caused by an I/O cycle to the power management controller.
The I/O cycle that initiates the S3 sleep state is typically snooped by the processor. The processor integrated northbridge must be properly configured to snoop this I/O cycle, and the power management software must not use any other means aside from this I/O cycle to trigger a state transition to S3.
The processor will place the DRAMs into self-refresh by the time the I/O cycle reaches the power management controller. There are no special requirements for the power management signaling between the I/O cycle and the removal of main power.
Total System Latency
The total latency for entering and exiting the C2 and C3 states is largely a function of the overall system design. Here are some examples of system characteristics and the expected total entrance and exit latencies.
Example 1 (C2)
A system designer may implement a system with the following C2 characteristic:
• In response to a wake event from C2, the power management controller de-asserts the processor STPCLK# signal no earlier than 2 µS after receiving the Stop Grant cycle.
System Sleep State (S1)
STPCLK#
Stop Grant
x86execution
SLEEP#
CPU_CLK
PCI_CLK
T1
T2
T4 T5T7
T6T3
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Processor Power Supplies and PowerManagement
This type of system is expected to have a typical C2 entrance + exit latency of 8.5 µS, and a worst-case C2 entrance + exit latency of 15 µS.
Example 2 (C3)
A system designer may implement a system with the following C3 characteristics:
• The power management controller waits 64 µS after receiving the Stop Grant cycle before it asserts the processor SLEEP# signal.
• The power management controller waits 32 µS between asserting the processor SLEEP# signal and asserting the clock generator CPU_STP# signal.
• In response to a wake event from C3, the power management controller de-asserts the clock generator CPU_STP# signal no earlier than 2 µS after it asserted the clock generator CPU_STP# signal.
• The clock generator requires < 12 µS for restarting the processor CPU_CLK# upon deassertion of the clock generator CPU_STP# signal.
• The power management controller waits 32 µS between de-asserting the clock generator CPU_STP# signal and de-asserting the processor SLEEP# signal.
• The power management controller waits 64 µS between de-asserting the processor SLEEP# signal and de-asserting the processor STPCLK# signal.
This type of system is expected to have a worst-case C3 entrance + exit latency of 207 µS.
Example 3 (C3)
A system designer may implement a system with the following C3 characteristics:
• The power management controller waits 2 µS after receiving the Stop Grant cycle before it asserts the processor SLEEP# signal.
• The power management controller waits 32 µS between asserting the processor SLEEP# signal and asserting the clock generator CPU_STP# signal.
• In response to a wake event from C3, the power management controller de-asserts the clock generator CPU_STP# signal no earlier than 2 µS after it asserted the clock generator CPU_STP# signal.
• The clock generator requires < 12 µS for restarting the processor HCLK# upon deassertion of the clock generator CPU_STP# signal.
• The power management controller waits 32 µS between de-asserting the clock generator CPU_STP# signal and de-asserting the processor SLEEP# signal.
• The power management controller waits 60 nS between de-asserting the processor SLEEP# signal and de-asserting the processor STPCLK# signal.
This type of system is expected to have a worst-case C3 entrance + exit latency of 82 µS.
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Processor Power Supplies and Power Management
LongRun Power Management
LongRun power management is a power saving feature of TM5500/TM5800 processors that allows the processor to dynamically change its operating frequency and voltage in response to the instantaneous performance demands of running applications. The basic goal is to provide just-sufficient performance for the task at hand, without expending any more energy than is strictly necessary.
In Code Morphing software, LongRun power management defines up to eight performance levels, each consisting of a unique operating frequency and a unique operating voltage. Each successive performance level has a higher frequency and voltage than the previous one. When LongRun power management is enabled, it will raise and lower the performance level based on the amount of idle time in the system.
The algorithms that LongRun power management uses to determine when to raise or lower the performance level are fairly complex, and beyond the scope of this document. This document will only focus on how LongRun power management relates to hardware signals external to the processor.
Frequency Change Mechanism
When the core and memory frequencies are changed, LongRun power management must start by ensuring that there is no external activity in the system during the frequency change. This is accomplished by flushing any queued PCI or memory writes, and force-granting the PCI bus to the processor.
In addition, since the memory frequencies may be changed at the same time as the core frequency, the memories must not be accessed during the frequency change process. LongRun power management thus places the memories into self-refresh, and then writes new multipliers/divisors for the core and memory frequencies. Then the clocks are stopped, and hardware commences the frequency change, after which the processor wakes up and starts running with the new core and memory frequencies.
Finally, the memories are brought out of self-refresh, and the force-granted PCI bus is released.
LatencyTiming Information/Requirements Diagram Note
ISR execution to PCI Force Grant 1 µS typical2 µS maximum
T1
PCI Force Grant to memories in self-refresh 1 µS typical2 µS maximum
T2
Memory self-refresh to clocks off 1 µS typical2 µS maximum
T3
PLL relock time 10 µS minimum requiredvalue configurable
T4
Clocks on to memory out of self-refresh 1 µS typical2 µS maximum
T5
Memory out of self-refresh to PCI Force Grant deassert
1 µS typical2 µS maximum
T6
PCI Force Grant deassert to end of ISR execution 2 µS typical4 µS maximum
T7
Voltage regulator settling time 64 µS default value configurable 1
1. This value may be required to be set to 256 µS for some silicon revisions
T8
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Processor Power Supplies and PowerManagement
Voltage Change Mechanism
The voltage change mechanism is extremely simple when compared to the frequency change mechanism. In essence, the processor just writes a value to the 5 pins on the regulator, and the voltage changes.
The only complication from the hardware side is that some voltage regulators may deassert POWERGOOD if they change their output too rapidly, resulting in a system reset. Thus, LongRun power management only changes the voltages in 1 LSB increments, and incorporates a delay between increments to account for the regulator settling time. The default LongRun power management parameters assume a 64 µS settling time, which is compatible with the voltage regulators referenced in this document.
Note that though LongRun power management requires a minimum regulator settling time to operate correctly, this settling time does not result in processor dead time, since the processor continues to execute x86 instructions during the voltage change.
LongRun Power Management Frequency Change
PCI
Core
Force Grant*
memoryself-refresh*
new clock multipliers/divisors written
T2
T3 T5
T4
T6
Clock
ISR Executing*
* these traces do not representhardware signals, but rather logicalstates.
T1 T7
MemoryClocks
Volta
ge
Time
1 LSB on the regulator
T8
LongRun Power Management Voltage Change
July 17, 2002
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Processor Power Supplies and Power Management
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C h a p t e r 4
DDR Memory Design
This chapter provides guidelines for implementing DDR SDRAM memory interface designs for TM5500/TM5800 processors. Following the recommended DDR memory interface design rules and layout procedures will result in reliable system designs that maximize performance while minimizing power consumption. Signal descriptions and timing specifications for the TM5500/TM5800 DDR SDRAM memory interface can be found in the Data Book.
4.1 DDR Memory Interface The DDR SDRAM interface is the highest performance memory interface available on TM5500/TM5800 processors. The DDR controller supports only DDR SDRAM and transfers data at a rate that is twice the clock frequency of the interface. The DDR SDRAM controller supports the equivalent of one DIMM (one bank only) of DDR SDRAM using a 64-bit wide interface. The DDR SDRAM interface does not support parity bits.
The DDR SDRAM can be populated with 64-Mbit, 128-Mbit, 256-Mbit, or 512-Mbit devices. For the highest performance, it is recommended that the DDR SDRAM devices be soldered down to the circuit board, rather than incorporated on DIMMs. The DDR SDRAM interface supports only x8 or x16 devices. The table below shows possible TM5500/TM5800 DDR SDRAM configurations.
Table 11: DDR SDRAM Memory Configurations
DDR Device Size
DDR Device Configuration
Devices per Bank
Mbytes per Bank
Maximum Banks
Maximum Memory Size
64 Mbit 4M x 16 4 32 1 32 Mbytes8M x 8 8 64 1 64 Mbytes
128 Mbit 8M x 16 4 64 1 64 Mbytes16M x 8 8 128 1 128 Mbytes
256 Mbit 16M x 16 4 128 1 128 Mbytes32M x 8 8 256 1 256 Mbytes
512 Mbit 32M x 16 4 256 1 256 Mbytes64M x 8 8 512 1 512 Mbytes
July 17, 2002
52
DDR Memory Design
The frequency setting for the DDR SDRAM interface is initialized during the boot sequence from data stored in the configuration ROM. DDR interface frequency settings vary at each LongRun power management step. DDR interface timing specifications and operating frequencies at various LongRun power management steps are provided in the Data Book. The Data Book also provides DDR memory interface configuration constraints, as well as recommended and example system memory configurations. See the OEM Configuration Table chapter of the Development and Manufacturing Guide for further LongRun configuration and memory frequency information.
4.2 Clock Enable Isolation The processor DDR_CKE clock enable signals must be isolated from the DDR SDRAM. This is because power states exist where the processor is powered down and the DDR SDRAM remains powered (e.g. STR).
Since TM5500/TM5800 processors do not have a suspend power well, output signals are undefined during power transitions and subject to glitching. The SUSPEND_STATUS signal from the southbridge remains asserted while in STR mode, and is therefore used to control the isolation switches.
4.3 Signal Termination Series termination is recommended on all signals. Termination impedance should be calculated on a per-design basis.
July 17, 2002
53
DDR Memory Design
4.4 DDR Reference Voltage The VDDIO25 power supply pins of the processor are connected to V2_5. The DDR interface has a DDR_VREF pin whose input should be derived from that power supply using a 1% resistor voltage divider. The specification for this input is described in the Data Book. Two examples are provided below for selecting DDR_VREF divider resistor values.
• For a DDR_VREF specification of 1.25 V, the recommended V2_5 voltage divider network for deriving DDR_VREF is: upper resistor (tied to V2_5) = 2490 Ω, and lower resistor (tied to ground) = 2490 Ω.
• For a DDR_VREF specification of 1.35 V, the recommended V2_5 voltage divider network for deriving DDR_VREF is: upper resistor (tied to V2_5) = 1960 Ω, and lower resistor (tied to ground) = 2320 Ω.
4.4.1 DDR Reference Voltage Noise Filter Circuit TM5500/TM5800 processors require a ferrite bead noise filter on the C_VREF DDR interface reference voltage signal. C_VREF is derived from IOVDD25 (2.5 V I/O power supply) using a resistive voltage divider. The recommended noise filter circuit is shown below.
Figure 5: Recommended DDR Reference Voltage Circuit with Ferrite Bead Noise Filter
R22.32K1%
GND
V2_5
C10.1uF
R11.96K1%
C_VREF_A
GND
C_VREF
FB2100 Ohms @ 100 MHz0805
C_VREFK19
U1ACrusoe BGA474
NOTE:PLACE FB2 AS CLOSE ASPOSSIBLE TO PROCESSORBALL K19
TM5500/TM5800Processor
July 17, 2002
54
DDR Memory Design
4.5 DDR Memory Interface Design Guidelines The DDR SDRAM interface operates at frequencies of 100-133 MHz. Use standard high-speed design, layout, and routing practices. Some specific guidelines in DDR memory layout are provided below.
• To achieve the most ideal DDR layout possible, the TM5500/TM5800 DDR interface and memory layout should be completed first, with trace lengths as short as possible, before other sections of the design layout complicate DDR signal routing.
• A nominal DDR SDRAM layout must have trace lengths less than 4”.
• Data traces are routed in groups. Each group consists of one DDR_DQS, one DDR_DQMB, and eight DDR_DQ lines.
• The DDR_DQ and DDR_DQMB signals within each group must be routed such that the maximum difference in their lengths is 0.4” or less. The DDR_DQS signal for the group must have a length that is within 0.1” of the longest other trace in that group. The length of all DQS signals must be within a 2” range and within 1” of the length of the clocks.
• The differential clocks (DDR_CLKA/A#, DDR_CLKB/B#) must be routed such that the length of each clock signal to each SDRAM is the same length within 0.05”. The length of the clocks must be within 1.0” of all DQS signals.
• All byte groups may be swapped with other byte groups and all data bits within each byte may be swapped to facilitate meeting length requirements.
• Characteristic impedance should be 60 Ω ± 10%.
• Layout components as shown in the example below. The components should be exactly on top of one another in the following specified order. Devices 0-1 get differential clock pair DDR_CLKA/DDR_CLKA# and devices 2-3 get differential clock pair DDR_CLKB/DDR_CLKB#.
July 17, 2002
55
DDR Memory Design
4.6 PCB Placement and Routing Example
Device Placement
The figure below shows the recommended TM5500/TM5800 processor and four DDR memory device placement using both sides of the PCB.
Figure 6: Recommended 4-Device DDR Memory Chip Placement
DDR 2
DDR 3
DDR 0TM5x00
Processor
DDR 1
Top BottomPlace components one overthe other on opposite sides ofthe board. in this configuration.
U3
U4
U1TM5x00
Processor
U2
Top BottomPlace components one overthe other on opposite sides ofthe board. in this configuration.
July 17, 2002
56
DDR Memory Design
Primary Side (Top Layer) Signal Routing
The figure below shows the connections from the TM5500/TM5800 processor to the DDR memory on the primary (top layer) side of the board.
Figure 7: Recommended 4-Device DDR Memory Signal Routing - Top Layer
1 1
U5 U6U2U1
July 17, 2002
57
DDR Memory Design
Internal Layer Signal Routing
The figure below shows the connections from the TM5500/TM5800 processor to the DDR memory on an internal layer of the board.
Figure 8: Recommended 4-Device DDR Memory Signal Routing - Internal Layer
July 17, 2002
58
DDR Memory Design
Secondary Side (Bottom Layer) Signal Routing
The figure below shows connections from the TM5500/TM5800 processor to the DDR memory on the secondary (bottom layer) side of the board.
Figure 9: Recommended 4-Device DDR Memory Signal Routing - Bottom Layer
1 1
U8 U7U4 U3
July 17, 2002
59
DDR Memory Design
4.7 DDR SDRAM Schematics The following pages show DDR SDRAM reference schematics.
• Single bank DDR soldered down (2 pages)
• Single bank DDR SODIMM (2 pages)
• DDR clock enable isolation circuit (1 page)
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilFriday, November 30, 2001 1 2
Single Bank DDR Down (1/2)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
DDR_DQM0
DDR_DQ21
DDR_DQ24
DDR_BA0
DDR_A12
DDR_RAS#
DDR_DQM2
DDR_DQ14
DDR_A3
DDR_DQ26
DDR_DQ6
DDR_MWE#
DDR_DQ8
CLK_DDRA#
DDR_A3DDR_DQ3
DDR_DQS2
DDR_A11DDR_DQ28
DDR_DQM1
DDR_A0DDR_DQ1
CLK_DDRA
DDR_DQ23
DDR_DQ18DDR_DQ2
DDR_BA0
DDR_A1
DDR_RAS#
DDR_A1
DDR_DQ5DDR_A4
DDR_DQ15
DDR_DQ11
DDR_DQS0
DDR_DQ27
DDR_A5
DDR_CAS#
DDR_DQ10
DDR_DQM3
DDR_BA1
DDR_A4
CLK_DDRA
DDR_A8
DDR_DQ13
DDR_CAS#
DDR_A2
DDR_DQ22
DDR_DQ9
DDR_A5
DDR_DQ25
DDRVREF
DDR_DQ12
DDR_DQ4
DDR_CKE0
DDR_DQ0
DDR_A9DDR_A8
DDR_A11
DDR_A6
DDR_A9
DDR_CKE0
DDR_A12
DDR_DQS1
DDR_A6
DDR_CS0#
DDR_BA1
DDR_DQ29
DDRVREF
DDR_DQ17
DDR_DQ7
DDR_DQS3
DDR_A10
DDR_A7
DDR_DQ30DDR_DQ31
DDR_A0
DDR_DQ20
DDR_CS0#
DDR_DQ16
DDR_MWE#
DDR_A7
DDR_DQ19
DDR_A10
CLK_DDRA#
DDR_A2
DDR_BA0
DDR_DQ[63:0]
DDR_A[12:0]
CLK_DDRA
DDR_RAS#
DDR_DQM[7:0]
DDR_CAS#
DDR_CKE0
DDR_DQS[7:0]
DDR_BA1
DDR_CS0#
CLK_DDRA#
DDRVREF
DDR_MWE#
DDRVREF
V2_5_STR
V2_5_STR
V2_5_STR
R17681%
12
U2128Mb DDR SDRAM
1
2
3
45
6
78
9
1011
12
13
14
15
16
17
18
19
20
21222324
25
2627
28
29303132
33 66
65
64
6362
61
6059
58
5756
55
54
53
52
51
50
49
48
47
4645
44
43
4241
403938373635
34VDD
DQ0
VDDQ
DQ1DQ2
VSSQ
DQ3DQ4
VDDQ
DQ5DQ6
VSSQ
DQ7
NC1
VDDQ
LDQS
NC2
VDD
NU/QFC
LDM
WE#CAS#RAS#CS#
NC3
BA0BA1
A10/AP
A0A1A2A3
VDD VSS
DQ15
VSSQ
DQ14DQ13
VDDQ
DQ12DQ11
VSSQ
DQ10DQ9
VDDQ
DQ8
NC6
VSSQ
UDQS
NC5
VREF
VSS
UDM
CK#CK
CKE
NC4
A12A11
A9A8A7A6A5A4
VSS
R27681%
12
C10.1uFX7R
12
U1128Mb DDR SDRAM
1
2
3
45
6
78
9
1011
12
13
14
15
16
17
18
19
20
21222324
25
2627
28
29303132
33 66
65
64
6362
61
6059
58
5756
55
54
53
52
51
50
49
48
47
4645
44
43
4241
403938373635
34VDD
DQ0
VDDQ
DQ1DQ2
VSSQ
DQ3DQ4
VDDQ
DQ5DQ6
VSSQ
DQ7
NC1
VDDQ
LDQS
NC2
VDD
NU/QFC
LDM
WE#CAS#RAS#CS#
NC3
BA0BA1
A10/AP
A0A1A2A3
VDD VSS
DQ15
VSSQ
DQ14DQ13
VDDQ
DQ12DQ11
VSSQ
DQ10DQ9
VDDQ
DQ8
NC6
VSSQ
UDQS
NC5
VREF
VSS
UDM
CK#CK
CKE
NC4
A12A11
A9A8A7A6A5A4
VSS
C160.001uFX7R
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilThursday, June 14, 2001 2 2
Single Bank DDR Down (2/2)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
DDR_DQ32
DDR_DQ45
DDR_A5
DDR_DQ41
DDRVREF
DDR_DQM7
DDR_A0
DDR_DQ51
DDR_DQS7
DDR_DQ59DDR_DQ44
DDR_DQS5
DDR_MWE#
DDR_BA0
DDR_MWE#
DDR_DQ58
DDR_DQ35
DDR_A8DDR_A9
DDR_DQM6
DDR_DQ50
DDR_DQ54
DDR_DQS6
DDR_DQ39
CLK_DDRB
DDR_DQS4
DDR_A4
DDR_DQ33
DDR_DQ61
DDRVREF
DDR_DQM4
DDR_A7
DDR_A12
DDR_DQ49
DDR_CS0#
DDR_A9
DDR_CKE0DDR_DQ63
DDR_DQ42
DDR_A4
DDR_DQ43
DDR_DQ53
DDR_DQ56DDR_A7
DDR_A11
DDR_A5
DDR_A3
DDR_A6
DDR_A11
DDR_DQ47DDR_DQ62
DDR_DQ55
DDR_DQM5
DDR_A6
DDR_A1
DDR_CKE0
DDR_A2
DDR_CAS#
DDR_A12
CLK_DDRB#
DDR_DQ60
DDR_BA1DDR_BA1
DDR_A3
DDR_CAS#
DDR_BA0
DDR_DQ36
DDR_A10
DDR_DQ40
CLK_DDRB DDR_DQ46
DDR_DQ48DDR_A1
DDR_DQ38DDR_DQ37
DDR_A10
DDR_A0
DDR_A8
CLK_DDRB#
DDR_DQ34
DDR_CS0#
DDR_A2
DDR_RAS# DDR_RAS#
DDR_DQ57
DDR_DQ52
DDR_A[12:0]
DDR_DQ[63:0]
DDR_DQS[7:0]
DDR_BA0
DDR_CS0#DDR_CKE0
DDR_RAS#
CLK_DDRB#
DDR_CAS#DDR_MWE#
DDR_DQM[7:0]
DDRVREFDDR_BA1
CLK_DDRB
V2_5_STR
V2_5_STR V2_5_STR
C60.1uF
12
C120.1uF
12
C100.1uF
12
C110.1uF
12
C130.1uF
12
C30.1uF
12
C90.1uF
12
C210uFX5R
12
C140.1uF
12
C40.1uF
12
C80.1uF
12
U3128Mb DDR SDRAM
1
2
3
45
6
78
9
1011
12
13
14
15
16
17
18
19
20
21222324
25
2627
28
29303132
33 66
65
64
6362
61
6059
58
5756
55
54
53
52
51
50
49
48
47
4645
44
43
4241
403938373635
34VDD
DQ0
VDDQ
DQ1DQ2
VSSQ
DQ3DQ4
VDDQ
DQ5DQ6
VSSQ
DQ7
NC1
VDDQ
LDQS
NC2
VDD
NU/QFC
LDM
WE#CAS#RAS#CS#
NC3
BA0BA1
A10/AP
A0A1A2A3
VDD VSS
DQ15
VSSQ
DQ14DQ13
VDDQ
DQ12DQ11
VSSQ
DQ10DQ9
VDDQ
DQ8
NC6
VSSQ
UDQS
NC5
VREF
VSS
UDM
CK#CK
CKE
NC4
A12A11
A9A8A7A6A5A4
VSS
C150.1uF
12
U4128Mb DDR SDRAM
1
2
3
45
6
78
9
1011
12
13
14
15
16
17
18
19
20
21222324
25
2627
28
29303132
33 66
65
64
6362
61
6059
58
5756
55
54
53
52
51
50
49
48
47
4645
44
43
4241
403938373635
34VDD
DQ0
VDDQ
DQ1DQ2
VSSQ
DQ3DQ4
VDDQ
DQ5DQ6
VSSQ
DQ7
NC1
VDDQ
LDQS
NC2
VDD
NU/QFC
LDM
WE#CAS#RAS#CS#
NC3
BA0BA1
A10/AP
A0A1A2A3
VDD VSS
DQ15
VSSQ
DQ14DQ13
VDDQ
DQ12DQ11
VSSQ
DQ10DQ9
VDDQ
DQ8
NC6
VSSQ
UDQS
NC5
VREF
VSS
UDM
CK#CK
CKE
NC4
A12A11
A9A8A7A6A5A4
VSS
C50.1uF
12
C70.1uF
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilThursday, June 14, 2001 1 2
Single DDR SODIMM (1/2)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
DDR_DQS4
DDR_DQ29
DDR_DQ15
DDR_DQ57
DDR_DQ41
DDR_DQ2
DDR_DQ61
DDR_DQ34
DDR_A9
DDR_DQS7
DDR_DQM4
DDR_DQ50
DDR_DQ36
DDR_DQM7
DDR_A0
DDR_DQS3
DDR_DQ25
DDR_DQ44
DDR_DQ6DDR_DQ7DDR_A7
DDR_DQ9
DDR_DQM2
DDR_DQ45
DDR_DQ13
DDR_DQS5
DDR_DQ56
DDR_DQ58
DDR_DQ55
DDR_DQM0
DDR_DQ14
DDR_DQM3
DDR_DQ53
DDR_DQM1
DDR_DQS1DDR_DQS2
DDR_DQ63
DDR_DQ4
DDR_DQ37
DDR_DQ23
DDR_DQ40
DDR_A11
DDR_DQ32
DDR_A1
DDR_DQ21DDR_DQ20
DDR_DQ35
DDR_DQ17
DDR_SOD1_SA2
DDR_DQ30
DDR_A6
DDR_SOD1_SA0
DDR_DQS0
DDR_DQ38
DDR_DQ27
DDR_A5DDR_A4
DDR_DQ62
DDR_DQ52
DDR_DQ19
DDR_DQ31
DDR_A2DDR_DQ1
DDR_A12
DDR_A3
DDR_DQ26
DDR_DQ59
DDR_DQ18
DDR_DQM5
DDR_SOD1_SA1
DDR_DQ60
DDR_DQ33
DDR_DQ43
DDR_DQ51
DDR_DQ8
DDR_DQ39
DDR_DQ28
DDR_DQ5
DDR_DQ22
DDR_DQ46
DDR_DQ49
DDR_DQ54
DDR_DQ48
DDR_A8
DDR_DQS6
DDR_DQ16
DDR_DQ10
DDR_DQ24
DDR_DQ0
DDR_DQM6
DDR_DQ11
DDR_DQ3
DDR_DQ47
DDR_DQ42
DDR_DQ12
DDR_A10
DDR_CS0#
DDR_DQ[63..0]
DDR_CKE1
DDR_CS1#
CLK_DDRA
DDR_DQS[7..0]
CLK_DDRA#CLK_DDRB
SMBCLK
DDR_RAS#
DDR_DQM[7..0]
DDR_BA1DDR_BA0
DDR_MWE#
DDR_A[12..0]
SMBDATA
DDR_CAS#
DDR_CKE0
CLK_DDRB#
V3_3
J1A200_SODIMM_DDR
1121111101091081071061051021011151009997
12264862
134148170184
121122
118120119
11711698
3537
1601588991
9695
195193
867173798372748084
7778 85
123124200
194196198
5713176814181923293120243032
41434953424450545559656756606668
127129135139128130136140141145151153142146152154
163165171175164166172176177181187189178182188190
18316914713361472511
A_00A_01A_02A_03A_04A_05A_06A_07A_08A_09A_10A_11A_12A_13
DM_0DM_1DM_2DM_3DM_4DM_5DM_6DM_7
S0#S1#
RAS#CAS#WE#
BA0BA1BA2
CK0CK0#CK1CK1#CK2CK2#
CKE0CKE1
SCLSDA
RESET#CBQ0CBQ1CBQ2CBQ3CBQ4CBQ5CBQ6CBQ7
CBQSCBDM NC1
NC2NC3NC4
SA0SA1SA2
DQ_00DQ_01DQ_02DQ_03DQ_04DQ_05DQ_06DQ_07DQ_08DQ_09DQ_10DQ_11DQ_12DQ_13DQ_14DQ_15
DQ_16DQ_17DQ_18DQ_19DQ_20DQ_21DQ_22DQ_23DQ_24DQ_25DQ_26DQ_27DQ_28DQ_29DQ_30DQ_31
DQ_32DQ_33DQ_34DQ_35DQ_36DQ_37DQ_38DQ_39DQ_40DQ_41DQ_42DQ_43DQ_44DQ_45DQ_46DQ_47
DQ_48DQ_49DQ_50DQ_51DQ_52DQ_53DQ_54DQ_55DQ_56DQ_57DQ_58DQ_59DQ_60DQ_61DQ_62DQ_63
DQS_7DQS_6DQS_5DQS_4DQS_3DQS_2DQS_1DQS_0
R20
12
R30
12
R110K
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilTuesday, August 14, 2001 2 2
Single DDR SODIMM (2/2)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
V3_3
V2_5_STR
V2_5_STR
V2_5_STR
V2_5_STR
R57681%
12
C80.1uF
12
C120.001uF
12
C40.1uF
12
C110.1uF
12
C90.1uF
12
C30.1uF
12
J1B200_SODIMM_DDR
197199
12
3415162728383940515263647576878890103104125126137138149150159161162173174185186
91021223334364546575869708182929394
113114131132143144155156157167168179180191192
VDDSPDVDDID
VREFAVREFB
GND_01GND_02GND_03GND_04GND_05GND_06GND_07GND_08GND_09GND_10GND_11GND_12GND_13GND_14GND_15GND_16GND_17GND_18GND_19GND_20GND_21GND_22GND_23GND_24GND_25GND_26GND_27GND_28GND_29GND_30GND_31GND_32GND_33
VDD_01VDD_02VDD_03VDD_04VDD_05VDD_06VDD_07VDD_08VDD_09VDD_10VDD_11VDD_12VDD_13VDD_14VDD_15VDD_16VDD_17VDD_18VDD_19VDD_20VDD_21VDD_22VDD_23VDD_24VDD_25VDD_26VDD_27VDD_28VDD_29VDD_30VDD_31VDD_32VDD_33
C60.1uF
12
C100.1uF
12
C20.1uF
12
C70.1uF
12
C50.1uF
12
C10.1uF
12
R47681%
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TWO DISCRETE QUICKSWITCHES ARE USEDTO FACILITATE LAYOUT PLACEMENT.
TM5800 Design Guide
Custom
ABasilThursday, November 29, 2001 1 1
CKE Quickswitch3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
DDR_CKE_MUX1
DDR_CKE_MUX0
AGP_STP#
DDR_CKE0
DDR_CKE1
SUSP_ALI#SUSPEND#
SDR_CKE1
SDR_CKE0
SDR_CKE_MUX1
SDR_CKE_MUX0
V3_3_ALWAYS
V5_0_ALWAYS
V5_0_ALWAYS
U3QS3257QUALITY SEMI
2356
11101413
151
4
7
9
12
16
8
1A1B2A2B3A3B4A4B
GA#/B
1Y
2Y
3Y
4Y
VCC
GND
U27SZ08FAIRCHILD SEMI
1
24
53
R11K
12
C20.1uF
12
C10.1uF
12
R21K
12
U1QS3257QUALITY SEMI
2356
11101413
151
4
7
9
12
16
8
1A1B2A2B3A3B4A4B
GA#/B
1Y
2Y
3Y
4Y
VCC
GND
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C h a p t e r 5
SDR Memory Design
This chapter provides guidelines for implementing SDR SDRAM memory interface designs for TM5500/TM5800 processors. Following the recommended SDR memory interface design guidelines and layout procedures will result in reliable system designs that maximize performance while minimizing power consumption. Signal descriptions and timing specifications for the TM5500/TM5800 SDR SDRAM memory interface can be found in the Data Book.
5.1 SDR Memory Interface The SDR SDRAM controller supports up to two 64-bit DIMMS (up to four banks) of single data rate SDRAM. The SDR SDRAM interface does not support parity bits. SDR SDRAM DIMMs can be populated with 64-Mbit, 128-Mbit, 256-Mbit, or 512-Mbit devices. All DIMMs must use the same frequency SDRAMs, but there are no restrictions on mixing different DIMM configurations into the two DIMM slots.
Table 12 shows possible SDR SDRAM configurations for a TM5500/TM5800 processor-based system. The maximum memory size in Table 12 assumes two double-sided DIMMs of identical configuration and a maximum of 8 total devices per DIMM.
Table 12: SDR SDRAM Memory Configurations
SDR Device SizeSDR Device Configuration
Devices per Bank
MBytes per Bank
Maximum Banks
Maximum Memory Size
64 Mbits 4M x 16 4 32 4 128 MBytes8M x 8 8 64 216M x 4 16 128 1
128 Mbits 8M x 16 4 64 4 256 MBytes16M x 8 8 128 232M x 4 16 256 1
256 Mbits 16M x 16 4 128 4 512 MBytes32M x 8 8 256 264M x 4 16 512 1
512 Mbits 32M x 16 4 256 4 1024 MBytes64M x 8 8 512 2
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SDR Memory Design
The frequency setting for the SDR SDRAM interface is initialized during the boot sequence from data stored in the configuration ROM. SDR interface frequency settings vary at each LongRun power management step. SDR interface timing specifications and operating frequencies at various LongRun power management steps are provided in the Data Book. The Data Book also provides SDR memory interface configuration constraints, as well as recommended and example system memory configurations. See the OEM Configuration Table chapter of the Development and Manufacturing Guide for further LongRun configuration and memory frequency information.
5.2 SDR Memory Interface Design Guidelines The SDR SDRAM interface operates at frequencies up to 133 MHz and with edge rates as fast as 100 pS. Use careful high-speed design, layout, and routing practices to minimize inductance and crosstalk, maintaining the integrity of the transmission line structure throughout. Some specific guidelines for SDR memory layout are provided below.
• Place the memory as close as possible to the processor and oriented to reduce routing lengths.
• A nominal SDR layout is based on the total trace length of any SDR address or command signal (motherboard plus DIMM, if used). For a given number of loads, the rules are as follows:
- For up to 16 loads the maximum total trace length must be <= 5”.- For up to 12 loads the maximum total trace length must be <= 8”.
• Source termination of 33 Ω (at the processor) is recommended for the data and mask signals.
• Source termination of 10 Ω (at the processor) is recommended for the address and command signals.
• The clock signals should be of matched lengths. Source termination of 22 Ω (at the processor) is recommended for the clock signals.
• The SDR_CLKOUT signal should have a 33 Ω source termination resistor. The trace routing from the output of this resistor to the SDR_CLKIN processor input is a timing delay. This trace length should be equal to the sum of the total length of a clock trace and the length of the shortest data signal route. This is explained in detail in SDR SDRAM Layout Notes on page 67.
• Characteristic impedance should be 55 Ω ± 10% for SDR-only systems. If DDR is present, the characteristic impedance should be 60 Ω ± 10%.
• For specific information about memory timing, see the Data Book. Refer to the Development and Manufacturing Guide for additional information on memory configuration.
5.2.1 Bank Selection The memory banks are selected with the SD_CS[3:0] signals. Use them in-order from highest to lowest. For example, if only one bank of memory is used, connect it to SD_CS[3]. For one DIMM, which may have two banks, connect SD_CS[3:2]. If both soldered-down memory and DIMM are used, connect the highest-order bits to the soldered-down memory.
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SDR Memory Design
5.2.2 Clock Enable Isolation During Power-down States The processor SD_CKE[3:0] clock enable signals must be isolated from the SDR SDRAM. This is because power states exist where the processor is powered down and the SDR SDRAM remains powered (e.g. STR). The processor does not have a suspend power well, and like any CMOS circuit, the outputs are undefined for short periods of time during power transitions. It is likely that all the signals glitch as power is applied or removed from the processor. If the clock enable signal on the SDRAM remains at a stable state, preventing activity within the SDRAM during power transitions, data integrity is maintained.
The SUSPEND_STATUS signal from the southbridge remains asserted while in STR mode, and is therefore used to control the isolation. The output should multiplex between a pull-down resistor and the SD_CKE signal from the processor, controlled by SUSPEND_STATUS.
5.2.3 Signal Termination Series termination is recommended for all signals. Termination impedance should be calculated on a per-design basis.
5.2.4 Miscellaneous Notes If DIMMs are used, the serial presence detect (SPD) bus must be connected to the southbridge (not shown in the block diagram).
All SDR SDRAM power supply inputs should be connected to V3_3_STR.
5.3 SDR SDRAM Layout Notes This section describes procedures and guidelines for implementing SDR memory interface designs for TM5500/TM5800 processors. Following the recommended SDR memory interface design rules and layout procedures will result in reliable system designs that maximize performance while minimizing power consumption.
5.3.1 SDR SDRAM Memory Interface Timing The TM5500/TM5800 processor SDR SDRAM memory controller is capable of addressing up to four banks of memory. The SDRAM configuration and size of each bank may be different.
The four clocks from the memory controller are copies of the SDR SDRAM clock. It does not matter which clock goes to which bank, as bank selection is done with the CKE# and select lines. The clocks always have four loads, making their behavior very predictable.
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SDR Memory Design
The critical timing parameters of the processor memory controller and SDR SDRAM devices are shown in Table 13. The design rules described in this document satisfy these timings.
Careful placement and routing of the SSDR DRAM interface signals results in the best possible memory performance. Trace lengths can be controlled and clock feedback delays correctly calculated. If provision is made to compensate for layout and timing uncertainties with zero Ω resistors, it is possible to attain PC133 data rates on TM5500/TM5800 processor-based system designs.
5.3.2 Example Design Strategy Layout of the TM5500/TM5800 processor SDR SDRAM interface is simplified with the application of one basic strategy:
Laying out the SDR SDRAM design using only JEDEC-compliant SODIMMs is very straightforward. Place the SODIMMs close together, using reverse-image connectors, routing signals from the processor to the SODIMMs.
Note that if the SODIMM connectors are placed in close proximity, it does not matter whether a star or daisy-chain topology is used.
If the SDR SDRAM memory is laid out in this way, the system has the best possible performance, as long as the read and write timings are carefully controlled.
Table 13: SDR SDRAM Interface Device Specifications
Device Output Hold Time Input Setup Time Input Hold Time
TM5500/TM5800 (800 MHz SKU) 1
1. The figures listed here are examples only. See the Data Book for processor memory timing specifications.
1.38-1.96 nS 1.7 nS 1.9 nS
JEDEC-compliant SDRAM 2.2-5.0 nS 1.5 nS 0.8 nS
Critical RuleThe TM5500/TM5800 processor SDR SDRAM layout works optimally with SODIMMs, specifically JEDEC-compliant SODIMMs.
Figure 10: Physical SDRAM Configurations
CPUSODIMM 0
SODIMM 1
CPU
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SDR Memory Design
5.3.3 Write Timing
The minimum output hold time of the processor exceeds the input hold time of the SDRAM by:
Because of this, the flight time of the clock must not exceed the latest data, address or control signal by more than 450 pS. Unfortunately, compensation must be made for the negative skew built into the JEDEC specification.
The clock length on an SODIMM is specified as 2.50”, or 445 pS (routed on inner traces). All the other signals on the SODIMM are some distance less than this. This difference must be added to each trace on the motherboard as timing compensation, as specified in Table 14 below.
As an example of this required timing compensation, the data lines on the motherboard must all be at least 353 pS longer than the clocks.
This rule ensures that the maximum capacitive loading on each driver does not exceed the driver’s specified capacity.
It is important to note that this restriction is an original design limitation. The system may well be capable of successfully driving a longer line. However, Transmeta has not simulated this or designed for it, so violating this rule is done at the designer's risk.
Finally, the clocks traces must be as short as possible. This minimizes potential EMI and signal integrity problems.
Critical RuleA design can have no more than 450 pS of negative skew between the clock (at the SDR SDRAM) and all other inputs.
1.25 nS – 0.80 nS = 0.45 nS
Table 14: Write Timing Compensation
Signal Group Minimum Length Delay as Outer TraceDelay Added to Motherboard
Data 0.60” 92 pS 353 pSData Mask 1.00” 153 pS 292 pSAddress/Control 0.75” 115 pS 330 pSSelect 1.00” 153 pS 292 pSClock Enable 1.00” 153 pS 292 pS
Critical RuleIf 16 SDRAMS are used, the longest trace cannot be more than 5” in length, including the trace on the SODIMM. If the number of SDRAM chips is limited to 12, this maximum trace length can be increased to 8”.
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SDR Memory Design
5.3.4 Read Timing The processor memory controller has no information concerning the distance (and therefore delay) to and from the memory chips, but it must know when to expect valid data that is read from memory. The board designer must communicate this information by providing a carefully calibrated delay loop to resynchronize the data to the clock. The processor CLKOUT and SLKIN signal pins provide this function. The critical components of read timing compensation using CLKOUT and CLKIN are detailed in Figure 11 below.
The delay of the CLKIN line is equal to the round-trip delay of the read command and data. This delay has three components:
• The delay of the clock trace.
• The delay of the shortest data trace.
• A factor to allow for different capacitive loading of the clock and feedback traces, and for capacitive loading of the data trace.
These elements are described as delays, and not as lengths. Signals on the surface of a board travel at a different velocity (~150 pS/in) from the traces inside the board (~180 pS/in), due to the influence of the dielectric constant of the surrounding air.
Note also that these delays are from chip to chip. The trace delay on the SODIMM must be part of this calculation.
Looking at each component of the delay, the first two elements are easily understood. The delay of the clock trace is necessary to account for the timing of the signal to the chip. The delay of the data is needed to account for the return trip. The shortest data line is used to provide sufficient setup time without compromising hold time.
The loading of the clock and data can be quite different, and failure to account for this loading difference will skew the timing. The clock will almost always have four loads, and though actual loads must be determined from the manufacturer specifications, one load is usually about 2-4 pF.
The delay due to clock and data loading is determined by the amount of loading, the drive current, and the termination resistance. Rather than calculate this in each instance, it is often simpler to rely on past experience to determine delay values. Experience has shown these capacitive delays cause a skew of approximately 500 pS. Therefore, a 500 pS delay element must be added to the clock feedback.
Figure 11: Read Timing Compensation
SDRAM Feedback Clock - SD_CLKIN
Rs
SD_CLKIN
ZB ZB ZB
ZB
SD_CLKOUT
RTL0 Delay of Clock Trace
Delay of Shortest Data Trace
Clock Loading
L0MAXMIN
0.00" 1.20"
ZB
Minimum Data LoadingDelay
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SDR Memory Design
5.3.5 Uncertainty in the Feedback Calculation The JEDEC specification is very specific about the layout of the clock trace on the SODIMM, but only gives the total length of the other lines, including data. There will also be some variation of capacitive delays in boards due to geometry, number of vias, etc. There may also be some variation in the actual delays of data and clock lines depending on how well the designer controls the return path integrity.
To address delay variation possibilities, a structure in the CLKIN feedback path that allows for some adjustment of the final configuration is strongly recommended. As shown in Figure 12, zero Ω jumpers can be used to add or remove delays from the line. Testing can be done during the prototyping stage to determine the optimum delay setting. For manufacturing, either the bill-of-materials (BOM) can be selected to give the optimum delay, or the board layout can be revised to remove the unneeded jumpers and delay elements.
5.3.6 Using Soldered-down Memory The previous sections have established the basis for an effective layout of the SDR SDRAM subsystem in a TM5500/TM5800 processor-based system. However, the method discussed requires the use of two SODIMMs. Code Morphing software cannot dynamically configure memory, and if a factory-installed memory module is replaced by a different module, Code Morphing software could fail to load or operate reliably. Another memory solution possibility uses soldered-down memory on the system motherboard. It is often desirable to place one or two banks of memory on the motherboard to provide a minimum system memory configuration and assure that Code Morphing software can always operate in this permanent memory section.
The design approach for soldered-down memory is straightforward. Having established that the two SODIMM design method previously discussed delivers optimal performance, soldered-down memory can be treated from the design perspective as if it was an SODIMM, using exactly the same routing topology used for the all-SODIMM solution. This topology results in a component placement that keeps the SODIMM connector and the on-board SDRAM in close proximity, as shown in Figure 13 and Figure 14.
The layout in Figure 13 is the simplest from a routing perspective. Signals are routed from the processor to the SODIMM connector and then to the on-board SDR SDRAM (passing through any needed termination resistors on the way). If the SODIMM connector is facing the other direction, as shown in Figure 14, the traces are routed from the processor to the connector, then back to the SDR SDRAM chips. In this sub-optimal placement, routing congestion occurs, possibly increasing the number of required board layers.
Figure 12: Adjustment of CLKIN Delay
CLKOUT
CLKIN
RT 0 0
00 00
0
00
Calculated Delay of SCLKIN
250 psec 250 psec 250 psec
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SDR Memory Design
It is possible to place the SODIMM connector as in Figure 13 and avoid routing congestion. Placing the on-board memory on the far side of the SODIMM from the processor yields the optimum routing solution.
Figure 13: Optimum Placement and Routing
Figure 14: Sub-optimal Placement
Crusoe CPU
SODIMM ConnectorTermination ResistorsSoldered-Down SDRAMS(top and bottom)
SODIMM ConnectorTermination Resistors
Soldered-Down SDRAMS(top and bottom)
Crusoe CPU
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SDR Memory Design
The JEDEC specification for SDRAM SODIMMs (JEDEC spec # JC42.5) is used to determine how to lay out the soldered-down memory traces to mimic the structure of an SODIMM. In the JEDEC specification the structure diagrams, with maximum and minimum lengths for each branch, are given for each trace.
These structure diagrams may be substituted into the circuit for each trace. If an advanced CAD software package is used to lay out the board, these branches may be assigned length rules. Routing the board in a manner different from the JEDEC specification will result in design rule violations.
Substituting the one SODIMM on a data line with the equivalent net structure from the JEDEC specification results in the structure shown in Figure 15. Note that this adds a termination resistor to the circuit.
It is important also to note the board impedance of the SODIMM. The JEDEC specification requires a trace impedance of 55 Ω ± 15%. However, the target motherboard may have a different characteristic impedance. The tolerance is unimportant, most board fabricators can easily meet a 10% tolerance at no additional cost.
Termination resistors are sized to match the board impedance to minimize reflections. If a characteristic impedance other than 55 Ω is used, the termination value must be similarly adjusted. Thus for a 60 Ω board, the value of the termination resistor at the memory end of the data line would be increased by five to 15 Ω.
These values are based on a 55 Ω characteristic impedance. If any other board impedance is used, these termination values must be adjusted accordingly using the following formulas.
and
Termination values are given in this document for 60 Ω and 55 Ω boards. If a different impedance is used, all termination impedances must be recalculated.
Figure 15: Data Structure Diagram
ZT = ZS + Z0,
∆ZT = ∆Z0
ZB
ZB
ZB
ZB
ZB
Data - Dual SODIMM
Rs ZB ZB
SODIMMBanks 2,3
SODIMMBanks 0,1
ZB
ZB
Rs ZB ZB
SODIMMBanks 0,1
ZB
JEDEC PC133 SODIMM LAYOUTSEE: JC42.5
TL0 TL1
TL22nd Bank
L0 L1
L2
L3 CONNECTOR
Data - One SODIMM plus On-Board Memory
RT
RTL0 L1
L2
L3
TL2
TL0 TL1 TL2MIN MAX MIN MAX MIN MAX
TOTALMIN MAX
0.10" 0.50" 0.00" 0.90" 0.00" 0.25" 0.60" 1.00"
Rs
Rs
10 ohms
L0 L1 L2MIN MAX MIN MAX MIN MAX
TOTALMIN MAX
0.00" 1.10" 0.00" 4.00" 0.10" 0.40" 0.75" 4.00"
L3MIN MAX
0.10" 0.40"
NOM TOL NOM TOL
RT 28 Ohms 10% 33 ohms 10%
ZB=60 ohmsZB=55 ohms
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SDR Memory Design
The figures below show structure diagrams for each of the remaining SDRAM interface signals.
Figure 16: Address Line Structure Diagram
Figure 17: Clock Line Structure Diagram
ZB
ZB
ZB
Address & Control - Dual SODIMM
Rs ZB ZB
SODIMMBanks 2,3
SODIMMBanks 0,1
ZB
ZB
Rs ZB ZB
SODIMMBanks 0,1
ZB ZB
ZB
ZB
ZB
ZB
ZB ZB
ZB
ZB
ZB
ZB
JEDEC PC133 SODIMM LAYOUTSEE: JC42.5
TL0
TL1 TL2TL3
TL1 TL2
TL3
TL3
TL3
TL3
TL3
TL3
TL3
2nd Bank
2nd Bank
2ndBank
L0 L1
L2
L3 CONNECTOR
TL0 TL1 TL2 TL3MIN MAX MIN MAX MIN MAX MIN MAX
TOTALMIN MAX
0.50" 2.50" 0.00" 1.10" 0.00" 1.00" 0.10" 0.40" 0.75" 4.00"
Address & Control - One SODIMM plus On-Board Memory
RT
RT
L0 L1 L2MIN MAX MIN MAX MIN MAX
TOTALMIN MAX
0.00" 1.10" 0.00" 4.00" 0.10" 0.40" 0.75" 4.00"
L3MIN MAX0.10" 0.40"
NOM TOL NOM TOLRT 28 Ohms 10% 33 ohms 10%
ZB=60 ohmsZB=55 ohms
ZB
ZBZB
ZB
ZB
ZB
ZB
Clock (CLK) - SODIMM
Rs ZB ZB SODIMM
Rs ZB ZB
JEDEC PC133 SODIMM LAYOUTSEE: JC42.5
TL0
TL2
L0 L1
Clock (CLK) - On-Board Memory
RT
RTL0 L1
TL2 ZB
TL3
ZB
TL4
TL4
ZB
TL3
TL4
TL4
One CLK Per Bank
TL1
ZB
TL3
ZB
TL3
TL2 TL3LEN TOL LEN TOL
TOTALMIN MAX
0.80" 0.50" 2.45" 2.55"
TL0 TL1LEN TOL LEN TOL0.10" +/-0.05" 1.00"
TL4LEN TOL0.10" +/-0.05"+/-0.02"+/-0.02"+/-0.02"
NOTE:- All Clocks (0, 1, 2 and 3) are to bematched within 100psec.
INNER
INNER
INNER
INNER
INNER
INNER
INNER
OUTER
OUTER
OUTER
OUTER
OUTER
OUTER
OUTER INNER
INNER
L0 L1MIN MAX MIN MAX
TOTALMIN MAX
0.00" 1.10" 0.00" 4.00" 0.75" 4.00"
NOM TOL NOM TOLRT 5 Ohms 10% 10
ohms 10%
ZB=60 ohmsZB=55 ohms
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SDR Memory Design
Figure 18: Data Mask Structure Diagram
Figure 19: Clock Enable Structure Diagram
ZB
ZB
ZB
ZB
ZB
Data Mask (DQMB) - Dual SODIMM
Rs ZB ZB
SODIMMBanks 2,3
SODIMMBanks 0,1
ZB
ZB
Rs ZB ZB
SODIMMBanks 0,1
JEDEC PC133 SODIMM LAYOUTSEE: JC42.5
TL0
TL12nd Bank
L0 L1
L2
L3 CONN
Data Mask (DQMB) - One SODIMM plus On-Board Memory
RT
RTL0 L1
L2
L3
TL1
TL0 TL1MIN MAX MIN MAX
TOTALMIN MAX
0.75" 1.10" 0.00" 0.30" 1.00" 1.40"
L0 L1 L2MIN MAX MIN MAX MIN MAX
TOTALMIN MAX
0.00" 1.10" 0.00" 4.00" 0.10" 0.40" 0.75" 4.00"
L3MIN MAX
0.10" 0.40"
NOM TOL NOM TOL
RT 5 Ohms 10% 10 ohms 10%
ZB=60 ohmsZB=55 ohms
ZB
ZB
ZB
ZB
ZB
Clock Enable (CKE) - SODIMM
Rs ZB ZB SODIMM
Rs ZB ZB
JEDEC PC133 SODIMM LAYOUTSEE: JC42.5
TL0
TL1
L0 L1
Clock Enable (CKE) - On-Board Memory
RT
RTL0 L1
TL1ZB
TL2
ZB
TL3
ZB
TL3
ZB
TL2
TL3
TL3
TL2 TL3MIN MAX MIN MAX
TOTALMIN MAX
0.00" 1.00" 0.05" 0.35" 1.00" 2.30"
TL0 TL1MIN MAX MIN MAX0.50" 1.10" 0.00" 0.50"
One CKE Per Clock
L0 L1MIN MAX MIN MAX
TOTALMIN MAX
0.00" 1.10" 0.00" 4.00" 0.75" 4.00"
NOM TOL NOM TOLRT 5 Ohms 10% 10 ohms 10%
Z0=60 ohmsZ0=55 ohms
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SDR Memory Design
5.3.7 Recommended Design Procedure 1. Determine the required memory configuration, soldered-down vs. SODIMM.
2. Generate schematics. If soldered-down memory is used, the second resistor for termination of data lines must be added. If an advanced CAD package is used, apply delay rules to memory lines per Table 14. Also, add delay rules to match line lengths within signal groups. Apply structures to soldered-down memory per the JEDEC SODIMM specification.
3. Determine the board stack-up to yield the desired characteristic impedance. Recalculate termination resistor values as needed.
4. Place SDR SDRAM close to the processor (no further than 4” from processor), preferably orthogonal with the processor, center-lines aligned. Place termination resistors as close to their source as possible.
5. Route clock lines, as direct and short as possible, splitting off in equal-length branches at the farthest point (starburst pattern).
6. Route CKEs, selects, data, address and control lines. If delay rules were not added in step 2, match line length within signal groups and add skew-correction values from Table 14.
7. From line length data, calculate the time needed for the CLKIN delay.
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SDR Memory Design
5.3.8 Design Example The design example below assumes there is one bank of x8 memory soldered onto a 55 Ω board. The silicon is placed such that the Manhattan distance from most of the drivers is 4”.
Follow the steps in the Recommended Design Procedure on page 76 to calculate length data to include in the feedback path (CLKIN).
The length of clock on the motherboard is 3.22", routed on internal layers only. The resulting delay is:
The delay on the SODIMM is:
The length of shortest data line on the motherboard is 4.24", half external, half internal. The delay of this line is:
The length of this trace on the SODIMM is 0.6-1.0”. Assume a length of 0.8” on a surface trace. The delay on the SODIMM is:
Using only one bank of x8 parts on the board, both CLK 3 and CLK 2 can be used, ensuring 4 loads per clock. Applying the estimate of 500 pS for clock/data loading delay gives the required delay on CLKIN:
If routed entirely on internal traces, the line length is:
5.4 SDR SDRAM Schematics The following pages show SDR SDRAM reference schematics.
• Single SDR SODIMM (1 page)
• Dual SDR SODIMM (2 pages)
• SMBus isolation circuit (1 page)
• SDR clock enable isolation circuit (1 page)
3.22 in x 180 pS/in = 580 pS
2.50 in x 180 pS/in = 450 pS, for a total of 1030 pS
((4.24"/2) x 180 pS/in) + ((4.24"/2) x 151 pS/in) = 701 pS
0.8 in x 151 pS/in = 121 pS, for a total of 822 pS
1030 pS + 822 pS + 500 pS = 2352 pS
2352 pS / 180 pS/in = 13 in
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilThursday, June 14, 2001 1 1
Single SDR SODIMM3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
PD_SDA13
SDR_DQ4
SDR_A1
SDR_DQ31
SDR_DQ45
SDR_DQ19
SDR_RAS#
SDR_DQ53
SDR_DQ24
SDR_DQ7
SDR_DQM4
SDR_DQ30
SDR_DQM6
SDR_A9
SDR_DQ35
SDR_DQM5
SDR_DQM7
SDR_DQM0
SDR_A3
SDR_DQM2
SDR_DQ16
SDR_CS3#
SDR_DQ50
SDR_DQ21
SDR_DQ55
SDR_A4SDR_A0
SDR_DQ62
SDR_DQ3
SDR_DQ15
SDR_A11
SDR_DQ26 SDR_DQ58
SDR_DQ29
SDR_A5
SDR_DQ6
SDR_DQM3
SDR_DQ63
SDR_DQ9SDR_DQ10
SDR_DQ47
SDR_DQ18
SDR_DQ52
SDR_A10
SDR_DQM1
SDR_DQ12SDR_DQ13
SDR_A7
SDR_DQ38
SDR_DQ17
SDR_DQ23
SDR_A8
SDR_DQ57
SDR_DQ34
SMBCLK
SDR_CKE1
SDR_DQ37
SDR_CKE0
SDR_DQ49
SDR_DQ2
SDR_DQ20
SDR_DQ54
SDR_MWE#
SDR_DQ61
SDR_DQ40SDR_DQ41
SDR_DQ5
SDR_DQ43
SDR_DQ44
SDR_A6
SDR_DQ8
SDR_DQ25
SDR_CS2#
SDR_DQ28 SDR_DQ60
SDR_DQ1
SDR_DQ11
SDR_DQ46
SDR_A12
SDR_DQ51
SDR_DQ33
SDR_CAS#
SDR_DQ0
SDR_A2
SDR_DQ36
SDR_BA0
SDR_DQ22
CLK_SDR2
SDR_DQ56
SDR_DQ27
SDR_DQ32
SDR_DQ14
SDR_DQ59
SMBDATA
SDR_DQ39
SDR_BA1
SDR_DQ48
SDR_DQ42
CLK_SDR3
V3_3_STR
V3_3_STRV3_3_STR
V3_3_STR
V3_3_STR
R122
12
C60.1uF
12
C110.1uF
12
C20.1uF
12
C70.1uF
12
DRAM / SDRAMX64
J1
SODIMM_UP144PIN SODIMM
13579
11131517192123252729313335373941434547495153555759
6163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139141143
24681012141618202224262830323436384042444648505254565860
62646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144
VSSDQ0DQ1DQ2DQ3VDDDQ4DQ5DQ6DQ7VSSDQMB0DQMB1VDDA0A1A2VSSDQ8DQ9DQ10DQ11VDDDQ12DQ13DQ14DQ15VSSNC1NC3
CK0VDDRASWE#S0S1NUVSSNC5NC7VDDDQ16DQ17DQ18DQ19VSSDQ20DQ21DQ22DQ23VDDA6A8VSSA9A10/APVDDDQMB2DQMB3VSSDQ24DQ25DQ26DQ27VDDDQ28DQ29DQ30DQ31VSSSDAVDD
VSSDQ32DQ33DQ34DQ35VDD
DQ36DQ37DQ38DQ39VSS
DQMB4DQMB5
VDDA3A4A5
VSSDQ40DQ41DQ42DQ43VDD
DQ44DQ45DQ46DQ47VSSNC2NC4
CKE0VDDCASCKE1A12A13CK1VSSNC6NC8VDD
DQ48DQ49DQ50DQ51VSS
DQ52DQ53DQ54DQ55VDDA7
BA0VSSBA1A11VDD
DQMB6DQMB7
VSSDQ56DQ57DQ58DQ59VDD
DQ60DQ61DQ62DQ63VSSSCLVDD
C100.1uF
12
C30.1uF
12
C80.1uF
12
C90.1uF
12
C10.1uF
12
C40.1uF
12
C130.1uF
12
C50.1uF
12
C120.1uF
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilThursday, June 14, 2001 1 3
Dual SDR SODIMM (1/2)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
PD_SDA13
SDR_DQ23
SDR_DQ1
SDR_A7
SDR_DQ41
SDR_DQ61
CLK_SDR3
SDR_DQ32
SDR_DQ14
SDR_DQM5
SDR_A3SDR_A0
SDR_A5
SDR_DQ36
SDR_DQ53
SDR_RAS#
SDR_DQ39
SDR_DQ62
SDR_DQ15
SMBDATA_SDR0
SDR_DQM0
SDR_DQ38
SDR_DQ40
SDR_A8
SDR_DQ17
SDR_DQ37
SDR_DQ13 SDR_DQ45SDR_DQ44
SDR_DQ28
SDR_DQ30
SDR_DQM3
SDR_A9
SDR_DQ51
SDR_CAS#
SDR_CS2#
SDR_DQ52
SDR_CKE0
SDR_DQ2
SDR_DQ8
SDR_DQ34
SDR_DQ63
SDR_DQ9
SDR_CS3#
SDR_DQ58
SDR_DQ4
SDR_DQ7
SDR_DQ35
SMBCLK_SDR0
SDR_DQ20SDR_DQ21
SDR_MWE#
SDR_DQ33
SDR_A10
SDR_DQ49
SDR_DQ31
SDR_DQ54
SDR_DQ50
SDR_DQM1
SDR_DQ6
SDR_A1
SDR_DQ0
SDR_DQ22SDR_DQ55
SDR_DQ27
SDR_A2
SDR_DQM4
SDR_A11
SDR_DQ59
SDR_BA0
SDR_DQ11
SDR_DQ48
SDR_DQ43
SDR_A6
SDR_DQ12
SDR_DQ19
SDR_DQ3
SDR_A12
SDR_DQM6
SDR_DQ5
SDR_BA1
SDR_DQ10
SDR_DQ46
SDR_DQ57
CLK_SDR2
SDR_DQ29
SDR_DQ18
SDR_DQM2
SDR_DQ56SDR_DQ25SDR_DQ26
SDR_DQ60
SDR_DQ47
SDR_DQ42
SDR_CKE1
SDR_DQ24
SDR_DQ16
SDR_DQM7
SDR_A4
V3_3_STR
V3_3_STR
V3_3_STRV3_3_STR
V3_3_STR
R122
12
C80.1uF
12
C60.1uF
12
C20.1uF
12
C90.1uF
12
C70.1uF
12
C50.1uF
12
C10.1uF
12
C130.1uF
12
C30.1uF
12
C40.1uF
12
C110.1uF
12
C120.1uF
12
C100.1uF
12
DRAM / SDRAMX64
J1
SODIMM_UP144PIN SODIMM
13579
11131517192123252729313335373941434547495153555759
6163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139141143
24681012141618202224262830323436384042444648505254565860
62646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144
VSSDQ0DQ1DQ2DQ3VDDDQ4DQ5DQ6DQ7VSSDQMB0DQMB1VDDA0A1A2VSSDQ8DQ9DQ10DQ11VDDDQ12DQ13DQ14DQ15VSSNC1NC3
CK0VDDRASWE#S0S1NUVSSNC5NC7VDDDQ16DQ17DQ18DQ19VSSDQ20DQ21DQ22DQ23VDDA6A8VSSA9A10/APVDDDQMB2DQMB3VSSDQ24DQ25DQ26DQ27VDDDQ28DQ29DQ30DQ31VSSSDAVDD
VSSDQ32DQ33DQ34DQ35VDD
DQ36DQ37DQ38DQ39VSS
DQMB4DQMB5
VDDA3A4A5
VSSDQ40DQ41DQ42DQ43VDD
DQ44DQ45DQ46DQ47VSSNC2NC4
CKE0VDDCASCKE1A12A13CK1VSSNC6NC8VDD
DQ48DQ49DQ50DQ51VSS
DQ52DQ53DQ54DQ55VDDA7
BA0VSSBA1A11VDD
DQMB6DQMB7
VSSDQ56DQ57DQ58DQ59VDD
DQ60DQ61DQ62DQ63VSSSCLVDD
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilThursday, June 14, 2001 2 3
Dual SDR SODIMM (2/2)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
PD_SDA13
SDR_DQ61
SDR_DQ44
SDR_DQ33
SDR_DQ30 SDR_DQ62
SDR_A2
SDR_DQ41
SDR_DQ57
SDR_DQ50
SDR_DQM6
SDR_DQ28
SDR_DQ2
SDR_DQ55
SDR_DQ40
SDR_DQ11
SDR_DQ34
SDR_DQ42
SDR_DQ35
SDR_DQ8
SDR_DQ22
SDR_DQ32
SDR_A8
SDR_A0
SDR_DQ46
SDR_DQ53
SDR_DQ19
SMBCLK_SDR1
SDR_DQ63
SDR_DQM3
SDR_DQ21
SDR_CKE1
SDR_CKE0
SDR_DQ27
SDR_BA1
SDR_DQ12
SDR_DQ58
SDR_DQ10
SDR_DQ29
SDR_DQ4
SDR_DQ25
SDR_DQ18
SDR_DQ15
SDR_A10
SDR_DQ23
SDR_A12
SDR_DQM0
SDR_DQ48
SDR_A3
SDR_DQM5
SDR_DQ45
SDR_CS0#SDR_MWE#
SDR_DQ39
SDR_A6
SDR_DQ54
SDR_DQ59
SDR_DQ38
SDR_DQ17
SDR_DQ6
SDR_DQ52
CLK_SDR0
SDR_DQ43
SDR_DQM2
SDR_RAS#
SDR_DQ0
SDR_DQ13
SDR_DQ47
SDR_DQ9
SDR_BA0
SDR_DQ31
SDR_A7
SDR_DQ3
SDR_A5
SDR_DQ37SDR_DQ36
SDR_DQM7
SDR_DQ5
SDR_DQ14
SDR_DQ20
SDR_DQ16
SDR_A11
SDR_DQ7
SDR_A4
SDR_CAS#
SDR_DQ24
SDR_DQ26
SDR_DQM1
SDR_A9
SDR_CS1#
SDR_DQ56
SDR_DQ60
SDR_DQM4
SDR_DQ51
SDR_DQ1
SDR_A1
CLK_SDR1
SMBDATA_SDR1
SDR_DQ49
V3_3_STR
V3_3_STR
V3_3_STRV3_3_STR
V3_3_STR
C240.1uF
12
C170.1uF
12
C250.1uF
12
C230.1uF
12
R222
12
C210.1uF
12
C190.1uF
12
C150.1uF
12
C220.1uF
12
C200.1uF
12
C180.1uF
12
C140.1uF
12
DRAM / SDRAMX64
J2
SODIMM_DN144PIN SODIMM LP REVERSE
13579
11131517192123252729313335373941434547495153555759
6163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139141143
24681012141618202224262830323436384042444648505254565860
62646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144
VSSDQ0DQ1DQ2DQ3VDDDQ4DQ5DQ6DQ7VSSDQMB0DQMB1VDDA0A1A2VSSDQ8DQ9DQ10DQ11VDDDQ12DQ13DQ14DQ15VSSNC1NC3
CK0VDDRASWE#S0S1NUVSSNC5NC7VDDDQ16DQ17DQ18DQ19VSSDQ20DQ21DQ22DQ23VDDA6A8VSSA9A10/APVDDDQMB2DQMB3VSSDQ24DQ25DQ26DQ27VDDDQ28DQ29DQ30DQ31VSSSDAVDD
VSSDQ32DQ33DQ34DQ35VDD
DQ36DQ37DQ38DQ39VSS
DQMB4DQMB5
VDDA3A4A5
VSSDQ40DQ41DQ42DQ43VDD
DQ44DQ45DQ46DQ47VSSNC2NC4
CKE0VDDCASCKE1A12A13CK1VSSNC6NC8VDD
DQ48DQ49DQ50DQ51VSS
DQ52DQ53DQ54DQ55VDDA7
BA0VSSBA1A11VDD
DQMB6DQMB7
VSSDQ56DQ57DQ58DQ59VDD
DQ60DQ61DQ62DQ63VSSSCLVDD
C260.1uF
12
C160.1uF
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
DUAL SDR SODIMM CONFIGURATIONS:
THE SYSTEM NEEDS THE ABILITY TO ISOLATETHE SMBCLK AND SMBDATA TO EACH SDR SODIMM
IN THIS CIRCUIT A 1 BIT BUS SWITCH IS USED INCONJUNCTION WITH AN INVERTER AND A GPIO
TM5800 Design Guide
Custom
ABasilThursday, June 14, 2001 3 3
SMBus Isolation3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
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Date: Author:
Project:
SPD_SELECT#
SPD_SELECT
SMBCLK
SMBDATA_SDR0
SMBCLK_SDR0SMBCLK_SDR1
SMBDATA_SDR1SMBDATA
V3_3
V3_3
U1FST3126FAIRCHILD
1
2 3
4
5 6
7
89
10
1112
13
14
OE1
1A 1B
OE2
2A 2B
GND
3B3A
OE3
4B4A
OE4
VCC
U2A7404
1 2
147
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TWO DISCRETE QUICKSWITCHES ARE USEDTO FACILITATE LAYOUT PLACEMENT.
TM5800 Design Guide
Custom
ABasilThursday, November 29, 2001 1 1
CKE Quickswitch3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
DDR_CKE_MUX1
DDR_CKE_MUX0
AGP_STP#
DDR_CKE0
DDR_CKE1
SUSP_ALI#SUSPEND#
SDR_CKE1
SDR_CKE0
SDR_CKE_MUX1
SDR_CKE_MUX0
V3_3_ALWAYS
V5_0_ALWAYS
V5_0_ALWAYS
U3QS3257QUALITY SEMI
2356
11101413
151
4
7
9
12
16
8
1A1B2A2B3A3B4A4B
GA#/B
1Y
2Y
3Y
4Y
VCC
GND
U27SZ08FAIRCHILD SEMI
1
24
53
R11K
12
C20.1uF
12
C10.1uF
12
R21K
12
U1QS3257QUALITY SEMI
2356
11101413
151
4
7
9
12
16
8
1A1B2A2B3A3B4A4B
GA#/B
1Y
2Y
3Y
4Y
VCC
GND
July 17, 2002
83
C h a p t e r 6
System Design Considerations
6.1 Clocking
The TM5500/TM5800 processor primary clock input (CLK_CPU0) requires a 60 or 66 MHz clock signal. This clock input is compatible with Pentium™ class clock generators. The processor generates the internal processor core clock and the SDRAM clocks for both memory interfaces from the primary clock input.
The processor also expects a PCI clock (CLK_PCI_TM) input of CLK_CPU/2. The phase relationship between the processor and PCI clocks should be such that the CLK_CPU leads CLK_PCI_TM by 3.3 nS (typical). The clock traces (including CLK_CPU and CLK_PCI_TM) from the clock generator to each PCI connector or device should be of equal lengths.
The schematics on the following pages illustrate two possible clock generation circuits. One uses an Integrated Circuit Systems ICS9248-192 clock generator. The other uses an International Microcircuits IMIXG571CYB clock generator. The ICS clock generator solution has a much smaller overall footprint.
NoteFor detailed TM5500/TM5800 processor clock specifications see the Input Clocks section in the Data Book.
A
A
B
B
C
C
D
D
E
E
F
F
1 1
2 2
3 3
4 4
5 5
PULL-DOWN SELECTS 2.5VSWING ON CPU CLOCK.
THE OTHER PCI CLOCKS ARE SYSTEMIMPLEMENTATION SPECIFIC
PULL-DOWN SELECTS 24 MHZ ONUNUSED OUTPUT.
NOTE: CLKPCI0 AND CLKPCI1 SHOULD BECONFIGURED AS FREE RUNNING CLOCKS
TM5800 Design Guide
Custom
ABasilTuesday, February 19, 2002 1 1
ICS Clock Generator3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
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Project:
PU_CKGEN
CLK_R14M
V_CKG25
CLK_RPCI_SB
PD_C
KG24
CLK_RUSB_SB
V_CKG33
CKGX1
CLK_RPCI_TM
CLK_RCPU
CKGX2
CLK_USB_SB
CLK_PCI_TM
SUSA#
CLK_14M
CLK_CPU
CLK_PCI_SBCPU_STP#PCI_STP#
SMBDATASMBCLK
V3_3
V2_5
V3_3
C30.1uF
12
R2 221 2
L1
100Ohms@100MHz
1 2
C20.1uF
12
U1ICS9248-192
18
172124
918
20
25
28
23
4
1314
19
2226
567101112
15
16
23
27GND1GND2GND3GND4GND5
VDD1VDD2
VDD_PLL
VDD_CPU
VDD3
X1X2
PD#
SDATASCLK
SEL66/60#
PCI_STOP#CPU_STOP#
CLKPCI0CLKPCI1CLKPCI2CLKPCI3CLKPCI4CLKPCI5
CLK24_48
CLK48_CPU33/25#
CLKCPU
CLKREF
R710K
12
R110K
12
C40.1uF
12
C50.1uF
12
R810K
12
R5 101 2
+C110uF10V20%
12
R4 331 2
R6 101 2Y114.318 MHZEPSONMA-506-14.318M-C2
1 432
C715pF
12
R3 331 2
L2
100Ohms@100MHz
1 2
C615pF
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
THE PCI CLOCKS ARE SYSTEMIMPLEMENTATION SPECIFIC
SEE THE DESIGN GUIDE FORINFORMATION REGARDING THE USE OFTHE FREE RUNNING PCI CLOCK FORTHE PROCESSOR AND SOUTHBRIDGE
THE SDRAM CLOCKS ARE NOTNEEDED AS THEY ARE PROVIDEDBY THE PROCESSOR
TM5800 Design Guide
Custom
ABasilThursday, January 03, 2002 1 1
IMI Clock Generator3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
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Date: Author:
Project:
XTL_OUT
NC_U1_30
NC_U1_36
NC_U1_29
XTL_IN
U1_P8
NC_U1_35
U1_23
U1_P42
NC_U1_33
U1_P47
U1_2
NC_U1_32
SMBDATA
PCI_STP#
CLK_14M
SUSA#
CLK_USB_SB
CLK_PCI_SB
CLK_CPU
CLK_PCI_TM
SMBCLK
CPU_STP#
V3_3V3_3
V2_5 L268 Ohm
12
L168 Ohm
12
R5 331 2
U1IMIXG571CYBINTL MICROCIRCUITS
45
1920
18
2627
44
6
2147
45
42413938
363533323029
91112131416
8
2223
2548
4640
342821157
3101724313743
XINXOUT
SDATASDCLK
SEL
PCI_STOPCPU_STOP
PWR_DWN
MODE
REF0REF1REF2
IOAPIC0
CPUCLK0CPUCLK1CPUCLK2CPUCLK3
SDRAM0SDRAM1SDRAM2SDRAM3SDRAM4SDRAM5
PCICLK0PCICLK1PCICLK2PCICLK3PCICLK4PCICLK5
PCICLK_F
48_24MHZ148_24MHZ2
VDDVDD
VDDQ2VDDQ2
VDDQ3VDDQ3VDDQ3VDDQ3VDDQ3
VSSVSSVSSVSSVSSVSSVSS
C80.1uF
12
R2 221 2
C70.1uF
12
C60.1uF
12
C50.1uF
12
C40.1uF
12
R14.7K
12
C1215pF
12
R3 101 2
C30.1uF
12
C20.1uF
12
+
C910uF10V20%
12
R81K
12
C110.1uF
12
C100.1uF
12
+
C110uF10V20%
12
R6 101 2
C1315pF
12
R4 331 2
R74.7K
12
Y114.318 MHZEPSONMA-506-14.318M-C2
1 432
July 17, 2002
86
System Design Considerations
6.2 System Reset TM5500/TM5800 processors require the reset connections shown below for proper operation. This allows the Transmeta Debug Module (TDM) to assert JTAG reset and RESET# (needed for some debugging functions) without asserting PCI_RST#. A system-level PCI reset will also assert JTAG_TRST# and RESET#, which is needed for normal operation.
Figure 20: System Reset Diagram
NoteDuring system power-up, TM5500/TM5800 processors drive the P_PCI_RST# pin invalid (high) when V3_3 (3.3 V I/O power supply) is powered and V_CPU_CORE (processor core supply) is not powered. In some systems the southbridge can also be driving PCI_RESET# valid (low) during this time period, creating a conflict if these signals are directly tied together. The 10 KΩ resistor in the circuit above prevents the processor P_PCI_RST# high-level output signal during power-up from driving against the southbridge PCI_RESET# signal.
TDM_TRST#
TDM_RST#
PCI_RST#
TRST#
RESET#
P_PCI_RST#
TM5x00
G9
H19
E8
4.7K 1.2K
10K
July 17, 2002
87
System Design Considerations
6.3 Signal Pull-ups and Pull-downs The following signals should be pulled up to V2_5: IGNNE#, INTR, INIT#, NMI, FERR#, and SMI#.
During the Deep Sleep power management state, the processor clock is stopped and most I/O pins are tri-stated (see the ACPI specification). Care must be taken to ensure that all signals going to sections of the system that are powered on during suspend must be pulled up/down to a valid state when the processor tri-states its outputs.
Specifically, PCI_GNT# and other PCI control signals are most important, so that the PCI agent is not confused when the grant lines float low.
TM5500/TM5800 processor signals should be pulled up or down as shown in the table below. Many of these signals are outputs from the processor, and all non-DRAM processor outputs are tri-stated (float) during Deep Sleep.
Table 15: Signal Pull-up/Pull-down Requirements
Processor Signal Pull-up / Pull-down ResistorValue / ConfigurationName Pin Number Type
FERR# H16 Output 10 KΩ pull-up to V2_5IGNNE# H15 InputINIT# G18 InputINTR G19 InputNMI H17 InputSMI# G14 InputSTPCLK# H18 InputEPROMA[0] J16 Output None (test point only)EPROMA[1] J15 Outputs 10 KΩ pull-up to V3_3EPROMA[2] J19 OutputP_CLKRUN# J18 BidirectionalP_GNT#[0] G15 OutputP_GNT#[1] A16 OutputP_GNT#[2] F13 OutputP_GNT#[3] A15 OutputP_GNT#[4] G16 OutputP_GNT#[5] F17 OutputP_HOLDA# E13 OutputSROM_CS#[0] K15 Output
SROM_CS#[1] 1 L15 Output
TCK W7 InputSROM_SCLK L16 Output 10 KΩ pull-up to V3_3 -or-
10 KΩ pull-down to groundSROM_SOUT K18 OutputCFG_SDATA A8 Bidirectional 1.2 KΩ pull-up to V3_3 -or-
4.7 KΩ pull-down to ground 2
July 17, 2002
88
System Design Considerations
CFG_SCLK 3 B7 Output 10 KΩ pull-down to ground
DEBUG_INT H14 InputDEBUG_NMI W11 Input
SROM_SIN 3 K17 Input
Reserved and No Connection SignalsRSV_F7 F7 - 10 KΩ pull-up to V3_3RSV_G1 G1 -RSV_H5 H5 -RSV_H6 H6 -RSV_V1 V1 -RSV_V2 V2 -RSV_V3 V3 -RSV_W6 W6 -RSV_E7 E7 - 4.7 KΩ pull-down to groundRSV_G13 G13 -
RSV_G2 4 G2 - 10 KΩ pull-down to ground
RSV D7 - None (test point only)RSV G11 -RSV J4 -RSV J5 -RSV R1 -RSV R2 -RSV R4 -RSV T5 -RSV AE19 -RSV K3 - No connectionRSV K4 -RSV K5 -RSV L5 -
1. During C3, all processor outputs are tri-stated. It is important to pull up SROM_CS#[1] to avoid the possibility of asserting serial ROM chip select.
2. When no mode-bit ROM is populated: use pull-up on CFG_SDATA to force Code Morphing software to boot from serial flash ROM, use pull-down on CFG_SDATA to force Code Morphing software to boot from parallel flash ROM.
3. May be pulled up or down. The recommended action is a pull-down, since the processor normally holds this signal low when idle. The goal is to prevent the signal from floating during C3.
4. If pin G2 is being used to unprotect the parallel ROM through a +12 V switch circuit, then it needs a pull-down. If the pin is not used, either a pull-up or pull-down is OK. Since the pin powers up as an input, the goal is to prevent the signal from floating.
Table 15: Signal Pull-up/Pull-down Requirements (Continued)
Processor Signal Pull-up / Pull-down ResistorValue / ConfigurationName Pin Number Type
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System Design Considerations
6.4 Mode-bit ROM
TM5500/TM5800 processors use a 2-wire serial interface to download the configuration mode-bits from this device at boot-up. The configuration mode-bits instruct the processor on several important boot and initialization options. The contents of the mode-bit ROM are read into the processor at power-on, configuring the processor to begin execution with optimal performance timings over a large range of system operating configurations.
Use of the external mode-bit ROM is required for guaranteed operation of all production parts. For more information, see the Development and Manufacturing Guide section Mode-Bit ROM Settings.
Currently, the only Transmeta-approved configuration mode-bit ROMs are:
• Microchip Semiconductor 93LC56B (128 x 16, 2 Kbit serial flash ROM).
• STMicro M93C56-WMN6 (128 x 16, 2 Kbit serial flash ROM).
The configuration mode-bit ROM is powered from V3_3.
The schematic on the following page illustrates the configuration mode-bit ROM circuit.
NoteAn external 2 Kbit mode-bit ROM is required for all TM5500/TM5800 processor-based systems.
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
2Kb SROM
TM5800 Design Guide
Custom
ABasilFriday, October 26, 2001 1 1
Modebit ROM3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
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Document Number:
Size:
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Date: Author:
Project:
DO_U1NC_U1_6
NC_U1_7CFG_CLKPCI_RST#
TDM_CFG_CS
TDM_CFG_CLK
TDM_CFG_DATA
CFG_DATA
V3_3
R1 4701 2
R4 4701 2
R510K
12
U193LC56B-1/SN
12
36
7
4
8
5
CSSK
DIPE
PRE
DO
VCC
VSS
TP1
C10.1uF
12
TP2
R2 3312R3 4701 2
July 17, 2002
91
System Design Considerations
6.5 Code Morphing Software ROM TM5500/TM5800 processors use a combination of hardware and software to create an x86-compatible processor. A memory device of at least 1 MByte is required for storing Code Morphing software in compressed form prior to decompression and loading into RAM. There are two basic approaches to storing Code Morphing software: in a serial flash ROM, or combined together with the system BIOS into a parallel ROM. These two Code Morphing software ROM configurations are described below.
6.5.1 Serial Flash ROM Interface Code Morphing software can be optionally stored in its own 8 Mbit (1 Mbyte) serial flash ROM. The SROM interface has all the signals needed to interface to Atmel serial flash ROM devices. Atmel provides up to 8 Mbit devices for which only one chip select is needed. The serial flash ROM uses the V3_3 power supply because it must be powered off when the processor is off.
The schematic on the following page illustrates a serial Code Morphing software flash ROM circuit.
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
CMS SerialFLASH ROM
SERIAL WRITEPROTECT DEVICE
SROM_WP IS A GPIO,MUST BE 3.3V IO
28 PIN TSOP PACKAGE PINOUT
TM5800 Design Guide
Custom
ABasilThursday, June 14, 2001 1 1
CMS Serial Flash ROM3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
U2_P3
SROM_CSOUT#
U2_P11U2_P13
U2_P12
TDM_SROM_CS0#
TDM_SROM_CLK
SROM_SOUT
SROM_CS0#
SROM_SCLK
SROM_SIN
SROM_WP
TDM_SROM_OUT
PCI_RST#
V3_3
V3_3 V3_3
V3_3 V3_3 V3_3 V3_3
R510K
12
R210K
12
R310K
12
R8 2201 2
R410K
12
R110K
12
U2
ATMELAT45DB081A-TI
121113
32
1
146
7
4589101516171819202122232425262728
SCLKCSSI
WPRESET
RDY/BUSY#
SOVCC
GND
NC_4NC_5NC_8NC_9
NC_10NC_15NC_16NC_17NC_18NC_19NC_20NC_21NC_22NC_23NC_24NC_25NC_26NC_27NC_28
U1
ATMELATF22LV10CZ
123456789
1011
12
13
14151617181920212223
24
I1/CLKI2I3I4/PDI5I6I7I8I9I10I11
GND
I12
I/O1I/O2I/O3I/O4I/O5I/O6I/O7I/O8I/O9
I/O10
VCC
R7 2201 2R6 2201 2
July 17, 2002
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System Design Considerations
6.5.2 Serial Flash ROM Write Protection Circuit The serial flash ROM used with TM5500/TM5800 processors does not provide a secure mechanism for protecting the contents from accidental erasure or accidental writes. This creates a potential risk for the serial flash ROM to be inadvertently erased or modified in-system, which affects the Code Morphing software boot image stored in that ROM. Therefore, to ensure a high level of system security and integrity, Transmeta requires a special write protection circuit for the serial flash ROM. Systems using a parallel ROM to store the Code Morphing software boot image do not have this risk and do not require this write protection circuit.
The write protection circuit uses a 22LV10 PLD to filter the chip select signals from the processor to the ROM. The PLD intercepts write cycles to the ROM when writes are not authorized. A southbridge GPIO pin signals the PLD when writes are authorized. The features of this circuit are:
• It provides security.
• It fully write protects the entire serial flash ROM.
• It ensures that the Code Morphing software boot image is not accidentally overwritten.
• It allows for field upgrades of Code Morphing software should they be needed.
6.5.2.1 Circuit Operation
The write protection PLD works by gating the chip select signal to the serial ROM when a write or erase command is detected. The device has an input pin (named WP) to enable and disable this feature. When WP is asserted, write and erase commands are not allowed to complete. When WP is negated, write and erase commands function normally. Read commands are always unaffected by the PLD.
The polarity of the WP input is selectable with another input pin (named WPNEG). When WPNEG is pulled up, the WP input is active-low. When WPNEG is pulled down, the WP input is active-high. WPNEG should be pulled up if the signal driving the WP input powers up in the low state. WPNEG should be pulled down if the signal powers up in the high state.
The PLD also has an input pin (named SEL) to select the type of serial ROM in use. The SEL pin should be pulled down for the Atmel flash device, which is the only device currently supported.
NoteFor JEDEC source code and CUPL source code, see Appendix B, Serial Write-protection PLD Data.
NoteDue to a potential race condition, do not use an ATF22LV10C part for this application.
July 17, 2002
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System Design Considerations
6.5.2.2 PLD Pinout
The full pinout of the PLD is described in the following table:
6.5.2.3 PLD Device Selection
The following should be considered when selecting a PLD device to implement the write protection circuit:
• Package. The state machine in the PLD design is very simple, and it could fit into a very small device. However, an asynchronous flip-flop reset is absolutely necessary for this PLD design to function, and the smallest PLD with this feature is a 22LV10. For tightly constrained board layouts, Atmel makes a 22LV10 in a 24-pin TSSOP. The Atmel part number is ATF22LV10CZ, and the device’s pinout and fuse map are the same as in a standard DIP 22LV10.
• Propagation delay. Transmeta successfully tested a part with a 15 ns propagation delay. Although a slower part may work, Transmeta cannot guarantee it because a slower part was not tested.
• Voltage. The PLD must have 3.3 V outputs because the serial flash ROM is not 5 V-tolerant.
• Power. Since the standard 22LV10 draws at least 70-90 mA from 3.3 V, Transmeta recommends a part with a power saving feature be used. Many vendors sell 22LV10 parts with power saving features. Transmeta recommends the Atmel ATF22LV10CZ.
Table 16: PLD Pinout
TSSOP Pin Number Signal Name Signal Description1 CKIN Serial flash clock input2 WP Write protect input3 DIN Serial flash data input4 PD Power-down pin, implied by device selection5 CS0IN# Serial flash 0 chip select input6 CS1IN# Serial flash 1 chip select input (tie high if unused)7 WPNEG Write protect negate input:
Low = WP is active-highHigh = WP is active-low
8 SEL Select serial flash interface input:Low = Atmel
9, 10, 11 - Unused inputs, tied to ground12 GND Device ground13 - Unused input, tied to ground14, 15, 16 - Unused tri-stated outputs, tied to ground17 CS0OUT# Serial flash 0 chip select output18, 19 - Reserved, no connects20, 21, 22 - Unused tri-stated outputs, tied to ground23 CS1OUT# Serial flash 1 chip select output (no connect if unused)24 VCC Device power - connect to 3.3 V
NoteDue to a potential race condition, do not use an ATF22LV10C part for this application.
July 17, 2002
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System Design Considerations
6.5.2.4 Schematic
The schematic below shows the serial flash ROM write-protection PLD circuit.
Figure 21: Schematic Diagram of Serial Flash Write-protection PLD in System
SROM_CS0#SROM_CS1#SROM_SCLKSROM_SOUTSROM_SIN
WPWPNEGSEL
CS0IN#CS1IN#CLKDIN
CS0OUT#CS1OUT#
CLKDIN
CS#
DOUT
SROM_SIN
SROM_CS0#SROM_CS1#SROM_SCLKSROM_SOUT
3.3V
GPIO
3.3VSouth Bridge
Crusoe
ATF22LV10CZ
Debug Connector
Atmel 1MBSerial Flash
WP pull-up is in case GPIOpowers up as an input
If GPIO powers up low, tieWPNEG high and change WPpull-up to a pull-down.
Tie all unused pins on PLD toeither 3.3V or GND.
All resistors shown are 220 Ω.
Notes:
July 17, 2002
96
System Design Considerations
6.5.3 Combined BIOS/CMS Parallel ROM Interface TM5500/TM5800 processors support use of the BIOS parallel ROM memory for Code Morphing Software (CMS) storage, thus eliminating the need for a 1 MByte serial Flash ROM to store Code Morphing software.
This is accomplished by connecting the processor EPROMA[2:1] signals to the highest-order address bits of a 2 MByte parallel flash ROM, in the usual way for a system BIOS interface (Xbus or similar). Code Morphing software is stored in the lower ¾ of the ROM, and the upper ¼ is used for the system BIOS. The processor controls the EPROMA[2:1] signals during Code Morphing software decompression, and then sets EPROMA[2:1] to 11b to enable access to the x86 BIOS code.
There is an important security issue arising from the use of a parallel ROM for Code Morphing software that must be addressed by the system designer. This issue relates to the use of JEDEC flash ROMs that have an erase-all command that erases all unprotected sectors in the ROM. This allows the possibility for x86 software (applications or viruses) to erase the entire ROM, including the Code Morphing software portion.
To protect against unauthorized Code Morphing software erasure, the Code Morphing software sectors of the ROM should be protected by enabling the ROM sector protection feature. The ROM sector protection feature is enabled by the ROM programming equipment at the OEM manufacturing site.
JEDEC flash ROMs have a temporary sector unprotection method that involves raising the reset pin of the ROM to +12 V. This method is used for Code Morphing software field upgrades. A pin on the processor (not accessible by x86 code) is used to control the temporary unprotect ROM feature during the upgrade process.
Future versions of parallel ROMs may allow the erase-all feature to be disabled, and some may also support software programmable protection of sectors. These enhancements eliminate the need for this protection circuit.
For debugging purposes, retain the serial flash connections to the Transmeta Debug Module (TDM) interface. The TDM has built-in serial flash and allows developers to boot from the TDM-based flash device.
The schematic on the following page illustrates a combined BIOS and Code Morphing software parallel flash ROM circuit.
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
IF BIOS_BSY# SIGNAL IS USED,CONNECT TO GPI OF SOUTHBRIDGEOR OTHER DEVICE.
If used for System BIOS only, install 512K (or 256K).If used for System BIOS and CMS, install 2M.In TM5X00 systems, the lower 3/4 of the ROM are protected and unable to be erased (i.e. by an 'erase all' command to the ROM). The unprotectcircuit allows CMS to reprogram protected sectors during a CMS upgrade (TM5X00 only). Note how EPROMA[2..1] signals are connected to the 2MB ROM. These signals act as bank selects to select either CMS sectors or BIOS. When CMS has decompressed and is ready to run x86 code, these signalsselect the highest bank (11) to allow access to the BIOS code.
SB_GPIO_A CAN BE USED TO ALLOWBIOS TO GATE WRITES TO THEPARALLEL ROM.
SB_GPIO_B IS USED TOENABLE/DISABLE APPLICATION OF12V TO THE PARALLEL ROM.
TM5800 Design Guide
Custom
ABasilTuesday, November 27, 2001 1 1
Parallel ROM with CMS Option3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
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Project:
SA11
SA1
SA15
SA0
XD6
BIOS_RST#
UNPROTECT_S
SA9
XD4
SA7
XD5
SA12
SA10
XD0
SA8
UNPROTECT_R
XD7
SA5SA4
SA14SA13
XD2
ROM_WE#
XD1
XD3
SA2
SA18
SA16
RST_CTL
SA17
SA6
SA3
SB_GPIO_B
EPROMA2
PCI_RST#
MEMR#ROMCS#
EPROMA1
MEMW#
SB_GPIO_A
SB_GPIO_C#
SA[18..0]
XD[7..0]
V5_0
V3_3
V5_0
V3_3
V5_0
V12_0
R5 10K1 2
R34.7K
1 2
C11000pF
12
C20.1uF
12
D1BAT54C
1
2 3
Q2IRLML2402INTL RECTIFIER
1
23
R410K
12
R610K
12
Q1IRLML6302INTL RECTIFIER
1
23
R110K
12
C3
0.1uF
12
R710K
12
R90
NI
1 2
U17SZ32
1
24
53
R810
12
X129F160TP-70PFTNFUJITSU
252423222120191887654321
481716
1226
11
28
2931333538404244
15
30323436394143
45
37
4627
47
9
14
1013
A0A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18
RESET#CE#
WE#
OE#
DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7
RY/BY#
DQ8DQ9
DQ10DQ11DQ12DQ13DQ14
DQ15/A-1
VCC
GNDGND
BYTE#
A19
NC_14
NC_10NC_13
R21K
12
July 17, 2002
98
System Design Considerations
6.6 Southbridge
6.6.1 Qualified Southbridge Devices The Acer ALI M1535 southbridge has been fully qualified by Transmeta for use with TM5500/TM5800 processors, and is the recommended southbridge solution. Other PCI-interface southbridge devices can also be used with TM5500/TM5800 processors. Contact your Transmeta representative for qualification status of other southbridge devices.
6.6.2 Using CLKRUN Refer to the following figure for the recommended CLKRUN implementation.
6.6.3 Southbridge Schematics The schematic diagrams on the following four pages illustrate the southbridge circuit using the ALI M1535.
Figure 22: Recommended CLKRUN Circuit
TM5x00
southbridgeclock generator
PCICLK_F
PCICLK0
PCICLK
CLKRUN#
PCI_STP#
PCI_STP#
P_PCLKP_CLKRUN#CLKRUN#from PCI devices
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
NOTE: THIS SCHEMATIC IS FOR THE ALI 1535 SOUTHBRIDGEONLY. SEE THE VENDOR DOCUMENTATION FOR ALI 1535+ ANDOTHER SOUTHBRIDGE DIFFERENCES.
TM5800 Design Guide
Custom
ABasilTuesday, December 04, 2001 1 4
ALi 1535 Southbridge (1/4)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
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Date: Author:
Project:
PCI_AD23
PCI_AD7
PCI_AD30
PCI_AD28
PCI_AD0
PCI_AD31
PCI_AD22
PCI_AD3
PCI_AD6
PCI_AD10
PCI_AD20
PCI_AD12
PCI_AD17
PCI_AD8
PCI_AD26
PCI_AD11
PCI_AD1
PCI_AD13
PCI_AD29
PCI_AD18
PCI_AD21
PCI_AD4
PCI_AD25
PCI_AD2
PCI_AD5
PCI_AD14
PCI_AD19
PCI_AD16
PCI_AD24
PCI_AD9
PCI_AD15
PCI_AD27
PCI_IRDY#
PCI_INTB#
PCI_CBE1#
CLK_PCI_SB
PCI_INTC#
PCI_TRDY#
PCI_AD[31..0]
PCI_CBE0#
PCI_SERR#
PCI_INTE#
PCI_HLD#
PCI_FRAME#
PCI_INTD#
PCI_HLDA#
PCI_DEVSEL#
PCI_CBE3#
PCI_INTA#
PCI_STOP#
PCI_RST#
PCI_INTF#
PCI_CBE2#
PCI_PAR
(Part 1 of 4)
PCI
IDE
Symbol ver 1
U1AM1535ALI
C5
G2F1F2F3E1E2E3D1D3C1B1A1C2B2A2C3E6D6C6B6A6E7D7C7A7D8C8B8A8C9B9A9
B3A5B7
A3
C4D4
A4
D5
B5
F4F5G3G4G5H4
A10
C11
G18G16F19F17E20E18D19C20B20D18D20E19F16F18F20G17
J16H19H20J18J17
G19 H18
H17 H16G20
B17E16C16A16D15B15E14D13E13D14A15C15E15B16D16A17
B19C18A19A20
A18
E17D17
D2
B18
C17
C19
B4
E8
N16
P16
PCIRST#
AD31AD30AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10AD9AD8AD7AD6AD5AD4AD3AD2AD1AD0
C_BE2#C_BE1#C_BE0#
FRAME#
TRDY#IRDY#
STOP#
SERR#
PAR
INTA#/M1INTB#/S0INTC#/S1/GPI27INTD#/S2/GPI28INTE#/GPI29INTF#/GPI30/MOTOR_ON#
PHLDA#
PHOLD#
PIDED15PIDED14PIDED13PIDED12PIDED11PIDED10PIDED9PIDED8PIDED7PIDED6PIDED5PIDED4PIDED3PIDED2PIDED1PIDED0
PIDEA2PIDEA1PIDEA0
PIDECS3#PIDECS1#
PIDEDRQ PIDEDAK#
PIDERDY PIDEIOR#PIDEIOW#
SIDED15SIDED14SIDED13SIDED12SIDED11SIDED10SIDED9SIDED8SIDED7SIDED6SIDED5SIDED4SIDED3SIDED2SIDED1SIDED0
SIDEA2SIDEA1SIDEA0
SIDECS3#
SIDERDY
SIDEIOR#SIDEIOW#
C_BE3#
SIDEDAK#
SIDEDRQ
SIDECS1#
DEVSEL#
PCICLK
SIRQI
SIRQII
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
NOTE: THIS SCHEMATIC IS FOR THE ALI 1535 SOUTHBRIDGEONLY. SEE THE VENDOR DOCUMENTATION FOR ALI 1535+ ANDOTHER SOUTHBRIDGE DIFFERENCES.
NOTE: THE SOUTHBRIDGE SIGNALCPU_RST# IS NOT REQUIRED BY THE CPU.
TM5800 Design Guide
Custom
ABasilTuesday, December 04, 2001 2 4
ALi 1535 Southbridge (2/4)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
SA0
SA8
SA10
XD4
SA12
XD7
XD2SA6
SA1
XD5
XD3
SA3XD6
SA15
SA11
XD0
SA14
SA9XD1
SA18
SA16SA17
SA5
SA2
SA4
SA13
SA7
SUSC#
SUSP_ALI#
MEMR#
THRM#
SA[18..0]
CPU_SMI#
PCIREQ#
CPU_NMI
CPU_STPCLK#
MEMW#
CPU_STP#
CPU_FERR#
RSM_RST#
CPU_INTR
CPU_IGNNE#
CLK_14M
PWRGOOD
SUSA#SUSB#
PCI_STP#
ROMCS#
CPU_INIT#
XD[7..0]
CLK_USB_SB
PCI_CLKRUN#
AGP_STP#
V2_5 V2_5 V3_3V3_3 V5_0
X Bus
Power Control
CPU Sideband
USB
RTC
(Part 2 of 4)
U1BM1535ALI
T15U15V15W15T16U16V16W16Y16R17T17U17V17W17Y17V18W18Y18V19
N17
T14U14
T13U13
T20
R20
R19R18
D10
W6Y6
V13
P20R16
U6
U5
T6
T5
T8U8
V7W7
U9
V8W8
H5
Y7
W19Y19V20W20Y20U18U19U20
V9
B13C14B12C12A13C13A14B14D12
V14W14Y14T9
C10B10W13A11D9Y13
E11
A12
W10U10
Y15V10
W11Y11Y10
W12V11
Y12
B11
T18
E12D11
N19
N18
M17
V6
BIOSA18/GPO24/CLK_OFF#BIOSA17/GPO25BIOSA16/GPO26
SA15/SD15/EGPIO15/EEGPIO15SA14/SD14/EGPIO14/EEGPIO14SA13/SD13/EGPIO13/EEGPIO13SA12/SD12/EGPIO12/EEGPIO12SA11/SD11/EGPIO11/EEGPIO11SA10/SD10/EGPIO10/EEGPIO10
SA9/SD9/EGPIO9/EEGPIO9SA8/SD8/EGPIO8/EEGPIO8
SA7/RUN_ENT23/EGPIO7/ERUN_ENT23/EEGPIO7SA6/RUN_ENT22/EGPIO6/ERUN_ENT22/EEGPIO6SA5/RUN_ENT21/EGPIO5/ERUN_ENT21/EEGPIO5SA4/RUN_ENT20/EGPIO4/ERUN_ENT20/EEGPIO4
SA3/LAD3/RUN_ENT19/EGPIO3/ERUN_ENT19/EEGPIO3SA2/LAD2/RUN_ENT18/EGPIO2/ERUN_ENT18/EE3GPIO2SA1/LAD1/RUN_ENT17/EGPIO1/ERUN_ENT17/EEGPIO1SA0/LAD0/RUN_ENT16/EGPIO0/ERUN_ENT16/EEGPIO0
PCS2#/BIOSA19/GPO29
MEMR#MEMW#
IOR#/GPO27IOW#/GPO28
ROMKBCS#
RTCAS
RTCRWRTCDS
OSC14M
OSC32KIOSC32KII
CLK32KO
PCS0#/GPO31PCS1#/CVROFF/RUN_ENT6/GPIO6
OVCR3#/DEC_CCFT/GPIO23
OVCR2#/INC_CCFT/GPIO22
OVCR1#/SEL_MODE1/GPIO21
OVCR0#/SEL_MODE0/GPIO20
USBP3-/RSM_ENT6/GPI35/GPO42USBP3+/RSM_ENT7/GPI36/GPO43
USBP2-/RSM_ENT4/GPI33/GPO40USBP2+/RSM_ENT5/GPI34/GPO41
USBP1+
USBP0-USBP0+
USBCLK
USBP1-
XD7XD6XD5XD4XD3XD2XD1XD0
USB_PWREN#/RSM_ENT2/GPI31/GPO38
CPURST#INIT#INTRNMI
SMI#IGNNE#A20M#
STPCLK#SLEEP#/GPO32
OFF_PWR0#/GPO36OFF_PWR1#/GPO37
OFF_PWR2#OFF_CDPWR#/RSM_ENT3/GPI32/GPO39
CPU_STP#/GPO44PCI_STP#SUSPEND#
CLKRUN#/GPIO20SLOWDOWN/GPIO21
SPLED
AGP_STP#/GPO33/CBLID_S
FERR#/IRQ13I
RSM_RST#PWG
PWRBTN#SLPBTN#
LB#/RSM_ENT0LLB#/RSM_ENT1ACPWR/RSM_ENT8
PME#RI#
IRQ8#
PCIREQ#
THRM#
ZZ/RATIO#AGP_BUSY#/GPI26/CBLID_P
IRQSER
AEN/GPO30
IOCHRDY/GPI24
SQWO
RN2C
10K
36
R310K
12
R410K
12
R110K
12
R12
10K
12
RN1A
10K
18
R510K
12
RN1B
10K
27
R610
K1
2
RN2D
10K
45
RN2A
10K
18
R210K
12
RN1C
10K
36
RN2B
10K
27
RN1D
10K
45
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
SYMBOL PROVIDED FORCUSTOMERS WHO LEVERAGETHE DESIGN GUIDESCHEMATICS
NOTE: THIS SCHEMATIC IS FOR THE ALI 1535 SOUTHBRIDGEONLY. SEE THE VENDOR DOCUMENTATION FOR ALI 1535+ ANDOTHER SOUTHBRIDGE DIFFERENCES.
TM5800 Design Guide
Custom
ABasilFriday, November 30, 2001 3 4
ALi 1535 Southbridge (3/4)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
PCIREQ_A#REQ0_1_2REQ0_1_2_3_4
PCI_REQ4#
PCIREQ#
PCI_REQ5#
PCI_REQ3#
PCI_REQ0#
PCI_REQ2#PCI_REQ1#
V3_3 V3_3 V3_3 V3_3
C10.1uF
12
R710K
12
U4C74LCX11FAIRCHILD SEMI
91011
8
147
U4A74LCX11FAIRCHILD SEMI
12
1312
147
Infrared
Keyboard & Mouse
Floppy
Serial Ports
Parallel Port
Audio
(Part 3 of 4)
U3CM1535ALI
J19
J20L20M16
K18K17K20K19
M20
L17L16M19L18L19
M18
U2R5U3
V1V2V3W1W2W3Y1Y2
T4 R4
W9Y8
Y9P5
P4U1
J2G1H3J4
J3H1J5H2
L1J1K5K1
L2K3K2K4
T19
P2P3N1N2N3N4N5M2
T1
L5
M5
M3
M4P1R3R2
R1
T12T11
V12U12U11
M1L3L4
DENSEL/EGPIO14
INDEX#/EGPIO13TRK0#/EGPIO12WPROT#/EGPIO11
MOT1#/EGPIO10MOT0#/EGPIO9DRV1#/EGPIO8
DRV0#/RUN_ENT23/EGPIO7
DSKCHG#/RUN_ENT22/EGPIO6
STEP#/RUN_ENT21/EGPIO5FD_DIR#/RUN_ENT20/EGPIO4HDSEL#/RUN_ENT19/EGPIO3WDATA#/RUN_ENT18/EGPIO2WGATE#/RUN_ENT17/EGPIO1
RDATA#/RUN_ENT16/EGPIO0
ACGP_MUTE#/RUN_ENT13/GPIO13ACGP_DOWN#/RUNENT12/GPIO12ACGP_UP#/RUN_ENT11/GPIO11
ACGAME0ACGAME1ACGAME2/GPIO16ACGAME3/GPIO17ACGAME4ACGAME5ACGAME6/GPIO18ACGAME7/GPIO19
ACMIDI_RXD ACMIDI_TXD
ACSDATA_IN0ACSDATA_IN1
ACRESET#ACBIT_CLK
ACSYNCACSDATA_OUT
RI1#DCD1#DSR1#CTS1#
DTR1#RTS1#/CONFIG
SOUT1SIN1
RI2#/RUN_ENT15/GPIO15DCD2#/RUN_ENT14/GPIO14DSR2#/RUN_ENT13/GPIO13CTS2#/RUN_ENT12/GPIO12
DTR2#/RUN_ENT11/GPIO11RTS2#/RUN_ENT10/GPIO10
SOUT2/RUN_ENT9/GPIO9SIN2/RUN_ENT8/GPIO8
SPKR
PD0PD1PD2PD3PD4PD5PD6PD7
ERROR#
SLCT
PE
PRNACK#
BUSYSTROB#
SLCTIN#PRINIT#
AUTOFD#
MSDATA/IRQ12IMSCLK/FPVEE
KBINH/IRQ1IKBDATA/CCFT
KBCLK/DISPLAY
IRTXIRRXIRRXH
U4B74LCX11FAIRCHILD SEMI
345
6
147
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
NOTE: THIS SCHEMATIC IS FOR THE ALI 1535 SOUTHBRIDGEONLY. SEE THE VENDOR DOCUMENTATION FOR ALI 1535+ ANDOTHER SOUTHBRIDGE DIFFERENCES.
TM5800 Design Guide
Custom
ABasilFriday, November 30, 2001 4 4
ALi 1535 Southbridge (4/4)3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
TEST#
SMB_ALERT#
SMBDATASMBCLK
V3_3 V5_0V5_0_ALWAYSV3_3_ALWAYS V3_3V2_5V5_0
C70.
1uF
12
C11
0.1uF
12
R81K
12
R910
K1
2
C30.
1uF
12
C10
0.1uF
12
C50.1uF
12
C60.1uF
12
R10
10K
12
C12
0.1uF
12
C20.1uF
12
C90.
1uF
12
C40.1uF
12
(Part 4 of 4)
Power & Ground
Miscellaneous
U1DM1535ALI
F15
K16G15
P6F14F7F6
P15
R14R8R6
T10
R13R7
R15N15N6G6
E10
J9J10J11J12
K9K10K11K12
L9L10L11L12
M9M10M11M12
N13N12N11N10N9N8M13
M8L13
L8K13
K8J13
J8H13H12H11H10H9H8
T7U7
W5V5
N20
E5
P18P19
T2
Y5
P17
E4T3
Y3V4W4Y4E9
U4
VCC_G
VCC_FVCC_F
VCC_3CVCC_3CVCC_3CVCC_3C
VCC_3B
VCCR_3EVCCR_3EVCCR_3E
UPSPWR
VCCR_5DVCCR_5D
VCC_5AVCC_5AVCC_5AVCC_5AVCC_5A
GNDGNDGNDGND
GNDGNDGNDGND
GNDGNDGNDGND
GNDGNDGNDGND
GNDGNDGNDGNDGNDGNDGND
GNDGND
GNDGND
GNDGND
GNDGNDGNDGNDGNDGNDGND
SMBCLKSMBDATA
FANOUT1/RUN_ENT7/GPIO7FANOUT2/RUN_ENT8/GPIO8
LFRAME#/RUN_ENT5/GPIO5
LRCLK/PDMA_GNT#/RUN_ENT15/GPIO15
GPIR#/GPO34GPOW/GPO35
SMB_ALERT#/FANIN1/EM_OFF
FANIN2/RUN_ENT9/GPIO9
LDRQ#/RUN_ENT4/GPIO4
SCLK/PDMA_REQ#/RUN_ENT14/GPIO14PCMDATA/RUN_ENT10
RUN_ENT0/GPIO0/IN_STROB#RUN_ENT1/GPIO1RUN_ENT2/GPIO2RUN_ENT3/GPIO3GPI25
TEST#
R11
10K
12
C80.1uF
12
July 17, 2002
103
System Design Considerations
6.7 Thermal Design TM5500/TM5800 processors use a new 474-pin CBGA package. The solder footprint and pinout is identical to the TM5400/TM5600 474-pin CBGA package. The location and dimensions of the exposed silicon die and bypass capacitors on the top of the package have changed on this new TM5500/TM5800 package compared to the previous TM5400/TM5600 package. Note that the exposed silicon die contact area available for the thermal solution has decreased on the TM5500/TM5800 processor (compared to TM5400/TM5600) due to the smaller device die produced by the 0.13µ process technology used to manufacture TM5500/TM5800 processors.
Transmeta strongly recommends die-referenced thermal solutions over PCB-referenced thermal solutions for new systems designed for TM5500/TM5800 processors. Die-referenced thermal solutions allow for possible improved packages with slightly different Z-axis dimensions in the future.
6.8 Thermal Diode and Thermal Sensor
The external thermal sensor device connects to the DIODE_CATHODE and DIODE_ANODE pins of the processor. The ALERT# signal from the temperature sensor is connected to the dedicated THRM# input on the southbridge. This device is powered from V3_3.
Careful layout is required to ensure the lowest noise and greatest accuracy of the thermal sensor/diode.
6.8.1 Thermal Sensor Circuit The thermal sensing circuit on a TM5500/TM5800 processor-based system has three components: a diode on the processor die, a thermal sensor chip (in a separate package), and the interconnecting circuitry.
The on-chip diode is operated in forward-bias mode with a carefully-controlled (and very small) bias current. In this mode the voltage-temperature curve is essentially linear within the processor operating temperature range.
The thermal sensor chip provides the bias current to the diode, measures the resulting voltage, and sends the information via the SMBUS to the system (usually the southbridge). This chip is available from Maxim (the MAX1617) or from Analog Devices (AD1021). The two chips generate slightly different bias currents, but otherwise operate in the same fashion.
NoteRefer to the Thermal Design Guide for detailed thermal design information. Thermal design power (TDP) specifications can be found in the Data Book
NoteThe signals from the thermal diode operate at very low voltage and current levels and are susceptible to induced noise. Transmeta recommends following each manufacturer’s design guidelines when incorporating their thermal sensors.
July 17, 2002
104
System Design Considerations
6.8.2 Thermal Sensor Issues As mentioned, the thermal sensor chip generates a bias current for the diode. This current is on the order of 10-200 nA. This current is carried along the interconnect circuitry to the diode.
On the way from the sensor to the diode (and back again) the current encounters two major sources of noise:
• Crosstalk from adjacent high-speed circuits. The EM fields of nearby circuits can couple inductively into the thermal connector wiring, causing voltage noise on the circuit.
• Leakage currents from power, ground, or signal circuits. There is always some surface resistance on a PCB board in the order of 10 MΩ or more. This means that some leakage current is always present, but is small relative to the current on the sensor. However, surface contamination local to the thermal sensor circuit can lower the surface resistance to 10-100 KΩ. This creates a much larger leakage current. If the source of the current is a power rail, the result is a fairly constant offset of the temperature from the correct reading.
The thermal connection does allow for a low-pass filter (a 2200 pF capacitor) to filter out some of the noise. However, this is not sufficient to ensure a good reading. It is necessary to lay the board out so that the opportunities for noise to enter the circuit are eliminated, or at least minimized.
6.8.3 Thermal Sensor Layout There are a number of rules to ensure minimal noise in the thermal sensor circuits:
• Minimize the distance from the processor to the sensor chip.
This rule minimizes crosstalk because the parallelism with other lines is reduced, and the area of the inductive loop of the circuit is also at a minimum. The opportunities for that area of the system board to become contaminated are also kept to a minimum. If possible, place the sensor chip directly adjacent to the processor.
• Route the sensor lines as a differential pair.
A differential pair is a structure that places the signal and its complement directly adjacent to each other. Route the anode and cathode connections as close as the PCB manufacturing process will allow, 0.004-0.005” is reasonable for most fabricators. Follow this structure from the point that the two signals emerge from the sensor chip to the point the signals enter the processor. Any electromagnetic disturbance that the two lines are subjected to should be rejected by the sensor chip as common-mode noise.
• Route the circuit on internal layers.
This allows the power planes to act as a shield. If possible, have a layer reserved for sensitive circuitry. Do not run digital lines on the layer adjacent to the thermal circuit.
• Use guard traces.
Surround the differential pair with a copper trace connected every 0.250” to ground. Do this on ALL layers, not just the routing layers. This serves two purposes:
› Any leakage current that does occur is shorted to ground.
› It ensures extra distance from noisy circuits to the thermal circuit.
• Keep signal traces away from the thermal circuit.
July 17, 2002
105
System Design Considerations
Do not allow other traces within 0.050” of the thermal pair. While electromagnetic fields may still be present, the gradient of those fields drops exponentially with distance. If the gradient is too large, the two traces are exposed to different field strengths, and the common-mode rejection of the sensor chip has no effect on this noise. Keep the gradient small by separating noise sources from the sensor circuit.
6.8.4 Thermal Sensor Example Schematic The schematic on the following page illustrates the thermal sensor circuit.
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
ABasilThursday, June 14, 2001 1 1
Thermal Sensor3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
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Date: Author:
Project:
THRM#
DIODE_ANODE
DIODE_CATHODE
SMBDATA
SMBCLK
V3_3
C22200pFX7R
12
U1IC_MAX1617MAXIM
3
4
215
106
7
14
12
11
8
1591316
DXP
DXN
VCCSTBY
ADD0ADD1
GND
SMBCLK
SMBDATA
ALERT
GND
NC_1NC_5NC_9
NC_13NC_16
C10.1uF
12
July 17, 2002
107
System Design Considerations
6.9 TDM Debug Interface Connection Connect TDCA RESET# directly to the processor RESET# signal, and also to P_PCI_RST# through a 1.2 KΩ resistor. This allows the TDM to override the PCI reset signal and issue a processor reset.
In general, TDM connections to serial ROM devices require a resistor between the processor signal and the ROM device to allow the TDM to override the active signal.
The Transmeta Debug Module (TDM) communicates to the target through a high-density 30-pin flex cable known as TDCA. The TDCA is shown with connections to the core system. The TDM and the debug connection is used for flashing Code Morphing software ROM and the mode-bit ROM, connecting to the Transmeta ICE, and for other debugging purposes.
NoteExercise caution when plugging or unplugging the TDCA ribbon cable. The pins that make up the interface can be easily bent, and the cable itself is delicate. If problems arise with the TDM unit, try changing the cable first, as it is much more likely to show problems than the TDM.
July 17, 2002
108
System Design Considerations
See the diagram below for the TDM interface pinout and signal descriptions.
The schematic diagram on the following page shows the TDM interface circuit.
Figure 23: Transmeta Debug Connector (TDCA)
RNMI
DOCKING
RESET#
CFG_CS
CFG_SCLK
CFG_SDATA
SROM_CS#1
SROM_CS#0
SROM_SCLK
SROM_SOUT
SROM_SIN
GND
S_SDATA
S_SCLK
TCK
TMS
TRST#
TDO
TDI
9
Tra
nsm
eta
Deb
ug C
onne
ctor
A(3
0 P
in, .
5mm
, FLE
X c
able
)
Non-Maskable Debug Interrupt(NM_DEBUG_INIT)
Remote Debug Interrupt(DEBUG_INIT)
Processor RESET# Signal
Mode Rom Control
CMS FLASH Control
Processor I2C interface
Processor JTAG Signals
GND from Target
The TDCA is a 30-pin, 0.5mm flex cable connector that has all vital signals needed to debug the Crusoeprocessor (CMS Flash control, Mode ROM Control, I2C, RNMI, Docking, RESET#, and JTAG signal)
TDCA Pinout
to target
to TDM
0.5mm,FPC,Vertical,SMT,ZIF30 contact - 52559-3092http://www.molex.com/product/ffc/52559.html
Vertical style part number (molex)
0.5mm,FPC,Right Angle,SMT,ZIF,Top Contact30 contact - 52435-3091http://www.molex.com/product/ffc/52745.html
Right Angle part number (molex)
SYS_RST#System Level Reset
Transmeta Debug Connector A
TDCA Functional Description
RNMI
DOCKING
RESET#
CFG_CS
CFG_SCLK
GND
CFG_SDATA
SROM_CS#1
SROM_CS#0
GND
SROM_SCLK
GND
SROM_SOUT
SROM_SIN
GND
S_SDATA
GND
S_SCLK
GND
TDI
GND
TCK
SYS_RST#
TMS
TRST#
GND
SUSC#
SUSB#
GND
3
2
4
5
6
7
8
9
10
11
13
12
14
15
16
17
18
19
20
21
23
22
24
25
26
27
28
29
30
1
Transmeta D
ebug Connector A
SUSC#Power Supply Control
SUSB#
RNMI
DOCKING
RESET#
CFG_CS
CFG_SCLK
GND
CFG_SDATA
SROM_CS#1
SROM_CS#0
GND
SROM_SCLK
GND
SROM_SOUT
SROM_SIN
GND
S_SDATA
GND
S_SCLK
GND
TDI
TDO
GND
TCK
SYS_RST#
TMS
TRST#
GND
SUSC#
SUSB#
GND
28
29
27
26
25
24
23
22
21
20
18
19
17
16
15
14
13
12
11
10
8
9
7
6
5
4
3
2
1
30
Transm
eta Debug C
onnector A
Pinout forVertical FPCConnector
Pinout for Right AngleFPC Connector
TDO
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TRANSMETA DEBUG CONNECTOR
NOTE: Pinout depends on type of connector used. Thepinout below is for the vertical TDC connector. See theDesign Guide for the pinout of the right angle connector.
TM5800 Design Guide
Custom
ABasilTuesday, December 04, 2001 1 1
TDM Connector3940 Freedom CircleSanta Clara, CA. 95054(408) 919-3000
DOCUMENT#
Copyright (C) 1995-2001 TransmetaCorporation. All rights reserved.This document contains confidential andproprietary information of TransmetaCorporation. It is not to be disclosed or usedexcept in accordance with applicableagreements. This copyright notice does notevidence any actual or intended publication ofsuch document. Page of
Title:
Document Number:
Size:
Revision:
Date: Author:
Project:
MANUAL_RST#
TDM_SDA
TDM_SCL
TDM_SROM_CS1#
SUSB#
TDM_SRCS
TDM_TCK
TDM_SROM_CLK
TDM_TDI
NM_DEBUG_INT
TDM_SRCLK
TDM_TDO
TDM_SRDATA
TDM_SROM_OUT
TDM_TRST#
DEBUG_INT
SUSC#
TDM_RST#
SROM_SIN
TDM_SROM_CS0#
TDM_TMS
J1
MOLEX52559_3092
123456
87
9101112131415161718192021222324252627282930
NM_DEBUG_INITDEBUG_INITRESET#SYS_RST#CFG_CSCFG_SCLK
CFG_SDATAGND
SROM_CS1#SROM_CS0#GNDSROM_SCLKGNDSROM_SOUTSROM_SINGNDS_SDATAGNDS_SCLKGNDTDIGNDTDOTCKTMSTRST#GNDSUSC#SUSB#GND
July 17, 2002
110
System Design Considerations
July 17, 2002
111
C h a p t e r 7
PCB Layout Guidelines
7.1 PCB Design Layout • For thermal sensor/diode signal routing make sure to follow the guidelines in Thermal Diode and Thermal
Sensor on page 103.
• V_CPU_CORE is placed on the bottom layer (Signal 4). All other supply voltages are placed on the PWR layer. If possible, place a V_CPU_CORE plane on as many layers as possible.
• GND 1 is the signal return path for traces on Signal 1 and 2. GND 1 plane is to be solid, with no breaks or cuts.
• GND 3 is the signal return path for traces on Signal 3 and 4 (6 and 5 for ten layer stack-ups). The GND 1, GND2, and GND 3 Planes are to be solid, with no breaks or cuts.
• Anti-pad treatment for vias on GND 1, GND 2, GND 3, and PWR layers. Pad diameter is to be smaller than the via hole. With 0.007" to 0.008" clearance from the via hole to the plane. This results in 0.022" to 0.023" copper between vias under the processor. If normal anti-pad treatments were allowed, the amount of copper under the chip would be severely decreased, limiting processor performance.
• Material between PWR and GND 2 layers must be a maximum of 0.005" thick. Thinner is desirable (0.003” should be attainable).
• If the previous note is followed, signals run on Signal 2 (Inner Layer 3) may cross cuts or breaks on the PWR plane (Inner Layer 4). Critical signals may also then be placed on any signal layer.
• HCLK and PCI_CLK to the processor should have matched lengths. Also, each PCI device/slot clock should be matched to this same length.
• All vias on the pad side of the PCB processor BGA footprint must be covered with solder mask. Failure to do so will potentially short signals together during the soldering process.
• Keep trace lengths as short as possible.
NoteThe guidelines in this chapter must be followed for the design to meet specified TM5500/TM5800 processor operating frequencies.
July 17, 2002
112
PCB Layout Guidelines
• When transitioning signals between the return paths, insert a ground via next to the signal via, i.e. when transitioning from Signal 1 or Signal 2 to Signal 3, or when transitioning from Signal 3 or Signal 4 to Signal 1. This will maintain return path continuity.
• For improved manufacturing of the PCB, 0.006” traces and 0.006” spaces is recommend for the outer two layers (top and bottom), with 0.005” traces and 0.005” spaces on the internal layers.
• DO NOT match impedances on traces wider than 0.006”.
• DO NOT allow cutouts in the ground planes.
7.2 Example PCB Fabrication Notes • The finished printed circuit board shall meet the requirements of IPC-A-600.
• Configuration of the printed circuit board not specifically dimensioned on the drawing shall be controlled by the Gerber data.
• Material: 0.056” ± 0.006” thick glass epoxy, natural color. Laminated NEMA grade FR4. See layer stack-up for copper weight and layer orientation. Core and prepreg combinations are optional to the manufacturer unless otherwise specified in the layer stack-up.
• Plating: all holes and conductive surfaces shall be plated with 0.001” copper minimum. All copper areas not covered by solder mask shall be solder coated 0.0003” minimum.
• All hole diameters are stated as finished hole sizes.
• Solder mask: photo-imaged liquid polymer on both sides of board in accordance with IPC-SM-840, type B Class 2 over bare copper.
• Component marking: silk-screen component side (and solder side) white, non-conductive epoxy ink. Lands and exposed plated areas to be free of ink.
• Bow and twist: shall not exceed 0.005” per lineal inch.
• Electrical test: the printed wiring board shall be electrically tested for opens and shorts. The results of the electrical test shall be documented and delivered along with each lot.
• Identification: vendor logo to be etched on the solder side, silk-screen date code on the bottom side.
• Characteristic impedance: 55 Ω ± 10%. Note: this will be 60 Ω ± 10% when DDR SDRAM is used in the design.
July 17, 2002
113
PCB Layout Guidelines
7.3 Board Design Guidelines The guidelines provided below were taken from TM5500/TM5800 processor-based reference designs using Allegro PCB layout tools. The dimensions are given in mils (1 mil = 1/1000 = 0.001 inch).
7.3.1 Printed Circuit Board Stackup
7.3.2 Allegro Standard Spacing Constraints
Table 17: Recommended Eight Layer PCB Stackup
Signal/Layer Material1 Signal 1 ½ oz. copper2 GND 1 1 oz. copper3 Signal 2 ½ oz. copper4 PWR 1 oz. copper5 GND 2 1 oz. copper6 Signal 3 ½ oz. copper7 GND 3 1 oz. copper8 Signal 4 ½ oz. copper
Table 18: Standard Spacing/Line/Via Constraints 1
1. Data taken from Allegro.
Constraint Name Constraint ValueLine-to-line 5 milsLine-to-pad 5 milsPad-to-pad 5 milsLine width 5 milsDefault via 25/12 milsPrimary/secondary signal via 12/12 milsEtch on subclass AllowedSame net DRC On
July 17, 2002
114
PCB Layout Guidelines
7.3.3 Allegro Extended Spacing Constraints
Table 19: Extended Global Spacing/Line/Via Constraints 1
Constraint Name Default Constraint Value BGA Constraint ValuePin-to-pin 5 mils 5 milsLine-to-pin 5 mils 5 milsLine-to-line 5 mils 5 milsVia-to-pin Note 2 Note 2
Via-to-via 10 mils 10 milsVia-to-line 5 mils 5 milsShape-to-pin 5 mils 5 milsShape-to-via 5 mils Note 2
Shape-to-line 5 mils 5 milsShape-to-shape 5 mils 5 milsThru pin-to-thru pin 5 mils 5 milsThru pin-to-SMD pin 5 mils 5 milsThru pin-to-test pin 5 mils 5 milsThru pin-to-thru via 10 mils 6 milsThru pin-to-test via 10 mils 6 milsThru pin-to-buried blind via 10 mils 6 milsThru pin-to-line 5 mils 5 milsThru pin-to-shape 5 mils 5 milsSMD pin-to-SMD pin 5 mils 5 milsSMD pin-to-test pin 5 mils 5 milsSMD pin-to-thru via 8 mils 7 milsSMD pin-to-test 8 mils 7 milsSMD pin-to-buried blind via 8 mils 7 milsSMD pin-to-line 5 mils 5 milsSMD pin-to-shape 5 mils 5 milsTest pin-to-test pin 5 mils 5 milsTest pin-to-thru via 10 mils 6 milsTest pin-to-test via 10 mils 6 milsTest pin-to-buried blind via 10 mils 6 milsTest pin-to-line 5 mils 5 milsTest pin-to-shape 5 mils 5 milsThru via-to-thru via 10 mils 10 milsThru via-to-test via 10 mils 10 milsThru via-to-buried blind via 10 mils 10 milsThru via-to-line 5 mils 5 milsThru via-to-shape 5 mils Note 2
Test via-to-test via 10 mils 10 milsTest via-to-buried blind via 10 mils 10 mils
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7.3.4 Allegro Extended Physical (Lines/Vias) Constraints
7.3.5 Allegro Extended Electrical (Lines/Vias) Constraints
Test via-to-line 5 mils 5 milsTest via-to-shape 5 mils Note 2
Buried blind via-to-buried blind via 10 mils 10 milsBuried blind via-to-line 5 mils 5 milsBuried blind via-to-shape 5 mils Note 2
Line-to-line 5 mils 5 milsLine-to-shape 5 mils 5 milsShape-to-shape 5 mils 5 mils
1. All etch/layers. Data taken from Allegro. 2. Defined as differential in other places.
Table 20: Extended Physical Constraints 1
1. All etch/layers. Data taken from Allegro.
Constraint Name Default Value PCI Net Value CLK Net ValueMaximum line width 5 mils 5 mils 5 milsMinimum neck width 5 mils 5 mils 5 milsMaximum neck length 0 mils 0 mils 0 milsAllow on etch subclass Allowed Allowed AllowedT-junctions Anywhere Pins and vias only Pins and vias onlyMinimum blind buried via stagger 5 mils 5 mils 5 milsMaximum blind buried via stagger 5 mils 5 mils 5 milsPad-pad direct connect Not allowed Not allowed Not allowedCurrent via 25/12 mils 25/12 mils 25/12 mils
Table 21: Extended Electrical Constraints 1
1. All etch/layers. Data taken from Allegro.
Net Category Maximum Stub Length Maximum Via Count/NetDefault Unlimited UnlimitedPCI 1500 mils 6CLK 600 mils 5DDR 300 mils 4SDR 300 mils 4
Table 19: Extended Global Spacing/Line/Via Constraints 1 (Continued)
Constraint Name Default Constraint Value BGA Constraint Value
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7.4 Footprint and Pin Escape Diagram Figure 24: Mechanical Footprint
A
1
AE
19
SILKSCREEN OUTLINE
PADSTACKSMT PAD = .030" DIASOLDERMASK OPENING = .033" DIAPASTEMASK OPENING = .026" DIA
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A p p e n d i x A
System Design Checklists
The checklist Status field is for designers and implementers to use as the project progresses. Use as follows:
Status DescriptionP Task is pending (waiting for other assistance, etc.) C Coding - implementation/testing in progress V Implementation verified O Other group’s function blank Task not begun
Power Supply Checklist
Item Description Status1. Processor power supply ramp-up must be properly sequenced. See Chapter 3, Power
Supply Sequencing in the System Design Guide for details on power sequencing requirements.
2. The VRDA (VID) pin connections between the processor and the V_CPU_CORE (CVDD) regulator should meet the following requirements: • The processor VRDA outputs are open-drain, and therefore require pull-ups. If the
VRM controller does not have internal pull-ups on its VID inputs, then external pull-up resistors must be used. At no time can the VRDA signals be pulled up to a voltage greater than 3.3 V plus a diode drop.
• Ensure that VRDA signals are connected to the correct corresponding VID pins (VRDA[0] to VID[0], etc.)
3. The POWERGOOD output of the V_CPU_CORE (CVDD) regulator must not glitch during LongRun power management transitions. Designs that do glitch must include a low pass filter, isolated from down-stream logic, to remove the glitch from the regulator POWERGOOD output. Note that regulators qualified by Transmeta for TM5500/TM5800 processor have their POWERGOOD output blanked during transitions to alleviate this problem.
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4. If an independent voltage monitor is used to generate POWERGOOD, the signals below should be connected correctly: • All power inputs should be connected to ACPI System S0 State power (not STR or
always-on power).• Manual reset (if supported) - no isolation resistors are needed between different
sources driving that pin (unless a source is push-pull instead of open-drain). No capacitor is needed on the manual reset pin either. The device should have a guaranteed 100 mS negation of POWERGOOD that acts as a much better debounce filter than an external capacitor. The manual reset input of an independent monitor is an ideal place to connect the SYS-RST# pin of the Transmeta debug connector.
5. ACPI System Power state support: • All ACPI System S0 State power in the system, including all processor power, should
be controlled by the OFF_PWR1# pin on the ALI 1535.• ACPI System S3 State power (DRAM power) supplies should be controlled by the
OFF_PWR2# pin on the ALI 1535. Rise time control should be used to minimize glitching/drooping of S0 power.
6. Make sure all voltage regulators operate within the specified tolerance range printed in the Data Book. Verify that these voltages remain within tolerance across all operating conditions for the system.
7. All ceramic decoupling capacitors should be X7R dielectric material. No Y5V or Y5U material should be used.
8. V_CPU_CORE (CVDD) decoupling:• High frequency: at least 8 low-ESL ceramic capacitors on the back side of the board
directly underneath the processor. The case size should be as small as possible - 0402, 0306, or 0603 are recommended. The dielectric should be X7R, and the value should be the highest supported in the chosen case size with an X7R dielectric. Typically, this value is 0.22 µF or 0.1 µF.
• Mid frequency: approximately 14 low-ESL ceramic capacitors as close to the processor as possible. Recommended value is 1 µF with 0805 case size and X7R dielectric.
• Low frequency: at least 800 µF. The combined ESR of all the low frequency capacitors together must be less than 0.005 Ω.
9. 3.3 V (IOVDD) switched supply decoupling at the processor: • High frequency: none required.• Mid frequency: approximately 10 low-ESL ceramic capacitors as close to the
processor as possible. Recommended value is 1 µF with 0805 case size and X7R dielectric.
• Low frequency: two low-ESR capacitors, 22 µF each.10. 2.5 V (IOVDD25) switched supply decoupling at the processor:
• High frequency: none required.• Mid frequency: if DDR memory is supported, approximately 8 low-ESL ceramic
capacitors as close to the processor as possible. If DDR memory is not supported, only 1 such capacitor is needed. For each of these capacitors, the recommended value is 1 µF with 0805 case size and X7R dielectric.
• Low frequency: if DDR memory is supported, one low-ESR capacitor of 22 µF. If DDR memory is not supported, no low frequency decoupling on 2.5 V switched is required.
Power Supply Checklist
Item Description Status
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11. If DDR memory is supported, the decoupling on 2.5 V STR at the DRAMs should be:• High frequency: approximately 3 low-ESL ceramic capacitors as close as possible to
the power pins of each DRAM. Recommended value is 0.1 µF with 0603 case size and X7R dielectric.
• Mid frequency: none required.• Low frequency: one 10 µF capacitor for approximately every 2 DRAMs. Each
capacitor should be either ceramic or low-ESR tantalum.12. Ensure that PLLVDD tracking circuit has been incorporated.
DRAM Checklist
Item Description Status1. Designs with no DDR should connect the high-order SDR chip selects to the most
permanent bank of memory. That is, CS[3:2], CLK[3:2], and CKE1 should connect to the most permanent banks of SDR.
2. The CKE high-speed bidirectional level-translator should be:• Controlled by SUS_STAT1# (pin T17) on the iPIIX4 or SUSPEND# (pin W13) on the
ALI 1535 .• Controlled by the same signal that is connected to the processor SLEEP# pin.• Powered by at least 4.3 V. If less than 4.3 V is used, the signals will be clamped, and
noise margin will be reduced.3. There can be no more than 8 DDR devices.4. DDR and SDR x32 memory is not supported.
SDR SDRAM Address Line Connections1
Processor Signal DRAMSignal
JEDEC SODIMM-144Pin Number
JEDEC DIMM-168Pin NumberName Pin Number
S_A[0] P3 A0 29 33S_A[1] N4 A1 31 117S_A[2] V5 A2 33 34S_A[3] P4 A3 30 118S_A[4] N5 A4 32 35S_A[5] M1 A5 34 119S_A[6] P1 A6 103 36S_A[7] N1 A7 104 120S_A[8] P2 A8 105 37S_A[9] N2 A9 109 121S_A[10] M2 A10 / AP 111 38S_A[11] K1 A11 112 123S_A[12] K2 A12 70 126S_BA[0] L2 BA0 106 122S_BA[1] L1 BA1 110 39
1. Designs containing an SDR SODIMM should connect the address lines as shown in this table.
Power Supply Checklist
Item Description Status
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PCI Checklist
Item Description Status1. All the PCI REQ and GNT signals must have pull-ups to V3_3 (IOVDD).2. All IDSEL series resistors should be 100 Ω.3. The PCI LOCK# pin on the processor should be pulled up to 3.3 V switched and not
connected to anything else. TM5500/TM5800 processors do not support locked PCI cycles. All other PCI LOCK# pins in the system should be connected together and pulled up.
4. No PCI signal should rise above 3.3 V because the processor is not 5 V tolerant. If the design contains any components that drive 5 V PCI signals, a high-speed bidirectional level-translator is needed at the processor to clamp it to 3.3 V. Such a translator is also needed if a PCI edge connector is present that is keyed for 5 V.
Serial Bus Checklist
Item Description Status1. The SMBus from the southbridge should not be connected to the Serial Debug Bus (i.e.
pins SD_SCLK and SD_SDATA). The Serial Debug Bus must be connected to the Transmeta debug connector and be pulled up to V3_3 (IOVDD).
2. If the Code Morphing software serial ROM is supported, the write protection PLD should be implemented. Check for the following:• The pull-up on CS# should be at the PLD input and not its output. The processor tri-
states the PLD input during Deep Sleep, but the PLD always drives the output.• The latest reference design pinout should be supported. The write protect signal
should connect to pin 2 of the DIP/TSOP or pin 3 of the PLCC. The CS# signal should connect to pins 4 and 5 on the DIP/TSOP and pins 5 and 6 on the PLCC.
• None of the pins are 5 V tolerant, so the signal driving the write protect line should have a 3.3 V swing.
• The PLD should be a 3.3 V part with a feature to reduce power consumption when inputs are not toggling.
• All unused inputs and tri-stated outputs should be connected to ground. Pins 18, 19, and 23 on the DIP/TSOP and pins 20, 21, and 27 on the PLCC should be no-connected.
3. All new designs must include a mode-bit ROM circuit. For older system designs that did not provide mode bit ROM support, a strapping resistor should be present on the mode bit ROM data line (i.e. pin CFG_SDATA) to support each applicable boot option below:• Boot from serial Code Morphing software ROM: 10 KΩ pull-up to 3.3 V switched.• Boot from parallel ROM: 10 KΩ pull-down.
4. The debug connector should be wired properly to both the mode-bit ROM and serial Code Morphing software ROM:• Series resistors (220 Ω each) on all the signals between the processor (or PLD) and
the ROMs.• No series resistor on all the signals between the debug connector and the ROMs.• Correct pinout on the debug connector. The most common mistakes are reversing
the pin order and swapping SROM_CS[1:0]#. On the vertical connector, pin 1 is RNMI. On the right angle connector, pin 1 is GND. SROM_CS1# should be on pin 9, and SROM_CS0# should be on pin 10.
5. If the serial Code Morphing software ROM is implemented, the 28-pin Atmel part should be used. The 32-pin Atmel part and the Macronix part have both been discontinued.
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Other Signals Checklist
Item Description Status1. Correct pull-up and pull-down resistors should be configured as described in Chapter 6,
Signal Pull-ups and Pull-downs in the System Design Guide.2. The SLEEP# pin should be driven by the proper signal on the southbridge:
• ALI 1535: an AND gate whose inputs are SUSPEND# (pin W13) and AGP_STP# (pin E11). The AND gate must have 5 V tolerant inputs and a 3.3 V output.
• The processor Reserved pin G2 should control the unprotect feature of the parallel ROM.
3. If a unified ROM (i.e. Code Morphing software and BIOS in a parallel ROM) is supported:• EPROMA[2:1] should connect to the highest order address lines on the parallel ROM.• The processor’s GPIO should switch 12 V onto the parallel ROM.
4. The Maxim thermal sensor should be connected as follows:• MAX1617 pin 3 to processor pin A18.• MAX1617 pin 4 to processor pin B16.• MAX1617 alert output to THERM# input of ALI 1535.• If a MAX1619 is supported, the OVERH# output should not be used.
5. The free running PCI clock (PCICLK_F) should connect to the processor’s PCI clock input as well as the southbridge PCI clock input. Since most clock generators have only one free running PCI clock, special routing considerations are necessary. See also Chapter 6, Using CLKRUN in the System Design Guide.
6. The RESET# pin on the Transmeta debug connector must be connected to reset only the processor. The SYS_RST# pin on the Transmeta debug connector should be connected in such a manner as to reset the entire system when asserted.All processor reset pins should be connected as shown in the Chapter 6, System Reset, in the System Design Guide.
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Serial Write-protection PLD DataJEDEC Fuse Map and CUPL Source Code
24-Pin TSSOP
The following text is the JEDEC file representing the fuse map for the write protection PLD. It was produced by the CUPL PLD design compiler for a 24-pin TSSOP package. CUPL source code is also shown below.
.
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Figure 25: Write Protection TSSOP-24 JEDEC Fuse Map
QP24*QF5892*G0*F0*L00000 11111111111111110111011111111111*L00032 11111111111111111111111111111111*L00064 11111111111111111111111111111111*L00096 11111111110110111111111111111111*L00128 11111111111111111111111110101111*L00160 11111111111111111111101111111111*L00192 11111011101111111111111111111111*L00224 01111111111111111011011111111111*L00256 11111111000000000000000000000000*L02144 00000000000011111111111111111111*L02176 11111111111111111111111111111111*L02208 11111111111011011111111111111111*L02240 11111111111101111111110111011111*L02272 11111111111111111111111101111111*L02304 11101110111111111111111111110000*L02880 00000000000000000000000011111111*L02912 11111111111111111111111111111111*L02944 11111111111110111111110111011111*L02976 11111111111111111111111111111111*L03008 11011110111111111111111111111111*L03040 11110111111111011101111101111111*L03072 11111111111111111011111111101110*L03104 11111111111111111111000000000000*L03648 00001111111111111111111111111111*L03680 11111111111111111111111111111111*L03712 10011111111111111111111111111111*L03744 11111111111110111110111111111111*L03776 11111111111110111111111110111111*L03808 10111111111111111111111101111111*L03840 11111011111101111111111111111111*L05792 00000000000000000100000010100100*L05824 00000011000000000000000000000000*C6A76*
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Figure 26: Write Protection TSSOP-24 CUPL Source Code
Name wrprotpd;PartNo 0;Date 8/09/00;Revision 3;Designer Transmeta;Company Transmeta;Assembly 1;Location 1;Format j; /* Use JEDEC output format */Device G22V10CP; /* This is the code for a 24-pin TSSOP package. */
/* The powerdown function on pin 4 is implied by *//* this description. */
/************************************************************************ This device protects against writes and erases to the serial flash* when the WP pin is asserted. It works by forcing the chip select* to negate when a write or erase command is detected. The WPNEG* pin causes the WP input to be inverted in case WP is active-low on* the circuit board. Two chip selects are handled for the case of* two half-size serial ROMs.** A select input pin is used to choose between Atmel and Macronix.* The reason this is needed is the opcodes between the two parts are* similar enough to require detection of all 8 bits of the opcode.* If the chip select is negated after the 8th bit of the opcode, the* flash device will execute the command with bogus address and data.* The select input allows write or erase opcodes to be detected in as* few as two bits.** This design file is written for the CUPL programmable logic* compiler. A free, functional, demo version of the compiler is* available from http://www.logicaldevices.com/.***********************************************************************/
/** Input pins** All unused inputs should be tied high or low on the circuit board.* Active-low pins are denoted by the ! prefix. After the input and* output sections of this file, all syntax refers to the logical* level of a pin and not its physical level.*/PIN 1 = CKIN; /* Serial flash clock */PIN 2 = WP; /* Write protect */PIN 3 = DIN; /* Serial flash data input *//* PIN 4 = PD; Powerdown pin, implied by device selection */PIN 7 = WPNEG; /* Write protect negate: */
/* Tie low if WP is active-high *//* Tie high if WP is active-low */
PIN 8 = SEL; /* Select type of flash: *//* High = Macronix *//* Low = Atmel */
PIN 5 = !CS0IN; /* Intercepted serial flash chip selects. If */PIN 6 = !CS1IN; /* one is unused, it should be tied high. */
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/** Output pins*/
PIN [18,19] = [Q0..1]; /* Flip-flops for the state machine */PIN 17 = !CS0OUT; /* New serial flash */PIN 23 = !CS1OUT; /* chip selects */
/** Assign asynchronous reset (AR) controls on all flip-flops** When both chip selects are negated, the state machine needs to* reset to the BIT7 state. Otherwise, it will never know when bit 7* of the opcode occurs.*/
Q0.AR = !CS0IN & !CS1IN;Q1.AR = !CS0IN & !CS1IN;
/** Assign synchronous preset (SP) and output enable (OE) controls on* all flip flops*/
Q0.SP = 'b'0;Q1.SP = 'b'0;Q0.OE = 'b'1;Q1.OE = 'b'1;
/** State names and numbers** To guard against output glitches, the state numbers are assigned so* that most transitions only change one flip-flop.*/
$DEFINE BIT7 'b'00$DEFINE BIT6 'b'11$DEFINE PAT_MATCH 'b'10$DEFINE NO_PAT_MATCH 'b'01
/** State transitions** The write or erase opcodes used by Crusoe are:* Macronix:* F2h Page Program* F1h Sector Erase* Atmel:* 82h Direct Program through Buffer* The read opcodes used by Crusoe are:* Macronix:* 83h Read Status* 52h Read Array* Atmel:* 57h Read Status* 52h Main Memory Page Read*/
Figure 26: Write Protection TSSOP-24 CUPL Source Code (Continued)
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Serial Write-protection PLD Data
SEQUENCE [Q1..0]
PRESENT BIT7IF !DIN NEXT NO_PAT_MATCH; /* No write or erase opcode */
/* has bit 7=0 */IF DIN & !SEL NEXT PAT_MATCH; /* For Atmel, bit 7=1 means a */
/* write or erase */IF DIN & SEL NEXT BIT6; /* For Macronix, need to keep */
/* checking */PRESENT BIT6
IF DIN NEXT PAT_MATCH; /* Must be F1h or F2h */IF !DIN NEXT NO_PAT_MATCH; /* Can't be F1h or F2h */
PRESENT PAT_MATCHNEXT PAT_MATCH; /* Only way out is reset */
PRESENT NO_PAT_MATCHNEXT NO_PAT_MATCH; /* Only way out is reset */
/** Output equations** Each chip select is copied from input to output unless the current* state is PAT_MATCH and the WP input is asserted. In that case,* both chip selects are negated. If WPNEG is asserted, the sense of* WP is reversed.** For the unusual case of WP being asserted after a write or erase* opcode but before the end of the bus cycle, both chip selects will* immediately negate.*/CS0OUT = CS0IN & !((WP $ WPNEG) & Q1 & !Q0);CS1OUT = CS1IN & !((WP $ WPNEG) & Q1 & !Q0);/* ^-- $ is the XOR operator in CUPL */
Figure 26: Write Protection TSSOP-24 CUPL Source Code (Continued)
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Index
AAllegro spacing constraints 114
Bblock diagram 13
CCD (DDR) port
Clock Enable (CD_CKE) isolation 52power supply 53signal termination 52
clocks 83Code Morphing software serial flash 91
write-protection circuit 93Code Morphing software storage 96configuration
mode-bit ROM 89serial Code Morphing software flash ROM 91, 93
connectiondebug connector cable 108
Ddebugging interface 107design considerations 21, 83DI (SDR) port
bank selection 66Clock Enable (S_CKE) isolation 67signal termination 67
Eerase-all command 96
Fflash, serial (for Code Morphing software ) 91
flash, serial (for Code Morphing software)write protection 93
footprint 116
Iinterface, debugging 107
Mmechanical footprint 116mode-bit ROM 89
Pparallel ROM Code Morphing software storage 96PCB footprint 116pin escape diagram 116pinout, debug connector 108power management
important issues 21protection circuit 96
Rreset 86ROM, mode-bit 89
Sserial flash (Code Morphing software) 91serial flash write protection circuit 93serial ROM Code Morphing software storage 96system reset 86
TTDCA 107TDCA connector pinout 108TDM 107
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Index