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TMS320DM357Evaluation Module

2008 DSP Development Systems

ReferenceTechnical

TMS320DM357 Evaluation Module Technical Reference

511455-0001 Rev. A December 2008

SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477

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WARNING

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Copyright © 2008 Spectrum Digital, Inc.

Contents

1 Introduction to the DM357 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the DM357 Evaluation Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-72 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the DM357 Evaluation Module. 2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 Flash, NAND Flash, SRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.3 Memory Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.4 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.1.5 EMIF Buffer/Decoder Control CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 Input Video Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.1 On Chip Video Output DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.2 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.1 I/O Expanders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.4.2 MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.5 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.6 DM357 Core CPU Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.7 USB Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.8 Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the DM357 Evaluation Module and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.1 J2, MSP430 JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.2 J3, SD/MMC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.3 J4, EM_CS2 Routing Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.4 J6, External RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.5 J7, USB Host/Gadget Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.6 J8, Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.7 J9, USB Capacitance Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.8 J10, MiniAB USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.2.9 J11, Composite Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.10 J12, RCA Jack, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.2.11 J13, 14 Pin TI JTAG Emulation Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.2.12 J14, +5 Volt Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.2.13 J15, 20 Pin ARM JTAG Emulation Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.2.14 J17, CPLD Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.2.15 J18, MSP430 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

3.2.16 J19, I2C Bus Expander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.2.17 P2, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.2.18 P3, Stereo Line In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.2.19 P4, Headphone Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.2.20 P5, Stereo Line Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.2.21 P6, RS-232 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.2.22 U3, Infrared Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.3 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.3.1 DC1, EMIF Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.3.2 DC2, GIOV33/Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.3.3 DC3, SPI, McBSP, I2C Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.3.4 DC4, Video Input Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.3.5 DC5, Video Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.3.6 DC6, SD Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.3.7 DC7, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.4 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.5 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.6.1 S1, EMU0/1 Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.6.2 S3, Processor Configuration/Boot Load Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.6.3 S4, RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.6.4 S5, User CPLD Option Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.6.5 SW1, Power On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.6 Test Point Connector, JP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 3.7 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the DM357 Evaluation ModuleB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the DM357 Evaluation Module

About This Manual

This document describes the board level operations of the DM357 Evaluation Module(EVM). The EVM is based on the Texas Instruments DM357 Processor.

The DM357 Evaluation Module is a table top card that allows engineers and softwaredevelopers to evaluate certain characteristics of the DM357 processor to determine ifthe processor meets the designers application requirements. Evaluators can createsoftware to execute on board or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The DM357 Evaluation Module will sometimes be referred to as the DM357 EVM orEVM.

Program listings, program examples, and interactive displays are shown in a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents, Application Notes and User Guides

Information regarding TMS320DM357 technology can be found at the following TexasInstruments website:

http://www.ti.com

Table 1: Manual History

Revision History

A Alpha Release

Table 2: Board History

PWBRevision

History

A Alpha Release

1-1

Chapter 1

Introduction to the DM357 EVM

Chapter One provides a description of the DM357 EVM along with the keyfeatures and a block diagram of the circuit board.

Topic Page

1.1 Key Features 1-21.2 Functional Overview 1-31.3 Basic Operation 1-41.4 Memory Map 1-51.5 Configuration Switch Settings 1-61.6 Power Supply 1-7

Spectrum Digital, Inc

1-2 DM357 EVM Technical Reference

1.1 Key Features

The DM357 EVM is a standalone development platform that enables users toevaluate and develop applications for the TI DM357 processor. Schematics, logicequations and application notes are available to ease hardware development andreduce time to market.

The EVM comes with a full complement of on board devices that suit a wide variety ofapplication environments. Key features include:

• A Texas Instruments DM357 processor with an ARM processor operating up to 270 Mhz. and H.264/MPEG4/JPEG coprocessor

• 1 video input port, supports composite or S video

• 1 video DAC outputs - composite

• 256 Mbytes of DDR2 DRAM

• UART, Media interface (SD card, MMC)

• 64 Mbytes NAND Flash for BOOT, 2 gigabyte NAND storage NAND

• AIC33 stereo codec

• USB2 Interface

Figure 1-1, Block Diagram DM357 EVM

IR PWRSW

S3

Con

fig

DC3 DC2

3VBAT

SD/MMC

TI JTAGMSP430 JTAG

SV

HS

IN

US

B

VID

EO

IN

AU

DIO

IN

HP

OU

T

AU

DIO

OU

T

S/P

DIF

Opt

ical

S/P

DIF

Ana

log

UART

+5V

MSP430

User LEDs

DC7

DC6

S1 StorageNAND

1.2V CPU Core Voltage

1.8V I/O Voltage

3.3V Board Supply Voltage

AIC33

I2CGPIO

I2CGPIO

I2C

GP

IOI2

CE

EP

RO

M

DC4 (VIDEO IN)

TVP5146

S/PDIFDrivers

CO

MP

OU

T

DC5 (VIDEO OUT)

EMIF

Video Ports

DDR

I2C

CPLD

Serial Media

ENETPHY

EMAC

CPLDPGM

DDR

DDR

10/100ENET

DC1 (EMIF)

TMS320DM357

ARM JTAG

BootNAND


1-3

• 10/100 MBS Ethernet Interface

• IR Remote Interface, real time clock, via MSP430

• Configurable boot load options

• JTAG emulation interface with 1.8 volt to 3.3 volt translators

• 8 user LEDs

• Single voltage power supply (+5V)

• Expansion connectors for daughter card use

1.2 Functional Overview of the DM357 EVM

The DM357 on the EVM interfaces to on-board peripherals through the 16-bit wideEMIF peripheral interface pins. The DDR2 memory is connected to its owndedicated 32 bit wide bus. The EMIF bus is also connected to the boot NAND, storageNAND, and daughter card expansion connectors which are used for add-in boards.

On board video decoder for composite or s-video and on chip encoders interface videostreams to the DM357 processor. One decoder and 1 on chip DAC channel forcomposite out are standard on the EVM. On screen display functions are implementedin software on the DM357 processor.

An on-board AIC33 codec allows the CPU to transmit and receive analog audio

signals. The I2C bus is used for the codec control interface, while the McBSP controlsthe audio stream. Signal interfacing is done through 3.5mm audio jacks that correspondto microphone input, line input, and line output. The codec can select the line input asthe active input.

The EVM includes 8 LEDs, IR interface, and Real time clock which can be used toprovide the user with interactive feedback. These interfaces are implemented via

software on a MSP430 and are accessed by reading and writing to the I2C registers.

SD/MMC Media card and ethernet MAC interfaces are integrated peripheral on theDM357 processor exploiting its system on a chip architecture.

An included 5V external power supply is used to power the board. On-board switchingvoltage regulators provide the +1.2V CPU core voltage and +3.3V for peripherals and+1.8V memory and DM357 I/O. The board is held in reset until these supplies arewithin operating specifications.

Code Composer Studio communicates with the EVM through an external emulator viathe 14 TI or 20 pin ARM external JTAG connector.



1.3 Basic Operation

The EVM is designed to work with TI’s Code Composer Studio IDETM, or standard GDBtool environments. Code Composer communicates with the board through an externalJTAG emulator.

Detailed information about the EVM including examples and reference material isavailable on the EVM’s CD-ROM.


1-5

1.4 Memory Map

The DM357 processor has a large byte addressable address space. However, somelimitations to byte addressing may be present depending on the board to deviceperipheral interconnection. Program code and data can be placed anywhere in theunified address space. Addresses are multiple sizes depending on hardwareimplementation. Refer to the appropriate device data sheets for more details.

The memory map shows the address space of a DM357 processor on the left withspecific details of how each region is used on the right.

The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces tothe DDR2 memory. The other EMIF has 4 separate addressable regions called chipenable spaces (CE2-CE5). The boot NAND Flash, or daughter card are mapped intoCE2 space and selectable via J4. Daughter cards use CE2 and CE3. When CE2 isused for daughter card interfacing J4 must be set appropriately. CE4 is used tointerface to storage NAND.

ARM Instruction RAM

DM357 EVMGeneric DaVinciAddress SpaceAddress

0x00000000

0x00040000

0x02000000

0x06000000

0x08000000

0x80000000

AEMIF CE3

AEMIF CE4

AEMIF CE5

DDR

Figure 1-2, Memory Map, DM357 EVM

ARM Instruction RAM

ARM Data RAM ARM Data RAM

AEMIF CE2 BootNAND

0x04000000DC

Storage NAND

DDR

Reserved



1.5 Configuration Switch Settings

The EVM has a single 10 position configuration switch that allow users to control theoperational state of the processor when it is released from reset. The configurationswitch is labeled S3 on the EVM board.

Switch S3 configures the boot mode that will be used when the processor startsexecuting. By default the switches are configured to EMIF boot (out of 8-bit NANDFlash) in little endian mode. The settings for switch S3 in chapter 3.

1.6 Power Supply

The EVM operates from a single +5V external power supply connected to the mainpower input (J14), a 2.5 MM. barrel-type plug. Internally, the +5V input is convertedinto +1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The+1.2V supply is used for the CPU core while the +3.3V supply is used for the CPU's I/Obuffers and other chips on the board. The +1.8 volt supply is used for DM357 I/O, lowvoltage memory, and peripherals, and DDR2 memory.

There are four power test points on the EVM; TP14, TP25, TP26, and TP43. These testpoints provide a convenient mechanism to check the EVM’s multiple power supplies.The table below shows the voltages for each test point and what the supply is used for.

Table 1: Power Test Points

Test Point Voltage Voltage Use

TP43 +1.2 V DM357 Core

TP25 +1.2 V DM357 Core/Power Down

TP26 +1.8 V DDR2 Memory, CPU I/O, and logic

TP14 +3.3V CPU I/O and logic

2-1

Chapter 2

Board Components

This chapter describes the operation of the major board components onthe DM357 EVM.

Topic Page

2.1 EMIF Interfaces 2-22.1.1 DDR2 Memory Interface 2-22.1.2 NAND Flash Interface 2-22.1.3 Storage NAND Interface 2-22.1.4 Memory Card Interface 2-22.1.5 UART Interface 2-32.1.6 EMIF Buffer/Decoder Control CPLD 2-32.2 Input Video Port Interfaces 2-42.2.1 On Chip Video Output DACs 2-42.2.2 AIC33 Interface 2-52.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator 2-62.3 Ethernet Interface 2-72.4 I2C Interface 2-72.4.1 I/O Expanders 2-82.4.2 MSP430 2-92.5 Daughter Card Interface 2-102.6 DM357 Core CPU Clock 2-102.7 USB Clock 2-102.8 Battery 2-11



2.1 EMIF Interfaces

A separate 16 bit EMIF with four chip enables divide up the address space and allowfor asynchronous accesses on the EVM. The EVM has a dedicates chip enables.CE2 is used for the boot NAND Flash. Both CE2 and/or CE3 can be routed to thedaughter card interface connectors. CE4 is used for storage NAND flash.

2.1.1 DDR2 Memory Interface

The DM357 device incorporates a dedicated 32 bit wide DDR2 memory bus. The EVMuses two gigabit 16 bit wide memories on this bus, for a total of 256 megabytes ofmemory for program, data, and video storage. The internal DDR controller uses aPLL to control the DDR memory timing. The interface supports rates up to 166 Mhz.,and is clocked on differential edges for optimal performance. Memory refresh for DDR2is handled automatically by the DM357 internal DDR controller.

2.1.2 Boot NAND Flash Interface

The DM357 has 64 megabytes of Boot NAND Flash mapped into the CE2 space. ThisNAND Flash memory is used for boot loading. The CE2 space is configured as 8 bitwide for NAND flash usage.

2.1.3 Storage NAND Interface

The EVM interfaces to 2 gigabytes of storage NAND flash mapped to CE4 space. CE4is configured to 8 bit wide access for storage NAND. The CPLD incorporates 1.8 to 3.3volt level translators to interface to the NAND.

2.1.4 Memory Card Interface

The EVM supports MMC/SD media cards via the on chip controller.

Table 1: EMIF Interfaces

Chip Select Function

CE2Boot NAND Flash

(see JP4 definition)

CE2Daughter Card Interface

(see JP4 definition)

CE3 Daughter Card Interface

CE4 Storage NAND Flash

CE5 Reserved


2-3

2.1.5 UART Interface

The internal UART0 on the DM357 device is driven to connector J6. The UART’sinterface is level shifted and routed to the RS-232 line drivers prior to being broughtout to a DB-9 connector, J6.

2.1.6 EMIF Buffer/Decoder Control CPLD

The EMIF buffer and decode functions are implemented with a CPLD. The EVM boardincorporates an Altera MAX II EPM240TCG100 device. The device has 2 banks ofI/O. One bank is used for +1.8 volt signals. The other bank is for+3.3 volt signals. This allows the device to do level shifting.

The CPLD incorporates the storage NAND level translators and decode interface alongwith a divide by 8 counter for video synchronization. The CPLD also incorporatesvarious glue logic for the EVM.

Div/8 Counter

Figure 2-1, DM357 CPLD Block Diagram

NAND

CPLD

1.8 Volt 3.3 VoltDomain Domain

3V3 Reset

EM_WAIT

3V3_EM

3V3 EM_CE4

1V8 Reset

EM_CLE

EM_ALE

EM_CE4

EM_RnW

EM_OE

EM_WRITZ

EM_D0-D7



2.2 Input Video Port Interfaces

The DM357 EVM supports video capture via the devices internal video ports. A TexasInstruments TVP5146 is used to decode composite video or S-video inputs into thedevice after being level shifted. J11 is used for the S-video inputs and J12 for thecomposite inputs on the EVM.

User inputs can be driven via daughter card connector DC4 when the on board leveltranslator is tristate via driving control Capture Enable signal high on DC4.

2.2.1 On Chip Video Output DACs

The DM357 incorporates 1 output DAC to interface to composite video. The DAC isbuffered via opamps and driven to connector, J8.


2-5

2.2.2 AIC33 Interface

The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output ofaudio signals. The codec samples analog signals on the microphone or line inputs andconverts them into digital data so it can be processed by the CPU. When the processoris finished with the data it uses the codec to convert the samples back into analogsignals on the line output so the user can hear the output.

The codec communicates using two serial channels, one to control the codec’s internal

configuration registers and one to send and receive digital audio samples. The I2C busis used as the unidirectional control channel. The control channel is generally only usedwhen configuring the codec, it is typically idle when audio data is being transmitted,

The McBSP is used as the bi-directional data channel. All audio data flows through thedata channel. Many data formats are supported based on the three variables ofsample width, clock signal source and serial data format. The EVM examples generallyuse a 16-bit sample width with the codec in master mode so it generates the framesync and bit clocks at the correct sample rate without effort on the processor side.

The codec has a programmable clock from a PLL1705 PLL device. The internal samplerate generator subdivides the default system clock to generate common audiofrequencies. The sample rate is set by a codec register. The figure below shows thecodec interface on the DM357 EVM.

Figure 2-2, DM357 EVM CODEC INTERFACE

DOUTDIN

BCLKWCLK

MIC IN

LINE IN

LINE OUT

HP OUT

McBSP

I2S Format

AIC33 Codec

Digital Analog

MIC IN

LINE IN

LINE OUT

HP OUT

SCLSDA

I2CControlSCL

SDAI2C Format

DRDXCLKRCLKXFSRFSX

Control Registers

ADC

DAC



2.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator

The DM357 EVM implements a multiple PLL clock generator for creating the Audioclocks for the board.

In streaming video applications the audio and video sequences can losesynchronization. The DM357 uses a VCXO interpolation circuit to incrementally speedup or slow down the STCLK input to allow for this synchronization to remain locked.

The PWM0 and timer inputs on DM357 are used to control this feature. The PWM0 pindrives a PICX100-27W Voltage Controlled Oscillator which is divided by 8 in the CPLDand fed back into the timer input pin.

The STCLK is also a source clock for the PLL1705 programmable PLL device. Thisdevice creates the clocks for the AIC33 Codec, daughter card VIDCLK an AUDIOCLK.

The PLL1705 is programmable via an I2C and Expander U18. Software sequencing onthe I/O expander is required to interface correctly to the PLL1708’s programmableinputs.

The diagram below is a simplified diagram of this clocking scheme.

DM357

VCXOCircuit UsingPICX100-27

PLL1705

SCK03SCK02

MCK02MCK01

XT1

PWM0 IN

PLLMS

PLLMC

PLLMD

To I/O Expander

Figure 2-3, Audio PLL/VCXO Circuit/PLL1705 Clock Generator

STCLKTIMER

AUDIO_CLKSCK01SCK00

CPLD /8Counter

VID_CLK


2-7

2.3 Ethernet Interface

The DM357 integrates an ethernet MAC on chip. This interface is routed to the PHYvia CBT switches. The EVM uses an Intel LXT971 PHY. The 10/100 Mbit interface isisolated and brought out to a RJ-45 standard ethernet connector, P2. The PHY directly

interfaces to the DM357. The ethernet address is stored in the I2C serial ROM duringmanufacturing.

The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellowand indicate the status of the ethernet link. The green LED, when on, indicates link andwhen blinking indicates link activity. The yellow LED, when illuminated, indicates fullduplex mode.

When configuring the PHY use the high drive option in the PHY register 26 tocompensate for the routing length and extra capacitance of the CBT switches.

2.4 I2C Interface

The I2C bus on the DM357 is ideal for interfacing to the control registers of many

devices. On the DM357 EVM the I2C bus is used to configure the video decoder,

stereo Codec, I/O expanders, and communicate with the MSP430. An I2C ROM is alsointerfaced via the serial bus. The format of the bus is shown in the figure below.

The addresses of the on board peripherals are shown in the table below.

Table 2: I2C Memory Map

Device Address R/W Function

TVP5146 0x5D R/W Capture 1 Decoder

PCF 8574A 0x38 R/W LEDs

PCF 8574A 0x39 R/W PLL/User Switch

PCF 8574A 0x3A R/W Peripheral Selects

TLV320AIC33 0x1B R/W CODEC

24WC256 0x50 R/W I2C EEPROM

MSP430 0x23 R/W LEDs, IR, RTC

Figure 2-4, I2C Bus Format

Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop

Write Sequence

Start Slave Address R Data STOP

Read Sequence



2.4.1 I/O Expanders

The DM357 EVM uses three I2C expanders to handle various bit I/O functions. Eachof these is an bit I/O expander, a PCF8574A. At Power Up Reset the expanders areinitialized to 0xFF, all ones. The functions for each of the I/O expanders are shown inthe tables below.

* - useful as input only High Input - Switch in “ON” Position Low Input - Switch in “OFF” Position

Table 3: U2, I/O Expander

Pin Number Function States

P0 User LED DS8 0 = Turns LED On, 1 = Turns LED Off









Pin Number Function

P0 PLL Program Interface, PLL CSEL Pin

P1 PLL Program Interface, PLL SR Pin

P2 PLL Program Interface, PLL FS1 Pin

P3 PLL Program Interface, PLL FS2 Pin

P4 Spare IO1

P5 Spare IO2

P6 Spare IO3

P7 User DIP Switch *


2-9

2.4.2 MSP430

The DM357 EVM incorporates infrared remote, real time clock, and some bit I/O in a

MSP430 microcontroller. The I2C interface is used on the DM357 processor to

communicate to the MSP430. The MSP430 acts as a slave device on the I2C bus.


Pin Number Function State

P0 Reserved

P1 VDD IMX Enable 0 = Disables VDDIMX supply

P2 Reserved

P3 Reserved

P4 Reserved

P5 Reserved

P6 Reserved

P7 Reserved



2.5 Daughter Card Interfaces

The EVM provides expansion connectors that can be used to accept plug-in daughtercards. The daughter card allows users to build on their EVM platform to extend itscapabilities and provide customer and application specific I/O. The expansionconnectors are for all major interfaces including memory, peripherals, and videoexpansion.

Spectrum Digital produces the THS8200 daughter card (part # 7xxxxx) which plugsonto the connector.

The pin outs for this interface are documented in Section 3.

The memory connector provides access to the CPU’s EMIF signals to interface withmemories and memory mapped devices.

The video capture port is brought out to the daughter card interface. Four signals areused to disable the on board video peripherals so that they can be used by theexpansion connector. The table below indicates the operation of these signals.

Other than the buffering, most daughter card signals are not modified on the board.

2.6 DM357 Core CPU Clock

The DM357 EVM uses a 27 Megahertz crystal to generate the input clock. TheDM357 has an internal PLL which can multiply the input clock to generate the internalclock. The PLL multiplier is set via software on the DM357 device.

2.7 USB Clock

The DM357 EVM uses a 24 Mhz crystal for the USB II clock generator. The USBcontroller is completely integrated in the DM357 device.

Table 6: Daughter Card Video Enable

SignalState To Enable Daughter Card

UseDM357 Signals Enables

CAPTURE_EN 1DC4 YI0-YI7 PCLK,VD,HD

McBSP_EN 1 DC3 McBSP

ENET_ENABLE 1 DC2 GIOV33 pins


2-11

2.8 Battery

The DM357 EVM incorporates a battery holder to provide backup power to theMSP430’s real time clock when the power is not applied to the board. The optionalbattery should be +3 volt 20 millimeter coin type Lithium single cell.

Some common part numbers for batteries which should operate in the EVM are shownin the table below.

These batteries are available from Duracell, Eveready, Panasonic, Ray-O-Vac, Sanyo,Sony, Sieko, Toshiba, Varta, and other battery manufacturers.

Table 7: Battery Part Numbers

Part Numbers

CR2032

DL2032

BR2032

CR2025

BR2025

CR2016

BR2016

DL2016

3-1

Chapter 3

Physical Description

This chapter describes the physical layout of the DM357 EVM and itsinterfaces.

Topic Page

3.1 Board Layout 3-33.2 Connectors 3-43.2.1 J2, MSP430 JTAG Header 3-53.2.2 J3, SD/MMC Connector 3-53.2.3 J4, EM_CS2 Routing Connector 3-63.2.4 J6, External RESET Interface 3-63.2.5 J7, USB Host/Gadget Termination 3-73.2.6 J8, Video Out 3-73.2.7 J9, USB Capacitance Select 3-83.2.8 J10, MiniAB USB Connector 3-93.2.9 J11, Composite Video In 3-103.2.10 J12, RCA Jack, Video In 3-113.2.11 J13, 14 Pin TI JTAG Emulation Header 3-123.2.12 J14, +5 Volt Input 3-133.2.13 J15, 20 Pin ARM JTAG Emulation Header 3-133.2.14 J17, CPLD Programming Header 3-143.2.15 J18, MSP430 I/O 3-143.2.16 J19, I2C Bus Expander 3-153.2.17 P2, Ethernet Interface 3-153.2.18 P3, Stereo Line In 3-163.2.19 P4, Headphone Out 3-173.2.20 P5, Stereo Line Out 3-173.2.21 P6, RS-232 UART 3-183.2.22 U3, Infrared Interface 3-19



Topic Page

3.3 Daughter Card Connectors 3-193.3.1 DC1, EMIF Expansion Connector 3-203.3.2 DC2, EMAC/GIO Connector 3-213.3.3 DC3, McBSP/SPI Expansion 3-223.3.4 DC4, Video Input expansion 3-233.3.5 DC5, Video Output Expansion 3-243.3.6 DC6, SD Interface Expansion 3-253.3.7 DC7, Power Expansion 3-253.4 LEDs 3-263.5 Switches 3-263.5.1 S1, EMU0/1 Select Switch 3-273.5.2 S3, Processor Configuration/Boot Load Options 3-283.5.3 S4, RESET 3-293.5.4 S5, User CPLD Option Switch 3-293.5.5 SW1, Power On/Off 3-293.6 Test Point Connector, JP1 3-303.7 Test Points 3-31


3-3

3.1 Board Layout

The DM357 EVM is a 6.75 x 10.0 inch (171 x 254 mm.) ten (10) layer printed circuitboard which is powered by an external +5 volt only power supply. Figure 3-1 shows thelayout of the DM357 EVM.

Figure 3-1, DM357 EVM, Interfaces Top Side

SW1

J7

J8

J9

J12

J11

J10 DC1

J15

J14

J4

J2

S4

DC6

DC2

DC3

DC4

DC5

P3

P4

P5

P2

P6

BHT1

S1

U3

DS10

DC7

S3

DS9

DS1-DS8

J6

J13

S3

J3

JP1

J19

J18

J17

S5



3.2 Connectors

The EVM has twenty-nine (29) connectors or interfaces to various peripherals. Theseconnectors are described in the following sections.

Table 1: Connectors

Connector Size Function

J2 2 x 7 MSP430 JTAG

J3 24 SD/MMC

J4 2 x 2 EM_CS2 Routing

J6 2 External RESET Input

J7 2 USB Host/Client Termination

J8 RCA Video Out

J9 1 x 3 USB Capacitance Select

J10 4 MiniAB USB

J11 4 Pin DIN Composite Video In

J12 RCA Video In

J13 2 x 7 14 Pin TI Emulation Header

J14 2.5 mm +5 Volt Input

J15 2 x 10 20 Pin ARM Emulation Header

J17 5 x 2 CPLD ProgrammingHeader (Factory Use)

J18 1 x 8, 2mm MSP430 I/O

J19 1 x 8, 2mm I/O Header

P2 RJ-45 Ethernet

P3 Dual RCA Stereo Line In

P4 3.5 mm Headphone Out

P5 Dual RCA Stereo Line Out

P6 9 RS-232 UART

DC1 2 x 35 EMIF Expansion

DC2 2 x 20 EMAC/GIO Expansion

DC3 2 x 15 McBSP/SPI Expansion

DC4 2 x 25 Video Input Expansion

DC5 2 x 25 Video Output Expansion

DC6 2 x 5 SD Expansion

DC7 2 x 5 Voltage Expansion

U3 IR Interface


3-5

3.2.1 J2, MSP430 JTAG Header

The J2, MSP430 JTAG header, is used to provide a programming interface to theMSP430 microcontroller. The pinout for the J2 connector is shown in the table below.

3.2.2 J3, SD/MMC Connector

The J3 SD/MMC connector is used to provide an interface to a SD/MMC card. Thepinout for the J3 connector is shown in the table below.

Table 2: J2, MSP430 JTAG Header

Pin # Signal Pin # Signal

1 430_TDO 2 NC

3 430_TDI 4 MSP430_3V3

5 430_TMS 6 NC

7 430_TCK 8 430_TEST/VPP

9 GND 10 NC

11 NC 12 NC

13 NC 14 NC

Table 3: J3, SD/MMC Connector


1 SD_DATA3 2 SD_CMD

3 GND 4 VCC_3.3V

5 SD_CLK 6 GND

7 SD_DATA0 8 SD_DATA1

9 SD_DATA2 10 GND



3.2.3 J4, EM_CS2 Routing Connector

The J4 connector is actually a 4 position jumper that is used to select the type ofmemory that the EM_CS2 signal is routed to. The EM_CS2 can be routed to either ofthe two signals shown in the figure below. Only one (1) device can be selected at atime. To reconfigure this signal, power down the EVM, change the jumper, and thenpower the board back up. Do NOT change this jumper with the power on. The pin outsare shown in the table below.

The figure below shows the two possible selections.

3.2.4 J6, External RESET Interface

The J6 connector is a 2 position jumper is used to externally reset the board. Thisconnector is unpopulated as shipped from the factory. This circuitry parallels theRESET switch, S4. The figure below represents this connector.

Table 4: J4, EM_CS2 Routing Connector


1 EM_CS2 3 NAND_CEz

2 EM_CS2 4 DC_EM_CS2

DC_EM_CS2, DC1, Pin 60

EM_CS2

Figure 3-2, J4, CS2 Routing

1

2

3

4

NAND_CEz, U6, Pin A4

SelectNAND

SelectDaughter Card

1J6

Figure 3-3, J6, External RESET Interface

GND

PBSW_RSTz

EX

T R

ES

ET


3-7

3.2.5 J7, USB Host/Gadget Termination

The J7 connector is a 3 position jumper that is used to select the termination for theUSB host/gadget configuration on USB connector J10. Either the +3.3V (1-2 position)for USB Gadget or Ground (2-3 position) for Host must be selected to properly enablethe mode of operation on the DM357 USB controller. To reconfigure this termination,power down the EVM, change the jumper, and then power the board back up. Do NOTchange this jumper with the power on. The figure below shows the signals on thisconnector.

3.2.6 J8, Video Out

The J8 connector is an RCA jack providing 1 DAC output. Do NOT plug into theseconnectors with the power on. This connector is driven by the signal DAC_IOUTAthrough the op-amp U50.The figure below shows this connector as viewed fromthe card edge.

J7

Figure 3-4, J7, USB Host/Gadget Termination

2 31

GN

D

+3.

3V

US

B_I

D

HostGadget

USB

Figure 3-5, J8, RCA Jack



3.2.7 J9, USB Capacitance Select

The J9 jumper is a 3 position jumper header of which only pins 1 and 2 are used. Thisjumper is used to provide more capacitance when the USB connector is used in thehost mode. When the jumper is shorted the extra capacitance is provided. Theseopen and shorted position are shown below.

Table 5: J9, USB Capacitance Select

Position Function

Open 6.8 uF Capacitance

Shorted 106.8 uF Capacitance

Figure 3-6, J9, USB Capacitance Select Open Shorted

1

J9

1

J9


3-9

3.2.8 J10, MiniAB USB Connector

Connector J10 is a mini A/B USB connector. The pinout for the J10 connector is shownin the table below.

The EVM incorporates the ability to toggle the ID pin on the USB connector viasoftware control. The USB_ID pin on the DM357 controls this function.

For “USB ON The Go” mode remove header J7. This will allow the cable to configurethe ID pin on the DM357 processor.

The EVM supplies up to 500 mA of current to the USB_VBUS via a TPS2065D DC/DCconverter. This is enabled via the DM357’s DRV_VBUS pin. J9 supplies extracapacitance for host mode operations.

Table 6: J10, MiniAB USB Connector

Pins Signal

1 USB_VBUS_CONN

2 USB_DM

3 USB_DP

4 USB_ID

5-9 USB_SHIELD/GND



3.2.9 J11, Composite Video In

Connector J11 is a four pin mini-din connector which interfaces to the TVP5146encoder. This connector brings in a video signal (LUMA) to pin 9 on the TVP5146. Do NOT plug into this connector with the power on. The figure below shows thisconnector as viewed from the card edge.

Table 7: J11, Video In, Mini-Din Connector

Pin # Signal Name

1 GND

2 GND

3 LUMA

4 Chroma

Pin 1 Pin 2Pin 3 Pin 4

Figure 3-7, J11, Front View, Mini-Din Connector


3-11

3.2.10 J12, RCA Jack, Video In

J13 is an RCA jack used as the CVBS/Y input to the TVP5146. The figure below showsthis connector as viewed from the card edge.

Table 8: J12, Video In RCA Jack

Pin # Signal Name

1 DEC_GND

2 VI_2_B, U51, Pin 8, TVP5146

3 DEC_GND

2 DEC_GND

Figure 3-8, J12, Video In RCA Jack

Pin 1,3,4 Shield (ground)

Pin 2, Signal Input



3.2.11 J13, 14 Pin TI JTAG Emulation Header

Connector J13 is a 2 x 7 double row male header with pin 6 clipped to serve as a key.This is the standard interface used by JTAG emulators to interface to TexasInstruments processors. The pinout for the connector is shown in the figure below.

The signal names for each pin are shown in the table below.

* Note: EMU0/EMU1 mode must be selected to ICEPICK mode

Table 9: J13, 14 Pin External JTAG Connector

Pin # Signal Name Pin # Signal Name

1 TI TMS 2 TI TRSTn

3 TI TDI 4 GND

5 TI PWR DECT 6 no pin - key

7 TI TDO 8 GND

9 TI TCK RET 10 GND

11 TI TCK 12 GND

13 TI EMU0 14 TI EMU1

1 23 4

5 67 89 1011 1213 14

TMSTDI

PD (+3.3V)TDO

TCK-RET

TCKEMU0

TRST-GNDno pin (key)GNDGND

GNDEMU1

Header Dimensions

Pin-to-Pin spacing, 0.100 in. (X,Y)Pin width, 0.025-in. square post

Pin length, 0.235-in. nominal

Figure 3-9, J13, 14 Pin External JTAG Connector


3-13

3.2.12 J14, +5 Volt Input

Connector J14 is the input power connector. This connector brings in +5 volts to theEVM. This is a 2.5mm. jack. Inside of the jack is tied to On/Off power switch SW1. The other side is tied to ground and LED DS9. The figure below shows this connectoras viewed from the card edge.

3.2.13 J15, 20 Pin ARM JTAG Emulation Header

The J15 emulation header is used to provide an interface to generic ARM9 JTAGemulators. The pinout for this connector is shown in the table below.

Note: EMU0/EMU1 switch, S1, must be set to ARM mode. This is shown in the figurebelow. See section 3.5.1 for more details.

Table 10: J15, 20 Pin ARM JTAG Emulation Header


1 VCC_3V3 2 VCC_3V3

3 ARM_TRSTn 4 Ground

5 ARM_TDI 6 Ground

7 ARM_TMS 8 Ground

9 ARM_TCK 10 Ground

11 ARM_TCKRET 12 Ground

13 ARM_TDO 14 Ground

15 ARM_RSTn 16 Ground

17 NC 18 Ground

19 NC 20 Ground

PC Board

J14+5V

Ground

Front ViewFigure 3-10, J14, +5 Volt Input Connector

Figure 3-11, S1, EMU0/1 Select Switch EMU0

EMU1

H

H

L

LS1

ARM Mode

ElevatedActuator



3.2.14 J17, CPLD Programming Header

Connector J17 is a 10 pin header that provides a programming interface to theFPGA, U14. Do NOT plug into this connector with the power on. The table below showsthe signals on this connector. This connector is for factory use only. Reprogrammingthis CPLD affects the functionality of your EVM.

3.2.15 J18, MSP430 I/O

Connector J18 brings out the I/O lines from the MSP430. These lines are pulled up to+3.3 volts through RN22. The signals on this connector are shown in the table below.

Table 11: J17, CPLD Programming Header


1 ISR_TCK 2 GND

3 ISR_TDO 4 VCC_1.8V

5 ISR_TMS 6 NC

7 NC 8 NC

9 ISR_TDI 10 GND

Table 12: J18, MSP430 I/O

Pin # Signal

1 P2.2/CAOUT/TAO

2 P2.3/CA0/TA1

3 P2.4/CA1/TA2

4 P3.0/STE0/A5

5 P3.1/SIMO0

6 P3.2/SOMI0

7 P3.3/UCLK0

8 P3.7/A7


3-15

3.2.16 J19, I2C Bus Expander

Connector J19 brings out the lines from U35, PCF8574A, the remote 8 bit expander for

the I2C bus. The signals on this connector are shown in the table below.

3.2.17 P2, Ethernet

The P2 connector is used to provide an Ethernet interface. P2 integrates the magneticsand standard RJ-45 connector. The two tables below show the signals present on themagnetics interface and the connector side.

Table 13: J18, I2C Bus Expander

Pin # Signal

1 PIO 0, U35, Pin 4

2 VDDIMX EN, U35, Pin 5

3 PIO 2, U35, Pin 6

4 PIO 3, U35, Pin 7

5 PIO 4, U35, Pin 9

6 PIO 5, U35, Pin 10

7 PIO 6, U35, Pin 11

8 PIO 7, U35, Pin 12

Table 14: P2, Magnetics/LEDs Interface Signals


1 TX+, U58, Pin 19 2 TX-, U58, Pin 20

3 RX+, U58, Pin 23 4 TXD-CT, U58, Pin 22

5 RXD-CT, NC 6 RXD-, U58, Pin 24

7 NC1 8 GND

9 LED1+ 10 LED1-

11 LED2+ 12 LED2-



3.2.18 P3, Dual Stereo Line In

The P3 connector is provides a stereo input (lower) and microphone input (upper) tothe TVL320AIC331 on the EVM. A view of the connector from the card edge is shownin the figure below. The signals present on this connector are defined in the followingtable.

Table 15: P3, Dual Stereo Line In

Pin # Signal Input

1 Isolated Ground Mic

2 MIC3L/MIC3R, U52, Pins A1,B3 Mic

3 MIC3L/MIC3R, U52, Pins A1,B3 Mic

4 Isolated Ground Line In

5 LINE1R+/LINE2R+, U52, Pins B4,B7 Line In

6 LINE1L+/LINE2L+, U52, Pins A4,A6 Line In

Figure 3-12, P3, Dual Stereo Line In

MIC

Stereo Line In

(upper)

(lower)


3-17

3.2.19 P4, Headphone Out

The P4 connector is a 3.5 mm. stereo headphone output from the TVL320AIC331ZQE,U52, on the EVM. A view of the connector from the card edge is shown in the figurebelow.

The signals present on this connector are defined in the following table.

3.2.20 P5, Stereo Line Out

The P5 connector is a dual output RCA jack bringing audio from the TVL320AIC331 onthe EVM. A view of the connector from the card edge is shown in the figure below. Thesignals present on this connector are defined in the following table.

Table 16: P4, Headphone Out Interface

Pin # AIC331 Signal

1 GND

2 HPLOUT, U52, Pin D1

3 HPROUT, U52, Pin G1

4 NC

Table 17: P5, Stereo Line Out

Pin # Signal

1 Isolated Ground

2 LEFT_LO+, U52, Pin J4

3 RIGHT_LO+, U52, Pin J6

Figure 3-13, P6, Headphone Out Interface

Headphone Out

Figure 3-14, P5, Stereo Line Out

WHITE

RED



3.2.21 P6, RS-232 UART

The P6 connector is a 9 pin make D-connector which provides a UART interface to theEVM. This connector interfaces to the MAX 3221 RS-232 line driver (U64) and islocated on the top side of the board. A view of the connector from the card edge isshown in the figure below. The signals present on this connector are defined in thefollowing table.

The pin numbers and their corresponding signals are shown in the table below. Thiscorresponds to a standard dual row to DB-9 connector interface used on personalcomputers.

Table 18: P6, UART Pinout

Pin # Signal Name Direction

1 NC N/A

2 S_A_RXD In

3 S_A_TXD Out

4 NC N/A

5 GND N/A

6 NC N/A

7 Connected to pin 8 Out

8 Connected to pin 7 Out

9 NC N/A

10,11 Earth Ground N/A

9

5 4 3 2 1

8 7 6

Figure 3-15, P6, DB9 Male Connector


3-19

3.2.22 U3, Infrared Interface

U3 is an infrared receiver mounted on the edge of the board. This device interfaces tothe MSP430 mircrocontroller. The view of U3 is shown from a board edge view in thefigure below.

The receiver supports interaction with an Infrared remote control included with yourEVM.

3.3 Daughter Card Connectors

The EVM has seven connectors that are available for daughter card connections.These connectors make many of the signals on the EVM available to be used byexternal logic. The signals on each of the connectors are described in the followingtables. The table below lists the connectors.

Table 19: U3, Infrared Interface

U3 Pin # MSP430 Signal, Pin #

1 P1.2/TA1, U4, Pin 23

2 GND

3 VCC_3V3

Table 20: Daughter Card Connectors

Connector Size FunctionSchematic

Page

DC1 2x35 EMIF 29

DC2 2x20 GIOV33/Ethernet 31

DC3 2x15 SPI, McBSP, I2C 31

DC4 2x20 Video In 30

DC5 2x25 Video Out 30

DC6 2x5 SD Interface 31

DC7 2x5 Power 35

Figure 3-16, U3, IR Interface, Card Edge View

U3

PC Card



3.3.1 DC1, EMIF Expansion Connector

Table 21: DC1, EMIF Expansion Connector


1 EM_A21 2 EM_A20

3 EM_A19 4 EM_A18

5 EM_A17 6 EM_A16

7 EM_A15 8 EM_A14

9 GND 10 GND

11 EM_A13 12 EM_A12

13 EM_A11 14 EM_A10

15 EM_A9 16 EM_A8

17 EM_A7 18 EM_A6

19 GND 20 GND

21 EM_A5 22 EM_A4

23 EM_A3 24 CLE_EM_A2

25 ALE_EM_A1 26 EM_A0

27 GND 28 GND

29 GPIO51 30 GPIO52

31 EM_BA1 32 EM_BA0

33 WRITE_WE 34 READ_OE

35 WAIT/BUSY 36 EM_RNW

37 GND 38 GND

39 EM_D15 40 EM_D14

41 EM_D13 42 EM_D12

43 EM_D11 44 EM_D10

45 GND 46 GND

47 EM_D9 48 EM_D8

49 EM_D7 50 EM_D6

51 EM_D5 52 EM_D4

53 GND 54 GND

55 EM_D3 56 EM_D2

57 EM_D1 58 EM_D0

59 EM_CS3 60 DC_EM_CS2

61 1.8V.SYS_RESETz 62 CLKOUT0

63 GND 64 GND

65 VCC_3.3V 66 VCC_3.3V

67 GND 68 GND

69 VCC_5V 70 VCC_1.8V


3-21

3.3.2 DC2, EMAC/GIO Connector

Table 22: DC2, EMAC/GIO Connector


1 GND 2 GND

3 GIOV33_0 4 GIOV33_1

5 GIOV33_2 6 GIOV33_3

7 GIOV33_4 8 GIOV33_5

9 GND 10 GND

11 GIOV33_6 12 GIOV33_7

13 GIOV33_8 14 GIOV33_9

15 GIOV33_10 16 GIOV33_11

17 GND 18 GND

19 GIOV33_12 20 GIOV33_13

21 GIOV33_14 22 GIOV33_15

23 GIOV33_16 24 GND

25 GND 26 3V3.SYS_RESETz

27 ENET_ENABLEz 28 GND

29 VCC_1.8V 30 3V3.UART_RXD1

31 VCC_1.8V 32 3V3.UART_TXD1

33 GND 34 GND

35 VCC_3.3V 36 VCC_3.3V

37 VCC_5V 38 VCC_5V

39 GND 40 GND



3.3.3 DC3, McBSP/SPI Expansion

Table 23: DC3, McBSP/SPI Expansion


1 SPI_EN1 2 SPI_EN0

3 SPI_DI 4 SPI_DO

5 SPI_CLK 6 TIMER_IN_DC3

7 GND 8 GND

9 DR 10 DX

11 CLKR 12 CLKX

13 FSR 14 FSX

15 GND 16 GND

17 1.8V.SYS_RESETz 18 1.8V.I2C_CLK

19 McBSP_EN 20 1.8V.I2C_DATA

21 AUDIO_CLK 22 GND

23 GND 24 1.8V_DC3_PCLK

25 VCC_3.3V 26 VCC_3.3V

27 GND 28 GND

29 VCC_5V 30 VCC_1.8V


3-23

3.3.4 DC4, Video Input Expansion

Table 24: DC4, Video Input Expansion


1 1.8V.SYS_RESETz 2 CAPTURE_EN

3 GND 4 GND

5 GIO1 6 GIO4

7 GND 8 GND

9 PWM1 10 PWM2

11 GND 12 GND

13 Y10 14 Y11

15 Y12 16 Y13

17 Y14 18 Y15

19 Y16 20 Y15

21 GND 22 GND

23 GND 24 HD

25 PCLK/1V8.DC_PCLK 26 VD

27 GND 28 GND

29 CI0 30 CI1

31 CI2 32 CI3

33 CI4 34 CI5

35 CI6 36 CI7

37 GND 38 GND

39 1V8.I2C_CLK 40 1V8.I2C_DATA

41 VCC_1.8V 42 VCC_1.8V

43 GND 44 GND

45 VCC_3.3V 46 VCC_3.3V

47 GND 48 GND

49 VCC_5V 50 VCC_5V



3.3.5 DC5, Video Output Expansion

Table 25: DC5, Video Output Expansion


1 GIO0 2 GIO2

3 GIO3 4 GIO5

5 GIO6 6 GIO38

7 GND 8 GND

9 COUT0 10 COUT1

11 COUT2 12 COUT3

13 COUT4 14 COUT5

15 COUT6 16 COUT7

17 GND 18 GND

19 VPBECLK/VID_CLK 20 HSYNC

21 GND 22 GND

23 VCLK 24 VSYNC

25 GND 26 GND

27 YOUT0 28 YOUT1

29 YOUT2 30 YOUT3

31 YOUT4 32 YOUT5

33 YOUT6 34 YOUT7

35 GND 36 GND

37 1.8V.I2C_CLK 38 1.8V.SYS_RESETz

39 1.8V.I2C_DATA 40 GND

41 VCC_1.8V 42 VCC_1.8V

43 GND 44 GND

45 VCC_3.3V 46 VCC_3.3V

47 GND 48 GND

49 VCC_5V 50 VCC_5V


3-25

3.3.6 DC6, SD Interface Expansion

3.3.7 DC7, Power Expansion

Table 26: DC6, SD Interface Expansion


1 SD_CLK 2 SD_CMD

3 GND 4 GND



9 GND 10 GND

Table 27: DC7, Power Expansion


1 VDDIMX_EN 2 GND

3 CORE_SUPPLY 4 CORE_SUPPLY

5 GND 6 GND

7 VCC_1.8V 8 VCC_1.8V

9 GND 10 GND



3.4 LEDs

The EVM has ten (10) LEDs which are located on the top side of the board. Eight of

these LEDs (DS1-8) are under user control and addressed over the I2C bus. One LED(DS9) indicates the presence of +5 volts on the board. The remaining LED (DS10)is tied to the CPLD, U14, B2.PIN86, and +3.3 volts. Additional information regardingthe LEDs are shown in the table below.

3.5 Switches

The EVM has five (5) switches. The function of these switches are shown in the tablebelow.

Table 28: LEDs

LED # Use ColorSchematic

Page

DS1 User Defined Green 23








DS9 +5V Green 29

DS10 +3.3V, U14, B2.PIN86 Red 14

Table 29: Switches

Switch Function TypeSchematic

Page

S1 EMU0/1 Selection DIP 28

S3Boot Configuration

Options DIP10

S4 RESET Push button 29

S5 Pull Ups DIP 14

SW1 Power On/Off Toggle 29


3-27

3.5.1 S1, EMU0/1 Select Switch

S1 is a 2 position DIP switch providing 2 options in selecting the state of the EMU0 andEMU1 pins on the processor. A view of the switch is shown in the figure below. Theselection options with this switch are in the table below.

* is the factory shipped configuration

Table 30: S1, EMU0/1 Select

State at ResetEMU0 EMU1

Function TAP Configuration

L L Emulation Debug ARM JTAG Enabled(20 pin JTAG connector)

14 bit = (Bypass(6) + ARM9(4) + Bypass(4)

L H Not Defined

H L Not Defined

H H TI Emulation Debug *ICE PICK Mode

6 bit = ICE PICK

Figure 3-17, S1, EMU0/1 Select Switch EMU0

EMU1

H

H

L

L

S1 ElevatedActuator



3.5.2 S3, Processor Configuration/Boot Load Options

S3 is a 10 position DIP switch providing 9 options in selecting the processorconfiguration and boot load modes. The connections for this switch are shown on page10 of the schematics in appendix A. A view of the switch is shown in the figure below.The selection options with this switch are in the table below.

AEAW4:0 configure address pins required to boot. See the tables in the device datasheet for more information. For the DM357 all address active are selected.

Table 31: S3, Processor Configuration/Boot Load Options

Position Name Function

1 COUT0 0 0 = Boot from ROM (NAND) *0 1 = Boot from AEM IF1 0 = Boot from ROM (HPI)1 1 = Boot from ROM (UART)

2 COUT1

3 COUT2 Selects AEMIF CS2 Bus width: 0=8 bit *, 1=16 bit

4 COUT3 Always Low

5 YOUT4 AEAW4

6 YOUT3 AEAW3

7 YOUT2 AEAW2

8 YOUT1 AEAW1

9 YOUT0 AEAW0

10 Composite Video Format

Figure 3-18, S3, Processor Configuration/

COUT0S3

ON1

23

45

67

89

10

COUT1

COUT2

COUT3

YOUT4

YOUT3

YOUT2

YOUT1

YOUT0

Boot Load Options

Logic “1”Switch ON

Logic “0”Switch “OFF”

ElevatedActuator


3-29

3.5.3 S4, RESET

Switch S4 is a push button rest switch that will RESET the processor. This switch is inparallel with J6. The connections for this switch are shown on page 29 of theschematics in appendix A.

3.5.4 S5, User CPLD Option Switch

Switch S5 is a 2 position DIP switch that allows the user to select options on thePIN74 and PIN75 pins of the CPLD, U14. This switch is not used on the DM357 asshipped from the factory. This switch appears on page 14 of the schematics. Thediagram below shows which position is associated with each signal.

3.5.5 SW1, Power On/Off

Switch S1 is a toggle switch that provides power to the EVM. The connections for thisswitch are shown on page 29 of the schematics in appendix A.



3.6 Jumper Block, JP1

The DM357 EVM has 6 position jumper that is not populated. This connector is used fortest points on the CPLD internal operations during CPLD debug. The layout of thejumper block is shown below.

The signals on each pin are shown in the table below.

Table 32: Jumper Block, JP1


1 U14, PIN92 2 U14, PIN95

3 U14, PIN91 4 U14, PIN96

5 U14, PIN90 6 U14, PIN97

7 U14, PIN89 8 U14, PIN98

9 U14, PIN88 10 U14, PIN99

11 U14, PIN87 12 U14, PIN100

21

JP1

Figure 3-20, Jumper Block, JP1


3-31

3.8 Test Points

The EVM has 72 test points. All test points appear on the top of the board. Thefollowing figure identifies the position of each test point. the next table list each testpoint and the signal appearing on that test point.

Figure 3-21, DM357 EVM, Test Points

TP1

TP6

TP20 TP17 TP18

TP13

TP34

TP40 TP38TP39

TP46

TP44

TP45

TP47

TP60

TP58

TP59

TP72

TP62

TP68

TP70

TP19

TP21

TP11

TP22

TP24

TP23

TP3

TP4

TP2

TP5

TP16

TP15

TP29

TP28

TP14

TP27

TP26

TP25

TP71

TP61

TP50-52

TP53-55

TP30

TP42

TP41

TP66,67

TP65,69

TP63,64

TP56,57

TP48,49

TP44

TP35,36

TP37,12

TP33

TP31,32

TP9,10

TP7,8



Table 33: DM357 EVM Test Points

TP # Signal Page TP # Signal Page

TP1 GND 29 TP37 U27, P4, PWRGD, VCC_5V 30

TP2 GND 29 TP38 GND 4

TP3 GND 29 TP39 U28A,T10, DDR_VDDDLL, 1.8V 4

TP4 U4, P24, P1.3/TA2 24 TP40 VCC_1.8V 4

TP5 VCC_5V 29 TP41 CORE_VDD 9

TP6 GND 4 TP42 U28D, M12, CPU_CORE_VDD 9

TP7 U28A, R8, RSV7 4 TP43 CORE_VDD 30

TP8 U28E, M2, PLLVDD18, VCC_1.8V 8 TP44 CORE_SUPPLY 30

TP9 GND 8 TP45 GND 4

TP10 U28E, L3, RSV6 8 TP46 U28H, H17, USB_VDDA1P8, VCC_1.8V 7

TP11 U28D, T5, CPU_VCC_1.8V, VCC_1.8V 9 TP47 VCC_1.8V 7

TP12 U38, P4, PWRGD, VCC_5V 30 TP48 VCC_3.3V 7

TP13 U44, P1, RESET 29 TP49 U28H, J19, USB_VDDA3P3.1, VCC_3.3V

7

TP14 +3.3V 29 TP50 U28G, P18, DAC_IOUT_B 5

TP15 U19, P6, PH1 29 TP51 U28G, R19, DAC_IOUT_C 5

TP16 U19, P4, PWRGD, 3V3_PWR_OK 34 TP52 U28G, T19, RSV45 5

TP17 GND 4 TP53 U28G, R18, VDDA_1P8V, VCC_1.8V 5

TP18 U28E, M3, RSV24, CORE_VDD 8 TP54 VCC_1.8V 5

TP19 VCC_1.8V 8 TP55 U28G, P16, VDDA_1P1V, CORE_VDD 5

TP20 CORE_VDD 8 TP56 U51,Pin 36, AVID/GPIO 20

TP21 VCC_1.8V 9 TP57 U51,Pin 37, GLCO/12CA 20

TP22 U28D, E13, CPU_VCC_3.3V, VCC_3.3V 9 TP58 U58,PIN 64,MDINT 22

TP23 U14, Pin 49, B1.PIN49 14 TP59 J10, Pin 4, USB_ID 17

TP24 U14, Pin 29, B1.PIN29 14 TP60 J10, Pin 1, USB VBUS 17

TP25 CORE_VDDMIX 30 TP61 CORE_VDD 5

TP26 VCC_1.8V 30 TP62 U51,Pin 30, INTREQ 20

TP27 GND 29 TP63 U52, A8, MPF2 22

TP28 VCC_3.3V 29 TP64 U52, A9,MPF3 22

TP29 U27, P6, PH1 30 TP65 U52, J8, GPIO2 22

TP30 CORE_VDDMIX 9 TP66 U28I, C15, PWM0/GIO45, VCC_1.8V 5

TP31 U28DM K11, CPU_CORE_VDDIMX 9 TP67 VIN, U54,PIN 3 5

TP32 VCC_3.3V 9 TP68 GND 29

TP33 U45, P1, RESET 29 TP69 U52, J9, GPIO1 22

TP34 U46, P1, RESET 29 TP70 GND 29

TP35 U38, P6, PH1 30 TP71 U68, Pin 4, USB.DRVVBUSz 17

TP36 VCC_1.8V 30 TP72 U68, Pin 5, USB.OVER_CURRENT 17

A-1

Appendix A

Schematics

This appendix contains the schematics for the DM357 EVM.


A-2 DM357 EVM Technical Reference

5 5

4 4

3 3

2 2

1 1

DD

CC

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lock

SCHEMATIC

CONTENTS

01 DM357 EVM TITLE SHEET

02 DM357 EVM BLOCK DIAGRAM

03 DM357 EMIF INTERFACE

04 DM357 DDR INTERFACE

05 DM357 VIDEO INTERFACE

06 DM357 I/O INTERFACE

07 DM357 USB & SD/MMC/MS CONTROLLER

08 DM357 EMULATION & CLOCKS

09 DM357 POWER PINS

10 DM357 CONFIGURATION CONTROL/BOOT OPTIONS

11 DDR2 MEMORY

12 BOOT NAND FLASH

13 STORAGE NAND FLASH

14 EMIF CPLD MULTIPLEXER

15 SD/MMC CONNECTOR

16 RS232 INTERFACE

17 USB 2.0 INTERFACE

18 ETHERNET INTERFACE

19 TVP5146 LEVEL SHIFTER

20 TVP5416 VIDEO DECODER

21 VIDEO OUT

22 AIC33 AUDIO INTERFACE

23 USER LEDS

24 MSP430 & IR INTERFACE

25 EMIF EXPANSION CONNECTOR

26 VIDEO INPUT/OUTPUT CONNECTORS

27 EMAC/GIO & McBSP/SPI & SD CONNECTORS

28 EMULATION HEADERS

29 POWER SUPPLY ( 3.3V ) & SYSTEM RESET LOGIC

30 POWER SUPPLY ( 1.8V & CPU_CORE) & EVM POWER CONNECTOR

REV

ENGR

2REVISION STATUS OF SHEETS

111

SH

DATE

14

12

13

DATE

ENGR-MGR

MFG

7

DWN

DATE

8

DATE

10

SH

DATE

CHK

RLSE

APPLICATION

REV

35

NEXT ASSY

DATE

6

DATE

9

QA

USED ON

4

15

AA

AA

AA

A

AA

AA

A

R.R.P.

T.W.K.

R.R.P.

R.R.P.

C.M.D.

R.R.P.

R.R.P.

02/17/2005

02/17/2005

16

17

18

19

20

21

22

23

24

25

02/17/2005

02/17/2005

03/01/2004

02/17/2005

02/17/2005

REV

SH

AA

AA

A

AA

A

AA

A

AA

AA

A

26

27

28

29

30

AA

AInitial schematic ready

for layout - Alpha Release

DESCRIPTION

REV

APPROVED

DATE

10/15/08

RRP

4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS

OTHERWISE NOTED. THEY ARE SHOWN

ON THE PAGE WITH THE INTEGRATED

CIRCUITS THEY SHOULD BE PLACED NEAR.

NOTES, UNLESS OTHERWISE SPECIFIED:

1. RESISTANCE VALUES IN OHMS.

2. CAPACTITANCE VALUES IN MICROFARADS.

3. REFERENCE DESIGNATORS USED:

5. OBSERVE THE FOLLOWING LAYOUT NOTES:

1. TOP - SIGNAL ROUTING

2. GROUND PLANE

3. INNER1 - SIGNAL ROUTING

4. VCC3 PLANE (3.3V BOARD)



7. VCC PLANE 2


9. GROUND PLANE

10. BOTTOM - SIGNAL ROUTING

6.

BOARD

PROPERTIES

B1. General layers 50 +/- 5 OHM MATCHED IMPEDANCE

C. OUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATING

D. INNER LAYERS 1.0 OZ CU

E. FR4 BOARD MATERIAL

F. MINIMUM TRACE WIDTH/SPACING 4 MILS

G. MINIMUM VIA SIZE 10/19 MIL

H. LAYER STACKUP:

A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE

B2. USB layer

90 ohm differential

I2CADDRESS TABLE

IO EXPANDER 0

IO EXPANDER 1

IO EXPANDER 2

I2C ROM

AIC33

TVP5146

MSP430

0x50

BASE

0x1B

0x5D

0x23

0x38

(LED)

0x39

(PLL/USER_SW)

0x3A

(USB/CD_RESET)

SHEET

22

20

23

24

24

24

6


A-3

5 5

4 4

3 3

2 2

1 1

DD

CC

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357

BL

OC

K D

IAG

RA

M

DM357

SH:3-9

DDR2 IF

SH:4

SH:12

NAND Flash (64MB)

SH:15

SD/MMC Connector

SH:21

(1) DAC Video Output

SH:26

DC #5 Connector

SH:26

DC #3 Connector

SH:7

Switch

SH:22

Stereo Codec

(AIC33)

SH:27

DC #3 Connector

SH:26

DC #4 Connector

SH:5

VCXO/PLL

(Audio & Video

Clock Generation)

SH:13

NAND Flash (1 OR 2 GB)

SH:14

1.8V to 3.3V

Level Shifters

SH:28

Emulator Header

SH:29

DC #1 Connector

SH:11

DDR2 SDRAM (256MB)

SH:17

USB 2.0 IF

SH:18

Ethernet IF

SH:26

DC #4 Connector

SH:31

DC #2 Connector

SH:18

Switch

SH:6

EEPROM

SH:22

(8) LEDs

SH:19

Level Shifter

& Switch

SH:16

UART

(Debug Term)

SH:20

Video Decoder

(TVP5146)

SH:24

MSP430

IR/RTC/SC

Emulator

SH:8

USB 2.0

SH:7

Image In

SH:5

UART1

SH:3

I2C SH:6

SH:6

EMAC/

GPIOs

UART0

SH:6

Config Control &

EM_CS2 Select

SH:10

Power Supply (3.3V)

& System Reset Logic

SH:29

Power Supply (1.8V & CPU Core)

& DC #7 Connector

SH:30

EMIF

SH:3

SD/MMC

SH:7

(3) DACs

SH:5

Video Out

SH:5

PWM0

SH:5

Timer In

SH:8

PWM [2:1]

SH:5

SPI SH:6

McBSP

SH:7

Power Pins

SH:9

SH:8

Crystal/Osc

SH:8

PLLs

1.8V to 3.3V

Level Shifters



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

_D

15

EM

_D

11

EM

_D

13

EM

_D

9

EM

_D

5

EM

_D

7

EM

_D

3

EM

_D

1

EM

_A21

EM

_A16

EM

_A18

EM

_A20

EM

_A14

EM

_A8

EM

_A6

EM

_A10

EM

_A4

EM

_A12

EM

_A19

EM

_A17

EM

_A15

EM

_A13

EM

_A11

EM

_A9

EM

_A7

EM

_A5

EM

_A3

EM

_D

14

EM

_D

12

EM

_D

8

EM

_D

4

EM

_D

6

EM

_D

2

EM

_D

0

EM

_D

10

CLE

_E

M_A

2A

LE_E

M_A

1E

M_A

0E

M_B

A1

EM

_BA

0

VC

C_

1.8

VV

CC

_1

.8V

CLE

_E

M_A

21

2,1

4,25

ALE

_EM

_A1

12

,14,

25E

M_A

01

4,2

5E

M_B

A1

14

,25

GP

IO52

14

,25

GP

IO51

14

,25

RE

AD

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2,1

4,2

5W

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4,2

5

EM

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S2

10

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EM

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S3

14

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EM

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4,2

5

UA

RT

_TX

D1

14

EM

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S5

14

EM

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S4

14

WA

IT/B

US

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4,2

5

EM

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NW

14

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RT

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114

EM

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92

5

EM

_D

112

5

EM

_D

132

5

EM

_D

152

5

EM

_D

11

2,1

4,2

5

EM

_D

31

2,1

4,2

5

EM

_D

51

2,1

4,2

5

EM

_D

71

2,1

4,2

5

EM

_D

102

5

EM

_D

122

5

EM

_D

142

5

EM

_D

01

2,1

4,2

5

EM

_D

21

2,1

4,2

5

EM

_D

41

2,1

4,2

5

EM

_D

61

2,1

4,2

5

EM

_D

82

5

EM

_A3

14

,25

EM

_A4

14

,25

EM

_A5

25

EM

_A6

25E

M_A

725

EM

_A8

25E

M_A

925

EM

_A10

25E

M_A

1125

EM

_A12

25E

M_A

1325

EM

_A14

25E

M_A

1525

EM

_A16

25E

M_A

1725

EM

_A18

25E

M_A

1925

EM

_A20

25E

M_A

2125

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35

7 E

MIF

IN

TE

RF

AC

E

R1

69

22

R1

79

22

RN

7R

PA

CK

8-1

0

1 2 3 4 5 6 7 8910111213141516

R1

722

2

R1

74

22

RN

9R

PA

CK

8-1

0

1 2 3 4 5 6 7 8910111213141516

U28

B

TM

S32

0D

M35

7

EM

_D14

/HD

14H

5E

M_D

13/H

D13

F2

EM

_D12

/HD

12D

1E

M_D

11/H

D11

G4

EM

_D10

/HD

10G

5E

M_D

09/H

D09

E2

EM

_D15

/HD

15E

1

EM

_D08

/HD

08F

3

EM

_D07

/HD

07C

1E

M_D

06/H

D06

F4

EM

_D05

/HD

05D

2E

M_D

04/H

D04

E4

EM

_D03

/HD

03E

3E

M_D

02/H

D02

F5

EM

_D01

/HD

01D

3E

M_D

00/H

D00

E5

EM

RW

n/H

RW

nG

3

EM

_WA

IT/(

RD

Y_B

US

Yn)

/HR

DY

nF

1

EM

_OE

n/R

En/

HD

S1n

H4

EM

_WE

n/W

En/

HD

S2n

G2

UA

RT

_TX

D1

H3

UA

RT

_RX

D1

G1

EM

_CS

5n/G

PIO

8T

1

EM

_CS

2n/H

CS

nC

2E

M_C

S3n

B1

EM

_CS

4n/G

PIO

9T

2

EM

_BA

1/G

PIO

52H

2

EM

_A2/

(CLE

)/H

CN

TL0

J1E

M_A

3/G

PIO

28K

2E

M_A

4/G

PIO

27K

4E

M_A

5/G

PIO

26K

3

EM

_A6/

GP

IO25

N1

EM

_A7/

GP

IO24

N2

EM

_A8/

GP

IO23

N3

EM

_A9/

GP

IO22

M4

EM

_A10

/GP

IO21

P1

EM

_A11

/GP

IO20

P2

EM

_A12

/GP

IO19

R1

EM

_A13

/GP

IO18

N4

EM

_A14

/GP

IO17

P4

EM

_A15

/GP

IO16

P3

EM

_A16

/GP

IO15

R5

EM

_A17

/GP

IO14

R2

EM

_A18

/GP

IO13

P5

EM

_A19

/GP

IO12

R4

EM

_A20

/GP

IO11

R3

EM

_BA

0/H

INT

nJ3

GP

IO52

J5G

PIO

51H

1

EM

_A21

/GP

IO10

T3

EM

_A1/

(ALE

)/H

HW

ILJ2

EM

_A0/

HC

NT

L1/G

PIO

53J4

R1

682

2

RN

8R

PA

CK

8-1

0

1 2 3 4 5 6 7 8910111213141516

RN

2R

PA

CK

8-1

01 2 3 4 5 6 7 8

910111213141516

R1

67

22R

18

022

R1

71

1K

R1

732

2

R1

75

22

RN

3R

PA

CK

8-1

0

1 2 3 4 5 6 7 8910111213141516

R1

61 1K

R2

032

2

R1

702

2


A-5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DD

R_

D8

DD

R_D

12

DD

R_D

14

DD

R_

D6

DD

R_D

25

DD

R_D

16

DD

R_D

26

DD

R_D

19

DD

R_D

21

DD

R_D

20

DD

R_D

22

DD

R_D

23

DD

R_D

28

DD

R_D

31

DD

R_D

27

DD

R_D

17

DD

R_D

29

DD

R_

D0

DD

R_

D1

DD

R_

D2

DD

R_

D3

DD

R_

D4

DD

R_

D5

DD

R_

D7

DD

R_

D9

DD

R_D

10

DD

R_D

11

DD

R_D

13

DD

R_D

15

DD

R_D

18

DD

R_D

24

DD

R_D

30

DD

R_

A0

DD

R_

A1

DD

R_

A2

DD

R_

A3

DD

R_

A4

DD

R_

A5

DD

R_

A6

DD

R_

A7

DD

R_

A8

DD

R_

A9

DD

R_A

10

DD

R_A

11

DD

R_A

12

DD

R_

BS

00

DD

R_

BS

01

DD

R_

BS

02 DD

R_

CS

DD

R_C

LK

DD

R_

CL

K_

N

DD

R_

DQ

S0

DD

R_

DQ

M0

DD

R_

DQ

S1

DD

R_

DQ

S2

DD

R_

DQ

S3

DD

R_

DQ

M3

BD

DR

_A

0

BD

DR

_A

3B

DD

R_

A4

BD

DR

_A

5B

DD

R_

A6

BD

DR

_A

7

BD

DR

_B

S02

BD

DR

_B

S01

BD

DR

_B

S00

BD

DR

_A

8B

DD

R_

A9

BD

DR

_A

10

BD

DR

_A

11

BD

DR

_A

12

BD

DR

_D

QS

0B

DD

R_

DQ

S1

BD

DR

_D

QS

2B

DD

R_

DQ

S3

BD

DR

_D

QM

0B

DD

R_

DQ

M1

BD

DR

_D

QM

2B

DD

R_

DQ

M3

BD

DR

_C

S

BD

DR

_C

LK

BD

DR

_C

LK

_N

BD

DR

_C

KE

DD

R_

DQ

M2

DD

R_

DQ

M1

VR

EF

_ST

L

BD

DR

_A

1B

DD

R_

A2

DD

R_

RA

S

DD

R_

CK

ED

DR

_W

E

DD

R_

CA

S

BD

DR

_W

E

BD

DR

_R

AS

BD

DR

_C

AS

VC

C_

1.8

V

DD

R_

D[0

:31

]11

DD

R_

A[0

:12

]11

DD

R_D

QM

011

DD

R_D

QS

211

DD

R_

CA

S11

DD

R_

CLK

11

DD

R_

CS

11

DD

R_

CL

K_

N11

DD

R_

WE

11D

DR

_R

AS

11

DD

R_

CK

E11

DD

R_D

QS

311

DD

R_D

QS

111

DD

R_D

QS

011

DD

R_D

QM

311

DD

R_

BS

02

11D

DR

_B

S0

111

DD

R_

BS

00

11

DD

R_D

QM

111

DD

R_D

QM

211

VR

EF

_ST

L1

1

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5114

52-0

001

Mo

nd

ay,

No

vem

be

r 0

3,

200

84

30

B

TM

S32

0DM

35

7 E

VA

LU

AT

ION

MO

DU

LE

DM

35

7

DD

R I

NT

ER

FA

CE

SURFACE MOUNT TEST POINT PADS

USED FOR VERIFYING DDR TIMINGS

ROUTE CLOCK DIFFERENTIAL WITH 15 MIL SPACING BETWEEN

PLACE RESISTOR BY DATA TERMINATOR PINS

BALANCE

LINE LENGTHS WITH DATA BYTES LENGTHS

R2

0420

0

R5

247

C1

89

0.1

uF

TP

39 1

R5

30

.22

R4

147

R1

8247

TP

171

RN

13

RP

AC

K4

-47

12345 6 7 8

TP

61

RN

11

RP

AC

K4

-47

12345 6 7 8

TP

381

RN

17

RP

AC

K4-

47

12345 6 7 8

R2

0647

R3

347

R2

0547

U2

8A

TM

S32

0DM

357

DD

R_A

00W

13

DD

R_A

01U

13

DD

R_A

02V

13

DD

R_A

03U

12

DD

R_A

04V

12

DD

R_A

05W

12

DD

R_A

06W

11

DD

R_A

07V

11

DD

R_A

08V

10

DD

R_A

09U

11

DD

R_A

10U

10

DD

R_A

11W

10

DD

R_A

12W

9

DD

R_B

S00

U8

DD

R_C

Sn

T9

DD

R_C

LK0n

W8

DD

R_W

En

T8

DD

R_C

LK0

W7

DD

R_C

KE

V8

DD

R_Z

PT

13

DD

R_Z

NT

12

DD

R_V

SS

DLL

T11

DD

R_V

DD

DLL

T10

DD

R_C

AS

nT

7

DD

R_R

AS

nU

7

DD

R_D

00U

1

DD

R_D

01U

2

DD

R_D

02V

1

DD

R_D

03V

2

DD

R_D

04W

2

DD

R_D

05U

3

DD

R_D

06V

3

DD

R_D

07W

3

DD

R_D

08V

4

DD

R_D

09W

4

DD

R_D

010

U5

DD

R_D

11V

5

DD

R_D

12W

5

DD

R_D

13V

6

DD

R_D

14W

6

DD

R_D

15V

7

DD

R_D

16W

14

DD

R_D

17V

14

DD

R_D

18W

15

DD

R_D

19V

15

DD

R_D

20U

15

DD

R_D

21W

16

DD

R_D

22V

16

DD

R_D

23T

17

DD

R_D

24V

17

DD

R_D

25U

17

DD

R_D

26U

18

DD

R_D

27W

17

DD

R_D

28V

18

DD

R_D

29W

18

DD

R_D

30V

19

DD

R_D

31U

19

DD

R_B

S01

V9

DD

R_B

S02

U9

RS

V7

R8

DD

R_D

QS

0U

4

DD

R_D

QS

1U

6

DD

R_D

QM

0T

4

DD

R_D

QM

1T

6

DD

R_D

QS

3U

16D

DR

_DQ

S2

U14

DD

R_D

QM

2T

14

DD

R_D

QM

3T

16

DD

R_V

RE

FT

15

RN

10

RP

AC

K4

-47

12345 6 7 8

RN

12

RP

AC

K4

-47

12345 6 7 8

R5

147

C2

160

.22

uF

R2

1920

0T

P40 1

R3

247

L10

BLM

21P

G22

1S

N1D

12

TP

71

TP

451

R2

2147

R2

180

C1

901

uF

R2

2047

R1

8147



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DA

C_

IOU

TA

DA

C_

IOU

TB

DA

C_

IOU

TC

VR

EF

_0

.5V

VR

EF

_1

.24V

VC

C_

1.8

V

VC

C_3

.3V

VC

C_

1.8

V

CO

RE

_V

DD

VC

C_

1.8

V

VC

C_

1.8

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_3

.3V

VC

C_

3.3

V

CO

UT

01

0,2

6

CO

UT

21

0,2

6

CO

UT

426

YO

UT

01

0,2

6

YO

UT

21

0,2

6

VS

YN

C26

CO

UT

11

0,2

6

CO

UT

31

0,2

6

HS

YN

C26

YO

UT

11

0,2

6

YO

UT

31

0,2

6

CO

UT

626

CO

UT

726

CO

UT

526

YO

UT

526

YO

UT

41

0,2

6

YO

UT

626

YO

UT

726

VP

BE

CLK

26

VC

LK

26

PW

M1

26

PW

M2

26

HD

19,

26

VD

19,

26

CI5

26

CI7

26

CI4

26

CI6

26

CI3

26C

I226

CI1

26C

I026

YI4

19,

26

YI6

19,

26

YI3

19,

26

YI5

19,

26

YI2

19,

26Y

I11

9,26

YI0

19,

26

PC

LK

19,

26

YI7

19,

26

DA

C_

IOU

TA

21

AU

DIO

_C

LK

22

,27

VID

_C

LK26

3V

3.D

C_P

CL

K14

PL

L.F

S2

24P

LL

.FS

124

PL

L.S

R24

PL

L.C

SE

L24

CP

LD_

TIM

ER

_IN

14

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

We

dn

esd

ay,

No

vem

ber

05

, 2

00

85

30

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

DM

35

7 V

IDE

O I

NT

ER

FA

CE

VREF =1.24 VOLTS

R2

394

.02K

R3

020

R30

010

K

R2

9133

C2

71

NO

-PO

P

TP

53 1

C2

720

.1u

F

C2

68

0.1

uF

C2

30

.1u

F

L21

BLM

21P

G2

21S

N1D

1 2

C3

10

NO

-PO

P

R6

30

.22

TP

511

U2

8G

TM

S32

0DM

357D

AC

_IO

UT

_AP

19

DA

C_I

OU

T_B

P18

DA

C_I

OU

T_C

R19

RS

V45

T19

VS

SA

_1P

1VT

18

VS

SA

_1P

8VP

17

DA

C_V

RE

FR

17

VD

DA

_1P

8VR

18

DA

C_R

BIA

SR

16

VD

DA

_1P

1VP

16

+C

71

10

uF

C2

67

0.1

uF

R2

9033

C3

110

.1u

F

R6

20

.22

TP

501

TP

55 1

Q1

2N

3904

R3

042

.2K

+C

66

10u

F

C2

351

uF

R2

97

33

R3

6533

R29

233

U5

7S

N7

4A

UC

1G1

25

3

4

5

2

1

C2

31

.00

1u

F

R2

322

2

C27

3

100

pF

TP

61 1

R29

3N

O-P

OP

U5

4

PI6

CX

100-

27W

X1

1X

28

GN

D4

VIN

3V

DD

6

CLK

OU

T5

NC

12

NC

27

R2

9610

K

R29

5N

O-P

OP

R2

342

2

U2

8I

TM

S3

20D

M35

7

CI7

/CC

D15

/UA

RT

_RX

D2

N19

CI6

/CC

D14

/UA

RT

_TX

D2

N18

CI5

/CC

D13

/UA

RT

_CT

S2

N17

CI4

/CC

D12

/UA

RT

_RT

S2

N16

CI3

/CC

D11

N15

CI2

/CC

D10

M17

CI1

/CC

D09

M16

CI0

/CC

D08

M15

YI7

/CC

D07

L18

YI6

/CC

D06

L17

YI5

/CC

D05

L16

YI4

/CC

D04

L15

YI3

/CC

D03

K19

YI2

/CC

D02

K18

YI1

/CC

D01

K17

YI0

/CC

D00

K16

PC

LKM

19

HD

M18

VD

L19

PW

M2/

B2/

GP

IO47

A15

PW

M1/

R2/

GP

IO46

B15

YO

UT

7/R

7E

18

YO

UT

6/R

6E

17

YO

UT

5/R

5E

16

YO

UT

4/R

4/A

EA

W4

E15

YO

UT

3/R

3/A

EA

W3

D18

YO

UT

2/G

7/A

EA

W2

D17

YO

UT

1/G

6/A

EA

W1

D16

YO

UT

0/G

5/A

EA

W0

D15

CO

UT

7/G

4C

16

CO

UT

6/G

3B

19

CO

UT

5/G

2B

18

CO

UT

4/B

7A

18

CO

UT

3/B

6/D

SP

_BT

B17

CO

UT

2/B

5/E

M_W

IDT

HA

17

CO

UT

1/B

4/B

TS

EL1

B16

CO

UT

0/B

3/B

T_S

EL0

A16

VC

LKD

19

VS

YN

CC

18

HS

YN

CC

17

VP

BE

CLK

C19

PW

M0/

GP

IO45

C15

R2

99

10K

R2

362

2

R29

4N

O-P

OP

RN

18

RP

AC

K8-

33

123456789 10 11 12 13 14 15 16

R2

417

.5K

U5

6S

N7

4AU

C1

G1

25

3

4

5

2

1

R36

633

RN

21

RP

AC

K8-

33

123456789 10 11 12 13 14 15 16

TP

66

1

C3

12

10

pF

R3

071

K

R3

01

NO

-PO

P

TP

54 1

R3

052

2.1

K 1

%

+C

65

10u

FC

23

3.0

01

uF

R3

03

100

K

C2

65

0.1

uF

C2

70

0.1

uF

C26

9

0.1

uF

R1

942

2

R2

9810

K

L22

BLM

21P

G2

21S

N1D

1 2

TP

521

C2

66

0.1

uF

C2

32

.1u

F

R2

162

2

U3

9

TLV

431A

DB

V

53

4

R2

44

NO

-PO

P

C2

34

.1uF

Y5

27M

Hz

U5

5

PLL

1705

VD

D1

1V

DD

213

XT

110

XT

211

VD

D3

20

VC

C8

DG

ND

14

DG

ND

216

SR

7

FS

26

FS

15

SC

KO

119

AG

ND

9

DG

ND

317

SC

KO

33

SC

KO

018

SC

KO

22

MC

KO

215

MC

KO

114

CS

EL

12

R2

332

2

R2

43

0

TP

67

1

R2

40

4.9

9K

R2

42

1K


A-7

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

I2C

_C

LK

I2C

_D

AT

A

UA

RT

_RX

D0

UA

RT

_TX

D0

3V

3.I

2C

_C

LK

3V

3.I

2C_

DA

TA

1V8

.MS

P43

0_I

NT

VC

C_

1.8

V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_3

.3V

VC

C_

1.8

V

VC

C_

1.8

V

1V

8.I2

C_

CL

K2

2,2

6,2

7

GIO

326

GIO

626

GIO

026

GIO

214

,26

GIO

526

GIO

38

26

GIO

426

GIO

126

GIO

V3

3_0

18,2

7

GIO

V3

3_2

18,2

7

GIO

V3

3_4

18,2

7

GIO

V3

3_6

18,2

7

GIO

V33

_8

18,2

7

GIO

V33

_10

18,2

7

GIO

V33

_12

18,2

7

GIO

V33

_14

18,2

7

GIO

V33

_16

18,2

7

GIO

V3

3_1

18,2

7

GIO

V3

3_3

18,2

7

GIO

V3

3_5

18,2

7

GIO

V3

3_7

18,2

7

GIO

V3

3_9

18,2

7

GIO

V33

_11

18

,27

GIO

V33

_13

18

,27

GIO

V33

_15

18

,27 SP

I_E

N1

27

SP

I_E

N0

27

SP

I_C

LK

27

SP

I_D

I27

SP

I_D

O27

3V

3.I

2C

_C

LK

20

,23,

24

3V

3.I

2C

_DA

TA

20,2

3,2

4

UA

RT

_R

XD

016

UA

RT

_TX

D0

16

1V

8.I

2C

_D

AT

A2

2,2

6,27

1V

8.M

SP

430

_IN

T14

GP

IO4

21

4

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

63

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

DM

35

7 I

/O I

NT

ER

FA

CE

EEPROM ( 32KBytes )

U2

8C

TM

S32

0DM

357

GP

IOV

33_1

/TX

CLK

A13

GP

IOV

33_2

/CO

LA

12

GP

IOV

33_3

/TX

D0

B12

GP

IOV

33_1

3/R

XE

RD

10

GP

IOV

33_4

/TX

D1

D12

GP

IOV

33_5

/TX

D2

A11

GP

IOV

33_6

/TX

D3

C12

GP

IOV

33_7

/RX

D0

E12

GP

IOV

33_1

4/C

RS

C10

GP

IOV

33_8

/RX

D1

C11

GP

IOV

33_9

/RX

D2

B11

GP

IOV

33_1

0/R

XD

3E

11

GP

IOV

33_1

1/R

XC

LKA

10

GP

IOV

33_1

5/M

DIO

E10

GP

IOV

33_1

2/R

XD

VD

11

GP

IOV

33_0

/TX

EN

B13

GP

IO0/

LCD

_OE

C13

GP

IO1/

C_W

En

E13

GP

IO2/

G0

D13

GP

IO3/

B0/

LCD

_FIE

LDC

14

GP

IO4/

R0/

C_F

IELD

B14

GP

IO5/

G1

E14

GP

IO6/

B1

A14

SD

A/G

PIO

44B

4

GP

IO38

/R1

D14

SC

L/G

PIO

43C

4

UA

RT

_TX

D0/

GP

IO36

C5

UA

RT

_RX

D0/

GP

IO35

D5

SP

I_D

O/G

PIO

41A

2

SP

I_E

N0/

GP

IO37

A4

SP

I_E

N1/

GP

IO42

B2

SP

I_C

LK/G

PIO

39A

3

GP

IO7

C3

GP

IOV

33_1

6/M

DC

B10

SP

I_D

I/GP

IO40

B3

R1

9722

R4

24

10K

R2

152.

2K

R2

0122

R2

1310

0

R2

12

2.2

K

C1

950

.1u

F

R4

1010

K

C1

940

.1u

F

U3

4 24W

C2

56

A0

1V

CC

8

VS

S4

NC

3S

CL

6

SD

A5

A1

2W

P7

RN

14

RP

AC

K4

-22

1 2 3 45678

R2

142

.2K

C1

620

.1u

F

VREF

2

GN

D

VR

EF1

ENAB

LE

SC

L1

SD

A1

SC

L2

SDA2

U33

PC

A9

306

7 6

2

8

3 1

54

R2

112

.2K

R1

9822



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_3

.3V

VC

C_

1.8

V

VC

C_

3.3

V

SD

_C

LK

15

,27

SD

_DA

TA

01

5,2

7

SD

_C

MD

15

,27

SD

_D

AT

A1

15,2

7

SD

_D

AT

A3

15,2

7S

D_D

AT

A2

15

,27

CL

KR

27

FS

R27

DR

27D

X27

FS

X27

CL

KX

27

US

B_

ID17

US

B_

VB

US

17

B_C

LK

R22

B_

FS

R22

B_

DR

22B

_DX

22

B_F

SX

22

B_C

LKX

22

McB

SP

_E

N27

US

B_D

M17

US

B_

DP

17

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

73

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

DM

357

US

B &

SD

/MM

C C

ON

TR

OL

LE

R

Place C206 as close to device as possible, between 2 to 5 millimeters

U53 is a switch used for DC3 to allow the McBSP

to be disconnected from on-board circuitry.

Signal levels are at 1.8 Volt logic levels on both

sides of switch

Place R217 as close to device as possible

C21

20

.1u

F

R2

002

2

U2

8H

TM

S32

0DM

357

US

B_V

DD

A3P

3.1

J19

US

B_V

SS

A3P

3.2

J18

US

B_V

DD

1P8

H17

US

B_V

SS

1P8

H16

US

B_D

PG

19

US

B_I

DJ1

6

US

B_V

BU

SJ1

7

US

B_V

DD

A1P

2LD

OG

18

US

B_V

SS

RE

FG

16

US

B_D

MH

19

US

B_R

1H

18

US

B_V

SS

A1P

2LD

OG

17

RN

16

RP

AC

K4-

22

12345 6 7 8

R6

10

.22

+C

601

0u

F

TP

48 1

C2

07

0.0

1u

F

+C

591

0u

FTP

46 1

R1

992

2

L15

BLM

21

PG

22

1SN

1D1

2

R3

0936

0C

274

0.1

uF

R2

17

10K

C2

06

1u

F

C20

90

.1u

F

L13

BL

M2

1PG

221S

N1D

12

C2

11

0.0

1u

F

U2

8F

TMS

320D

M3

57

FS

X/G

PIO

31C

8

FS

R/G

PIO

32C

7

CLK

X/G

PIO

29B

8

CLK

R/G

PIO

30A

8

DX

/GP

IO33

B7

DR

/GP

IO34

A7

SD

_DA

TA

1E

9

SD

_DA

TA

0D

8

SD

_DA

TA

2D

9

SD

_DA

TA

3C

9

SD

_CM

DB

9

SD

_CLK

A9

R6

00

.22

RN

15

RP

AC

K4

-22

1 2 3 45678

TP

47 1

R30

81

0K

R19

522

TP

49 1R

196

22

U5

37

4C

BT

LV3

245

A1

2B

118

A2

3B

217

A3

4B

316

A4

5B

415

A5

6B

514

A6

7B

613

A7

8B

712

A8

9B

811

G19

NC

1V

CC

20

GN

D10


A-9

VC

C_

1.8

V

VC

C_

1.8

VV

CC

_1

.8V

VC

C_

1.8

V

VC

C_

1.8

V

CO

RE

_V

DD

DS

P_

EM

U0

28

DS

P_

EM

U1

28

DS

P_

TR

ST

#28

DS

P_T

DO

28

DS

P_

TD

I28

DS

P_

TM

S28

DS

P_

RT

CK

28

DS

P_T

CK

28

TIM

ER

_IN

14

1.8

V.S

YS

_R

ES

ET

z1

4,2

2,25

,26

,27,

29

CL

KO

UT

025

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5114

52-

0001

Mo

nd

ay,

No

vem

be

r 0

3,

200

88

30

B

TM

S3

20D

M35

7 E

VA

LU

AT

ION

MO

DU

LE

DM

35

7 E

MU

LA

TIO

N &

CLO

CK

S

OPTIONAL OSCILLATOR POPULATION

CRYSTAL AND CAPS REMOVED WHEN

OSCILLATOR IS USED

C1

42

NO

-PO

P

U1

2

NO

-PO

P/2

7 M

Hz

VC

C4

OU

T3

GN

D2

EN

1

Y3 24

MH

z

C1

40

NO

-PO

P

R2

370

C2

291

8p

F

TP

19 1

R1

770

R2

35N

O-P

OP

TP

20 1

R1

78N

O-P

OP

TP8 1

TP

9

1

L14

BLM

21P

G22

1S

N1D

12 C2

27.1

uF

EIA

0402

C1

47

1u

F

TP

10

1

C2

281

8 p

F

R3

4N

O-P

OP

C1

41

.1uF

EIA

04

02C

13

71

000

pF

TP

18 1

R1

76N

O-P

OP

L5

NO

-PO

P1

2

Y2 27

MH

z

C1

38

0.1

uF

L2

BL

M21

PG

221

SN

1D1

2

C1

441

8p

F

C1

48

NO

-PO

P

C1

391

8p

F

R2

38N

O-P

OP

U2

8E

TM

S32

0DM

357

TC

KA

6

TM

SE

6

TR

ST

nD

7

TD

IA

5

TD

OB

5

EM

U1

C6

EM

U0

D6

RE

SE

Tn

L4

M24

XO

F19

M24

VS

SF

17

M24

XI

F18

CLK

_OU

T1/

TIM

_IN

/GP

IO49

E19

CLK

_OU

T0/

GP

IO48

K1

RT

CK

B6

MX

OM

1

MX

I/CLK

INL1

MX

VS

SL2

RS

V24

M3

RS

V6

L3

PLL

VD

D18

M2

L6

BL

M2

1PG

221S

N1D

12

U4

0

NO

-PO

P/2

4 M

Hz

VC

C4

OU

T3

GN

D2

EN

1

R3

50.

22



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CP

U_

CO

RE

_V

DD

MIX

CP

U_

VC

C_

3.3

V

CP

U_

CO

RE

_V

DD

CP

U_

VC

C_

1.8

V

CP

U_

VC

C_1

.8V

CP

U_

VC

C_

1.8

V

CP

U_

VC

C_

1.8

V

CP

U_

VC

C_

1.8

V

CP

U_

CO

RE

_VD

DM

IX

CP

U_

VC

C_

3.3

V

CP

U_C

OR

E_

VD

D

VC

C_

3.3

V

VC

C_

1.8

V

CO

RE

_V

DD

CO

RE

_V

DD

MIX

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

93

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

DM

35

7 P

OW

ER

PIN

S

C1

81

0.1

uF

R2

02

0

+C

272

2u

F

C2

13

0.1

uF

C1

13

0.1

uF

C1

45

0.1

uF

TP

11 1

C1

78

0.1

uF

+C

312

2u

F

+C

13

0N

O-P

OP

C20

0

0.1

uF

C1

46

0.1

uF

+

C1

25N

O-P

OP

C1

76

0.1

uF

C2

04

0.1

uF

U2

8D

TM

S32

0DM

357

DV

DD

18.1

E7

DV

DD

18.2

F6

DV

DD

18.3

F8

DV

DD

18.4

F14

M24

VD

DF

16

DV

DD

18.5

G7

DV

DD

18.6

G9

DV

DD

18.7

G15

DV

DD

18.8

H6

DV

DD

18.9

H14

DV

DD

18.1

0J7

DV

DD

18.1

1J1

5D

VD

D18

.12

K6

DV

DD

18.1

3K

14

MX

VD

DL5

DV

DD

18.1

4L7

DV

DD

18.1

5L1

3D

VD

D18

.16

M6

DV

DD

18.1

7M

14

CV

DD

DS

P.1

H8

CV

DD

DS

P.2

H10

CV

DD

DS

P.3

H11

CV

DD

DS

P.4

H12

CV

DD

DS

P.5

J9C

VD

DD

SP

.6J1

0C

VD

DD

SP

.7J1

1C

VD

DD

SP

.8J1

3C

VD

DD

SP

.9K

8C

VD

DD

SP

.10

K9

CV

DD

DS

P.1

1K

11

CV

DD

.1F

15C

VD

D.2

K10

CV

DD

.3K

12C

VD

D.4

L8C

VD

D.5

L9C

VD

D.6

L10

CV

DD

.7L1

1

RS

V2

A19

RS

V5

D4

VS

S.1

9K

5V

SS

.20

K7

VS

S.2

1K

13V

SS

.22

K15

VS

S.2

3L6

VS

S.2

4L1

2V

SS

.25

L14

VS

S.2

6M

5V

SS

.27

M7

VS

S.2

8M

9V

SS

.29

M11

VS

S.3

0M

13V

SS

.31

N6

VS

S.3

2N

8V

SS

.33

N10

VS

S.3

4N

12V

SS

.35

N14

VS

S.3

6P

7V

SS

.37

P9

VS

S.3

8P

11V

SS

.39

P13

VS

S.4

0P

15V

SS

.41

R6

VS

S.4

2R

7V

SS

.43

R10

VS

S.4

4R

12

VS

S.1

3H

13V

SS

.14

H15

VS

S.1

5J6

VS

S.1

6J8

VS

S.1

7J1

2V

SS

.18

J14

VS

S.1

E8

VS

S.2

F7

VS

S.3

F9

VS

S.7

G11

VS

S.9

G13

VS

S.4

G6

VS

S.8

G12

VS

S.1

0G

14V

SS

.11

H7

VS

S.1

2H

9

DV

DD

R2.

1N

7D

VD

DR

2.2

N9

DV

DD

R2.

3N

11D

VD

DR

2.4

N13

DV

DD

R2.

5P

6D

VD

DR

2.6

P8

DV

DD

R2.

7P

10D

VD

DR

2.8

P12

DV

DD

R2.

9P

14D

VD

DR

2.10

R9

DV

DD

R2.

11R

11D

VD

DR

2.12

R13

DV

DD

R2.

13R

15

CV

DD

.8M

8C

VD

D.9

M10

CV

DD

.10

M12

DV

DD

33.1

F10

DV

DD

33.2

F11

DV

DD

33.3

F12

DV

DD

33.4

F13

VS

S.5

G8

VS

S.6

G10

DV

DD

18.1

8N

5

VS

S.4

5R

14

RS

V4

W19

DV

DD

R2.

14T

5

RS

V1

A1

RS

V3

W1

+C

582

2u

F

C2

08

0.1

uF

C1

79

0.1

uF

C2

10

0.1

uF

C1

11

0.1

uF

C2

15

0.1

uF

C1

69

0.1

uF

C1

87

0.1

uF

TP

30 1

C2

01

0.1

uF

C1

99

0.1

uF

C1

77

0.1

uF

C1

43

0.1

uF

TP

42 1

+C

28

22u

F

C1

67

0.1

uF

C2

14

0.1

uF

C13

6

0.1

uF

C1

83

0.1

uF

TP

31 1

+C

29

22

uF

TP

41 1

C1

35

0.1

uF

C1

84

0.1

uF

C20

5

0.1

uF

C1

82

0.1

uF

+C

47

22u

F

TP

32 1

C2

03

0.1

uF

+C

49

22u

F

+C

48

22

uF

+C

40

22u

F

R42

0.02

5

C1

15

0.1

uF

C1

85

0.1

uF

+

C1

32

NO

-PO

P

C1

75

0.1

uF

C16

8

0.1

uF

C1

74

0.1

uF

C1

34

0.1

uF

C1

88

0.1

uF

C1

80

0.1

uF

C1

86

0.1

uF

+C

30

22

uF

R36

0.0

25

TP

21

1R54

0.0

25

R3

70

.02

5TP

22 1

C20

2

0.1

uF

+C

12

7N

O-P

OP


A-11

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_

1.8

V

YO

UT

05

,26

YO

UT

15

,26

YO

UT

25

,26

YO

UT

35

,26

YO

UT

45

,26

EM

_C

S2

3,1

4N

AN

D_

CE

z12

DC

_EM

_CS

225

CO

UT

35

,26

CO

UT

25

,26

CO

UT

15

,26

CO

UT

05

,26

US

ER

_S

W24

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

103

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

DM

357

CO

NF

IGU

RA

TIO

N C

ON

TR

OL

/BO

OT

OP

TIO

NS

BOOT CONFIGURATION SWITCH

ONLY ONE DEVICE CAN BE SELECTED

AT A TIME AT POWER UP.

TO RECONFIGURE BOARD

POWER DOWN EVM,

CHANGE JUMPER TO DESIRED DEVICE.

11 = Boot from ROM (UART)

PINS

FUNCTION

SWITCH S1

Selects ARM Boot Mode

BTSEL[1:0]

00 = Boot from ROM (NAND)

01 = Boot from AEM IF

10 = Boot from ROM (HPI)

Non-secure device

COUT[1:0]

MODE

Selects AEM IF CS2 Bus Width

8_16

COUT2

0 = 8-bit

1 = 16-bit

S1-2=OFF S1-1=OFF

S1-3=OFF

S1-3=ON

S1-2=OFF S1-1=ON

S1-2=ON S1-1=OFF

S1-2=ON S1-1=ON

COUT3

RESERVED

S1-4=OFF

YOUT[4:0]

AEAW [4:0]

Address Bus Width

S1-5=ON

S1-6=ON

S1-7=ON

S1-8=ON

ALL

ADDRESS LINES GPIO

S1-9=ON

SPARE SWITCH

PULL LOW

*

*

*

USER

* * * * *

*DEFAULT

DEMO

0 = NTSC

1 = PAL

S1-10=OFF

S1-10=ON

*

R2

29

1K

R22

710

K

J4

HE

AD

ER

2X

23 41 2

1 2 3 4 5 6 7 8 9 10S3

DIP

_S

WIT

CH

-10

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

RN

29

RP

AC

K8-

1K

1 2 3 4 5 6 7 8910111213141516

R2

28N

O-P

OP

RN

28

RP

AC

K8

-NO

-PO

P

123456789

10111213141516

R2

30

1K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DD

R_

A1

0

DD

R_

A8

DD

R_

A7

DD

R_

A1

DD

R_

A9

DD

R_

A5

DD

R_

A0

DD

R_

A6

DD

R_

A2

DD

R_

A1

1D

DR

_A

12

DD

R_

A3

DD

R_

A4

DD

R_

A4

DD

R_

A3

DD

R_

A1

2D

DR

_A

11

DD

R_

A2

DD

R_

A6

DD

R_

A0

DD

R_

A5

DD

R_

A9

DD

R_

A1

DD

R_

A7

DD

R_

A8

DD

R_

A1

0

DD

R_B

S0

0D

DR

_BS

01

DD

R_B

S0

2D

DR

_B

S02

DD

R_

BS

01D

DR

_B

S00

DD

R_

CL

K_

ND

DR

_C

LK

DD

R_

CS

DD

R_

CL

KD

DR

_C

LK_

N

DD

R_C

AS

DD

R_C

KE

DD

R_R

AS

DD

R_

WE

DD

R_

DQ

S0

DD

R_

DQ

M0

DD

R_

DQ

S1

DD

R_

DQ

S2

DD

R_

DQ

M1

DD

R_

DQ

M2

DD

R_

DQ

M3

DD

R_

CS

DD

R_

RA

S

DD

R_

CK

E

DD

R_

CA

S

DD

R_

WE

DD

R_

DQ

S3

VR

EF

_ST

L

VR

EF

_S

TL

DD

R_

D1

2D

DR

_D

14

BD

DR

_D

15

BD

DR

_D

14

BD

DR

_D

13

BD

DR

_D

12

BD

DR

_D

11

BD

DR

_D

10

BD

DR

_D

9B

DD

R_

D8

BD

DR

_D

7B

DD

R_

D6

BD

DR

_D

5B

DD

R_

D4

BD

DR

_D

3B

DD

R_

D2

BD

DR

_D

1

BD

DR

_D

14

BD

DR

_D

12

DD

R_

D2

8

DD

R_

D2

9

DD

R_

D3

0

BD

DR

_D

31

BD

DR

_D

30

BD

DR

_D

29

BD

DR

_D

27

BD

DR

_D

28

BD

DR

_D

26

BD

DR

_D

25

BD

DR

_D

24

BD

DR

_D

23

BD

DR

_D

22

BD

DR

_D

21

BD

DR

_D

20

BD

DR

_D

19

BD

DR

_D

18

BD

DR

_D

17

BD

DR

_D

16

BD

DR

_D

29

BD

DR

_D

30

BD

DR

_D

28

DD

R_

D2

DD

R_

D0

BD

DR

_D

2

BD

DR

_D

0

BD

DR

_D

0

DD

R_

D9

DD

R_

D1

1B

DD

R_

D1

1B

DD

R_

D9

DD

R_

D3

1D

DR

_D

24

BD

DR

_D

31

BD

DR

_D

24

BD

DR

_D

13

DD

R_

D1

5D

DR

_D

13

BD

DR

_D

15

DD

R_

D1

0D

DR

_D

8B

DD

R_

D1

0B

DD

R_

D8

DD

R_

D6

DD

R_

D4

BD

DR

_D

6B

DD

R_

D4

DD

R_

D1

DD

R_

D3

BD

DR

_D

1B

DD

R_

D3

BD

DR

_D

17

BD

DR

_D

19

BD

DR

_D

20

BD

DR

_D

22

BD

DR

_D

27

BD

DR

_D

25

DD

R_

D2

7D

DR

_D

25

BD

DR

_D

16

BD

DR

_D

18

DD

R_

D1

6D

DR

_D

18

BD

DR

_D

23

BD

DR

_D

21

DD

R_

D2

3

DD

R_

D2

1

BD

DR

_D

5B

DD

R_

D7

DD

R_

D7

DD

R_

D5

BD

DR

_D

26

DD

R_

D2

6

DD

R_

D1

7D

DR

_D

19

DD

R_

D2

2D

DR

_D

20

BD

DR

_D

[0:1

5]

BD

DR

_D

[16

:31

]

VC

C_

1.8

V

VC

C_

1.8

VV

CC

_1

.8V

DD

R_D

[0:3

1]

4

DD

R_

A[0

:12

]4

DD

R_

BS

02

4D

DR

_B

S0

14

DD

R_

BS

00

4

DD

R_W

E4

DD

R_

CK

E4

DD

R_

CL

K4

DD

R_

RA

S4

DD

R_

CL

K_

N4

DD

R_

CA

S4

DD

R_

CS

4

DD

R_

DQ

M2

4D

DR

_D

QM

34

DD

R_

DQ

S2

4

DD

R_

DQ

S1

4

DD

R_

DQ

S0

4 DD

R_

DQ

M1

4D

DR

_D

QM

04

VR

EF

_ST

L4

DD

R_

DQ

S3

4

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

113

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

DD

R2

ME

MO

RY

128 MEGABYTES

128 MEGABYTES

+C

18

22

uF

U3

2

MT

47H

64M

16B

T

A12

V2

A11

U7

A10

R2

A9

U3

A8

U8

A7

U2

A6

T7

A5

T3

A4

T8

A3

T2

A2

R7

A1

R3

A0

R8

BA

2P

1

BA

1P

3

BA

0P

2

NC

.1A

A9

NC

.2A

A8

NC

.3A

A2

NC

.4A

A1

NC

.5D

2

NC

.6V

8

NC

.7A

9

NC

.8A

8

NC

.9A

2

NC

.10

A1

NC

.11

H2

RF

U.1

V3

RF

U.2

V7

OD

TN

9

CS

#P

8

CA

S#

P7

RA

S#

N7

WE

#N

3

CK

EN

2

CK

M8

CK

#N

8

UD

QS

#/N

UD

8

UD

QS

E7

LDQ

S#/

NU

H8

LDQ

SJ7

UD

ME

3

LDM

J3

VD

D.1

M9

VD

D.2

H1

VD

D.3

R9

VD

D.4

D1

VD

D.5

V1

VD

DQ

.1F

3

VD

DQ

.2F

7

VD

DQ

.3K

1

VD

DQ

.4K

3

VD

DQ

.5K

7

VD

DQ

.6K

9

VD

DQ

.7D

9

VD

DQ

.8F

1

VD

DQ

.9F

9

VD

DQ

.10

H9

VD

DL

M1

VR

EF

M2

DQ

15E

9

DQ

14E

1

DQ

13G

9

DQ

12G

1

DQ

11G

3

DQ

10G

7

DQ

9F

2

DQ

8F

8

DQ

7J9

DQ

6J1

DQ

5L9

DQ

4L1

DQ

3L3

DQ

2L7

DQ

1K

2

DQ

0K

8

VS

S.1

U9

VS

S.2

T1

VS

S.3

H3

VS

S.4

D3

VS

S.5

M3

VS

SQ

.1G

8

VS

SQ

.2J8

VS

SQ

.3D

7

VS

SQ

.4J2

VS

SQ

.5E

2

VS

SQ

.6L8

VS

SQ

.7L2

VS

SQ

.8E

8

VS

SQ

.9H

7

VS

SQ

.10

G2

VS

SD

LM

7

RN

27

RP

AC

K4-

47

1 2 3 45678

RN

6R

PA

CK

4-4

71 2 3 4

5678

U2

0

MT

47H

64M

16B

T

A12

V2

A11

U7

A10

R2

A9

U3

A8

U8

A7

U2

A6

T7

A5

T3

A4

T8

A3

T2

A2

R7

A1

R3

A0

R8

BA

2P

1

BA

1P

3

BA

0P

2

NC

.1A

A9

NC

.2A

A8

NC

.3A

A2

NC

.4A

A1

NC

.5D

2

NC

.6V

8

NC

.7A

9

NC

.8A

8

NC

.9A

2

NC

.10

A1

NC

.11

H2

RF

U.1

V3

RF

U.2

V7

OD

TN

9

CS

#P

8

CA

S#

P7

RA

S#

N7

WE

#N

3

CK

EN

2

CK

M8

CK

#N

8

UD

QS

#/N

UD

8

UD

QS

E7

LDQ

S#/

NU

H8

LDQ

SJ7

UD

ME

3

LDM

J3

VD

D.1

M9

VD

D.2

H1

VD

D.3

R9

VD

D.4

D1

VD

D.5

V1

VD

DQ

.1F

3

VD

DQ

.2F

7

VD

DQ

.3K

1

VD

DQ

.4K

3

VD

DQ

.5K

7

VD

DQ

.6K

9

VD

DQ

.7D

9

VD

DQ

.8F

1

VD

DQ

.9F

9

VD

DQ

.10

H9

VD

DL

M1

VR

EF

M2

DQ

15E

9

DQ

14E

1

DQ

13G

9

DQ

12G

1

DQ

11G

3

DQ

10G

7

DQ

9F

2

DQ

8F

8

DQ

7J9

DQ

6J1

DQ

5L9

DQ

4L1

DQ

3L3

DQ

2L7

DQ

1K

2

DQ

0K

8

VS

S.1

U9

VS

S.2

T1

VS

S.3

H3

VS

S.4

D3

VS

S.5

M3

VS

SQ

.1G

8

VS

SQ

.2J8

VS

SQ

.3D

7

VS

SQ

.4J2

VS

SQ

.5E

2

VS

SQ

.6L8

VS

SQ

.7L2

VS

SQ

.8E

8

VS

SQ

.9H

7

VS

SQ

.10

G2

VS

SD

LM

7

+C

57

22

uF

C1

55

0.1

uF

C2

200

.1u

F

C1

57

0.1

uF

+C

102

NO

-PO

P

C1

52

0.1

uF

RN

31

RP

AC

K4

-47

1 2 3 45678

RN

5R

PA

CK

4-4

7

1 2 3 45678

RN

30

RP

AC

K4

-47

1 2 3 45678

C1

54

0.1

uF

R1

510

R2

071

K 1

%

C2

19

0.1

uF

RN

20

RP

AC

K4

-47

1 2 3 45678

C1

49

0.1

uF

C2

180

.1u

F

RN

19

RP

AC

K4

-47

1 2 3 45678

C1

50

0.1

uF

C2

17

0.1

uF

RN

26

RP

AC

K4-

47

1 2 3 45678

C1

51

0.1

uF

R15

20

C1

53

0.1

uF

R2

081

K 1

%

C22

30

.1u

F

C22

20

.1u

F

C1

56

0.1

uF

C2

21

0.1

uF

C2

25

0.1

uF

C2

24

0.1

uF


A-13

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

WR

ITE

_W

E

RE

AD

_O

E

EM

_D

0

EM

_D

2E

M_

D3

EM

_D

4E

M_

D5

EM

_D

1

EM

_D

6E

M_

D7

CLE

_E

M_A

2

ALE

_E

M_A

1

VC

C_

1.8

V

VC

C_

1.8

V

VC

C_

1.8

V

VC

C_

1.8

V

ALE

_EM

_A1

3,1

4,2

5

WR

ITE

_W

E3

,14

,25

CL

E_E

M_A

23,

14

,25

RE

AD

_O

E3

,14

,25 N

AN

D_

CE

z10

NA

ND

_BU

SY

14

EM

_D

13

,14

,25

EM

_D

33

,14

,25

EM

_D

53

,14

,25

EM

_D

73

,14

,25

EM

_D

03

,14

,25

EM

_D

23

,14

,25

EM

_D

43

,14

,25

EM

_D

63

,14

,25

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

123

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

SR

AM

/NA

ND

FLA

SH

NAND FLASH ( 64MBytes )

K9K1G08 supports 128 MEGABYTES

R1

41

10K

R1

4010

K

R1

35

10K

C9

2.1

uF

SA

MS

UN

G K

9K

12

08/Q

/D/U

/0C

U6

NC.1 B1

NC.2 B4

NC.3 B5

NC.4 B6

NC.5 C1

NC.6 C2

R/B

A6

RE

B2

CE

A4

NC.7 C3

NC.8 C4

VC

C.1

F6

VS

S.1

A3

NC.20 E4

NC.21 E5

CLE

B3

ALE

A2

WE

A5

WP

A1

NC.19 E3NC.18 E2NC.17 E1NC.16 D6NC.15 D5

VS

S.2

H1

I/O00

F2

NC.9 C5

I/O01

G2

NC.10 C6

I/O02

H2

NC.11 D1

I/O03

H3

NC.12 D2

NC.14 D4

NC.22 F1

NC.13 D3

VC

C.2

G4

LOC

KP

RE

E6

NC.23 F3

I/O04

H4

NC.25 F5

I/O05

G5

NC.24 F4

I/O06

H5

I/O07

G6

VS

S.3

H6

NC.26 G1

NC.27 G3

R1

39N

O-P

OP

R1

13N

O-P

OP

C9

3.1

uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

3V

3_

NA

ND

_BU

SY

3V

3_N

AN

D_

CE

0z

3V

3_N

AN

D_

CE

1z

3V

3_R

EA

D_

OE

3V3

_EM

_D0

3V3

_EM

_D1

3V3

_EM

_D2

3V3

_EM

_D3

3V3

_EM

_D4

3V3

_EM

_D5

3V3

_EM

_D6

3V3

_EM

_D7

3V

3_A

LE

_EM

_A1

3V

3_C

LE_E

M_A

2

3V

3_W

RIT

E_W

E

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_3.3

V

3V

3_E

M_D

114

3V

3_E

M_D

314

3V

3_E

M_D

514

3V

3_E

M_D

714

3V

3_E

M_D

014

3V

3_E

M_D

214

3V

3_E

M_D

414

3V

3_E

M_D

614

3V3_

EM

_A1

14

3V3_

EM

_WE

14

3V3_

EM

_A2

14

3V

3_

RE

AD

_O

E1

4

3V

3_N

AN

D_

BU

SY

14

3V

3_

NA

ND

_C

E0

z1

43

V3

_N

AN

D_

CE

1z

14

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

133

0

B

TM

S3

20D

M35

7 E

VA

LU

AT

ION

MO

DU

LE

EM

IF L

EV

EL

SH

IFT

ER

C3

76

10

uF

U67

MT2

9F16

G08

FAA

WC

:A

I/O7

44

I/O6

43

I/O5

42

I/O4

41

VC

C.1

12

I/O3

32

I/O2

31

I/O1

30

I/O0

29

VS

S.2

36

RE

8

CE

9

VC

C.2

37D

NU

/VS

S38

CLE

16

ALE

17

WE

18

WP

19

NC

.11

NC

.22

NC

.33

NC

.44

NC

.55

NC

.11

11

VS

S.1

13

R/B

2n6

R/B

n7

CE

210

NC

.14

14

NC

.15

15

NC

.20

20

NC

.21

21

NC

.22

22

NC

.23

23

NC

.24

24D

NU

.25

25D

NU

.26

26N

C.2

727

NC

.28

28

NC

.33

33N

C.3

434

NC

.35

35

NC

.39

39N

C.4

040

NC

.45

45N

C.4

646

NC

.47

47D

NU

.48

48

MH1 MH1

MH2 MH2

C3

77

0.1

uF

R4

340

R4

330

R4

3710

K

C3

75

0.1

uF

R4

360

R4

31

10K

R4

350

R4

32

10K


A-15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

ISR

_T

CK

ISR

_T

MS

ISR

_T

DO

ISR

_T

CK

ISR

_T

DO

ISR

_TM

S

ISR

_T

DI

ISR

_T

CK

ISR

_T

DO

ISR

_T

DI

ISR

_TM

S

3V

3_E

M_D

1

3V

3_E

M_D

3

3V

3_E

M_D

5

3V

3_E

M_D

7

3V

3_E

M_D

0

3V

3_E

M_D

2

3V

3_E

M_D

4

3V

3_E

M_D

6

3V

3_

NA

ND

_B

US

Y

3V

3_R

EA

D_

OE

3V

3_

NA

ND

_C

E1z

3V

3_

NA

ND

_C

E0z

3V

3_A

LE_E

M_

A1

3V

3_C

LE

_EM

_A

2

3V

3_W

RIT

E_

WE

VC

C_

3.3

VV

CC

_1.8

V

VC

C_3

.3V

VC

C_

1.8

V

VC

C_

1.8

VV

CC

_1

.8V

VC

C_3

.3V

VC

C_

3.3

VV

CC

_1

.8V

VC

C_

1.8

VV

CC

_1

.8V

VC

C_

3.3

V

1.8

V.S

YS

_R

ES

ET

z8

,22

,25

,26

,27

,29

1V

8.M

SP

430

_IN

T6

EM

_BA

13

,25A

LE

_E

M_A

13

,12,

25

EM

_A0

3,2

5CL

E_

EM

_A

23

,12

,25

3V

3.S

YS

_RE

SE

Tz

18

,20,

24

,27

3V

3.U

AR

T_

RX

D1

24

,27

3V

3.U

AR

T_T

XD

124

,27

SP

AR

EIO

324

SP

AR

EIO

224

SP

AR

EIO

124

TIM

ER

_IN

8T

IME

R_

IN_

DC

32

7

CP

LD

_T

IME

R_

IN5

GIO

26

,26

EM

_BA

03

,25

WA

IT/B

US

Y3

,25

EM

_C

S2

3,1

0

NA

ND

_BU

SY

12

GP

IO51

3,2

5G

PIO

523

,25

GP

IO4

26 U

AR

T_R

XD

13

UA

RT

_TX

D1

3

EM

_D

13

,12

,25

EM

_D

33

,12

,25

EM

_D

53

,12

,25

EM

_D

73

,12

,25

EM

_D

03

,12

,25

EM

_D

23

,12

,25

EM

_D

43

,12

,25

EM

_D

63

,12

,25

3V3

_EM

_D1

13

3V3

_EM

_D3

13

3V3

_EM

_D5

13

3V3

_EM

_D7

13

3V3

_EM

_D0

13

3V3

_EM

_D2

13

3V3

_EM

_D4

13

3V3

_EM

_D6

13

3V

3_

NA

ND

_B

US

Y13

3V

3_R

EA

D_

OE

133

V3

_N

AN

D_C

E0z

133

V3

_N

AN

D_C

E1z

13

3V3_

EM

_A2

133V

3_E

M_A

113

3V3_

EM

_WE

13

EM

_C

S4

3E

M_

CS

53

EM

_C

S3

3,2

5

EM

_R

NW

3,2

5

EM

_A4

3,2

5E

M_A

33

,25

US

B.D

RV

VB

US

z17

US

B.O

VE

R_

CU

RR

EN

T1

7

WR

ITE

_WE

3,1

2,2

5R

EA

D_

OE

3,1

2,2

5

1V

8.D

C_

PC

LK

26

MS

P4

30_

INT

24

3V

3.D

C_

PC

LK

5

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

143

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

CP

LD

DE

CO

DE

R/

LE

VE

L S

HIF

TE

R

CPLD

REVISION XXXXXX-0001A

R3

69

33

C1

29

0.1

uF

C1

08

0.1

uF

R4

38

10K

R1

65

0

R4

40

1K

R1

90

10K

JP1

HE

AD

ER

6X

2 2M

M

2 4 6 8 10 12

1 3 5 7 9 11

L63

BLM

41P

750S

PT

R19

110

K

R3

68

NO

-PO

P

C1

04

0.1

uF

C1

31

0.1

uF

DS

10

LE

D

R4

41

1K

C1

280

.1u

F

U1

4

EP

M2

40G

TC

100

B1.

PIN

22

B1.

PIN

33

TD

I.B1

23

B1.

PIN

44

B1.

PIN

66

B1.

PIN

77

B1.

PIN

88

B1.VCCIO1A9

GNDIO1 10

GNDINTA 11

B1.

GC

LK0

12

VCCINT113

B1.

GC

LK1

14

TM

S.B

122

B1.

PIN

1616

B1.

PIN

1717

B1.

PIN

1818

B1.

PIN

1919

B1.

PIN

2020

B1.

PIN

2121

B1.

PIN

2727

B1.

PIN

2626

B1.

PIN

2828

B1.

PIN

2929

B1.

PIN

3030

B1.VCCIO1B31

B1.

PIN

3333

B1.

PIN

3434

B1.

PIN

3535

B1.

PIN

3636

B1.

PIN

3737

B1.

PIN

3838

B1.

PIN

3939

B1.

PIN

4040

B1.

PIN

4141

B1.

PIN

4242

B1.

DE

V_O

E43

B1.

DE

V_C

LRn

44

B1.VCCIO1C45

GNDIO3 46

B1.

PIN

4747

B1.

PIN

4848

B1.

PIN

4949

B1.

PIN

5050

B1.

PIN

5151

B2.

PIN

5252

GNDIO2 32

B2.

PIN

5454

B2.

PIN

5555

B2.

PIN

5757

B2.

PIN

5858

B2.VCCIO1A59

GNDIO4 60

B2.

PIN

6161

TC

K.B

124

VCCINT263

B2.

PIN

6666

GNDINTB 65

B2.

PIN

6767

B2.

PIN

6868

B2.

PIN

6969

B2.

PIN

7070

B2.

PIN

7171

B2.

PIN

7272

TD

O.B

125

B2.

PIN

7373

B2.

PIN

7676

B2.

PIN

7777

GNDIO5 79

B2.VCCIO1B80

B2.

PIN

8181

B2.

PIN

8383

B2.

PIN

8484

B2.

PIN

8585

B2.

GC

LK3

64B

2.G

CLK

262

B2.

PIN

8686

GNDIO6 93

B2.VCCIO1C94

B2.

PIN

9696

B2.

PIN

9797

B2.

PIN

9898

B2.

PIN

9999

B2.

PIN

100

100

B1.

PIN

55

B1.

PIN

1515

B2.

PIN

5353

B2.

PIN

5656

B2.

PIN

7474

B2.

PIN

7575

B2.

PIN

7878

B2.

PIN

8282

B2.

PIN

8787

B2.

PIN

8888

B2.

PIN

8989

B2.

PIN

9090

B2.

PIN

9191

B2.

PIN

9292

B2.

PIN

9595

B2.

PIN

11

C1

260

.1u

F

R4

4710

K

R1

93 10K

R4

391

0K

1 2S5 D

IP_

SW

ITC

H_2

1 234

C1

070

.1u

F

TP

231

L62

NO

-PO

P

R2

23

2.2

K

J17

SM

T F

EM

AL

E H

EA

DE

R 5

X2

12

34

56

78

910

R1

92

0

R4

4633

RN

24

RP

AC

K4

-10K

1 2 3 45678

R7

633

0

TP

241

C1

090

.1u

F

RN

36

RP

AC

K4-

10K

12345

678



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SD

_DA

TA

0S

D_D

AT

A1

SD

_C

MD

SD

_DA

TA

2

SD

_C

LK

SD

_DA

TA

3

VC

C_3

.3V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

SD

_DA

TA

17

,27

SD

_DA

TA

37

,27

SD

_DA

TA

27

,27

SD

_C

LK7

,27

SD

_C

MD

7,2

7

SD

_DA

TA

07

,27

SD

/MM

C.I

NS

24

SD

/MM

C.W

P24

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mon

da

y, N

ove

mbe

r 0

3,

20

08

153

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

SD

/MM

C C

ON

NE

CT

OR

J3

MM

C/S

D_

CA

RD

DA

T3

1

CM

D2

VS

S1

3

VD

D4

CLK

5

VS

S2

6

DA

T0

7

DA

T1

8

DA

T2

9W

PW

P

CO

MC

O

CA

RD

DE

TE

CT

CD

MH1 13

MH2 14

MH3 15

MH4 16

MH5 17

MH6 18

R1

08

51K

R1

2251

K

R1

25

NO

-PO

P

R9

90

R1

24

51K

R1

18

NO

-PO

P

C7

8.1

uF

+C

101

0u

F

R1

23

51K

R1

26

51K

R11

9N

O-P

OP

R12

051

KR

11

75

1KR

73

51K


A-17

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

S_A

_TX

D

S_A

_RX

DS

_A_R

XD

3V3

.UA

RT

_R

XD

0

UA

RT

_TX

D0

3V3.

UA

RT

_TX

D0

UA

RT

_RX

D0

VC

C_3

.3V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3V

VC

C_

1.8

V

VC

C_3

.3V

VC

C_

1.8

V

UA

RT

_TX

D0

6

UA

RT

_R

XD

06

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

163

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

RS

23

2 I

NT

ER

FA

CE

L B-->A

H A-->B

DIR FUNCTION

C2

97

10p

F

C3

01.1

uF

L55

BL

M2

1PG

221S

N1D

12

C2

43

.1u

F

R3

5510

K

U42

SN

74A

VC

1T4

5

A1

3

VC

CB

6V

CC

A1

GN

D1

2

B1

4

DIR

5

C3

00

10

pF

R3

560

R3

57

10

C2

45

.1u

F

U6

4M

AX

3221

DIN

11

INV

ALI

D10

RO

UT

9

C1+

2

C1-

4

V+

3

VCC 15

GND 14

V-

7

C2-

6

C2+

5

RIN

8

EN

AB

LE1

FO

RC

EO

FF

16

DO

UT

13

FO

RC

EO

N12

+C

302

1u

F

C2

44

.1u

F

C2

95

10

pF

+C

299

1u

F

+

C29

61

uF

U43

SN

74A

VC

1T4

5

A1

3

VC

CB

6V

CC

A1

GN

D1

2

B1

4

DIR

5

C2

94

10

pF

+C

77

47

uF

L47

1u

H

L54

BL

M2

1PG

221S

N1D

12

+C

298

1u

F

C24

6.1

uF

R3

5410

K

P6

DS

UB

9-M

ale594837261

1011

L46

1u

H



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

US

B_

DP

US

B_

DM

US

B_

SH

IEL

D

VC

C_3

.3V

VC

C_

5V

VC

C_3

.3V

US

B_D

M7

US

B_

DP

7

US

B_

VB

US

7

US

B.D

RV

VB

US

z14

US

B.O

VE

R_

CU

RR

EN

T14

US

B_

ID7

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

173

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

US

B 2

.0 I

NT

ER

FA

CE

Selects Termination

forHost/Client

configurations

For host mode Capacitor Minimum Capacitance

is 100uF, this design uses 106.8uF

both

C133 and C69 installed.

For Peripheral or OTG the

Capacitancer should be 6.8 uF

so remove disconnect C133 by

putting J9 in the 2-3 position

C69 provides capacitance

J7H

EA

DE

R 3

1 2 3

TP

71 1

J9H

EA

DE

R 3

123

C2

93

10

0nF

J10

min

iAB

VB

US

1

D-

2

D+

3

GN

D5

ID4

S1 6

S2 7

S3 8

S4 9

R3

77

100K

U6

8

TP

S2

065D

OU

T1

8IN

12

GN

D1

EN 4

OCn 5

IN2

3O

UT

27

OU

T3

6

TP

72 1

L53

BLM

21P

G2

21S

N1D

12

L52

BLM

21P

G2

21S

N1D

12

+

C1

331

00u

F

TP

591

TP

601

R3

371

.5K

R4

290

+

C6

96

.8uF

R4

3010

K+C

16

31

00u

F


A-19

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LXT

_RD

M

LXT_TDCT

LXT

_TD

P

MII

_R

XD

V

MII

_C

RS

XS

PD

O_

MD

IO

MII

_RX

D3

MII

_R

CL

K

MII_

TX

CLK

RB

IAS

MII

_RD

X2

MT

XD

3LX

T_R

DP

_c

MII

_RX

D1

MT

XE

N

MT

XD

2M

TX

D1

LXT

_RD

M_c

MII

_RX

D0

MD

INT

_T

P

MT

XD

0

PW

RD

WN

SL

EE

P

MII

_C

OL

SY

S_

RS

Tz

MII

_R

XE

R

XS

PC

LK

_M

DC

LK

PA

US

ET

XS

LEW

1T

XS

LEW

0

LXT

_RD

P

MT

XD

3M

TX

EN

MT

XD

0

EN

ET

_E

NA

BLE

z

EN

ET

_E

NA

BLE

z

LIN

KL

ED

-

LED

1-

MT

XD

1M

TX

D2

LXT

_TD

M

PW

RD

WN

TX

SLE

W0

SL

EE

PP

AU

SE

TX

SLE

W1

LED

1-

LIN

KL

ED

-

AV

CC

3.3

AV

CC

3.3

AV

CC

3.3

VC

C_

3.3V

VC

C_3

.3V

VC

C_3

.3V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

EN

ET

_EN

AB

LEz

27

GIO

V33

_06

,27

GIO

V33

_26,

27

GIO

V33

_46

,27

GIO

V33

_66

,27

GIO

V33

_86,

27

GIO

V33

_10

6,27

GIO

V33

_12

6,27

GIO

V33

_14

6,27

GIO

V33

_16

6,2

7

GIO

V33

_16,

27

GIO

V33

_36

,27

GIO

V33

_56

,27

GIO

V33

_76,

27

GIO

V33

_96,

27

GIO

V33

_11

6,27

GIO

V33

_13

6,27

GIO

V33

_15

6,2

7

3V3

.SY

S_R

ES

ET

z1

4,2

0,2

4,27

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

183

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

ET

HE

RN

ET

IN

TE

RF

AC

E

DUPLEX

STATUS

Pla

ce te

rmin

atio

ns

clos

e to

PH

Y s

our

cepi

ns.

COLLISION/

LINK/

SPEED

ACTIVITY

Ro

ute

pair

s to

geth

er,

pair

s ar

e (3

an

d 6

) an

d(1

an

d 2)

.

U5

8

LXT

971A

LE

TX

_CLK

55

TX

D0

57

TX

D1

58

TX

D2

59

TX

D3

60

TX

_EN

56

TX

_ER

54

CO

L62

CR

S63

RX

_CLK

52

RX

D0

48

RX

D1

47

RX

D2

46

RX

D3

45

RX

_DV

49

RX

_ER

53

MD

DIS

3

MD

C43

MD

IO42

MD

INT

#64

TD

I27

TD

O28

TP

FO

P19

TP

FO

N20

TP

FIP

23

TP

FIN

24

LED

/CF

G1

38

LED

/CF

G2

37

LED

/CF

G3

36

AD

DR

012

AD

DR

113

AD

DR

214

AD

DR

315

AD

DR

416

XO

2R

EF

CLK

/XI

1

PW

RD

WN

39

RB

IAS

17

TE

ST

135

RE

SE

T#

4

TE

ST

034

VC

CA

22

GN

D25

SD

/TP

#26

GND1 7

GND2 11

GND3 18

GND4 41

GND5 50

GND6 61

VCCD51

VCCIO18

VCCIO240

VCCA21

TM

S29

TC

K30

TR

ST

#31

TxS

LEW

05

TxS

LEW

16

PA

US

E33

SLE

EP

32

N/C

19

N/C

210

N/C

344

C2

60 2

70p

F

R2

821

0k

U4

1C

BT

LV

162

10D

GG

R

2OE

47

1OE

48

1A1

2

2A1

13

1B1

46

2B1

35

GND 8GND 17GND 32GND 41

VCC15

1A2

3

1A3

4

1A4

5

1A5

6

1A6

7

1A7

9

1A8

10

1A9

11

1A10

12

2A2

14

2A3

16

2A4

18

2A5

19

2A6

20

2A7

21

2A8

22

2A9

23

2A10

24

NC

1

1B2

45

1B3

44

1B4

43

1B5

42

1B6

40

1B7

39

1B8

38

1B9

37

1B10

36

2B2

34

2B3

33

2B4

31

2B5

30

2B6

29

2B7

28

2B8

27

2B9

26

2B10

25

R2

851

0k

RN

34

RP

AC

K8

-33

1 2 3 4 5 6 7 8910111213141516

R2

791

0k

C2

63

0.0

1u

F

R2

88

49

.9

L56

BLM

21P

G2

21S

N1D

12

C3

04

27

0pF

C2

57

0.0

1uF

Y6

25M

Hz

R2

61

22

C2

62

.1u

F

R2

81N

O P

OP

TP

58M

DIN

T

R3

584

9.9

R2

842

2.1

k

L57

BLM

21P

G2

21S

N1D

12

R2

80

1.5

k

C2

59

.1u

F

R2

871

0k

R2

62

22

R2

831

0k

R27

710

0 C2

641

0p

F

R2

89

0

P2

RJ4

5 H

ALO

HF

J11

-245

0E

-L2

1

TX

D-C

T4

NC

17

GN

D8

TX

D+

1

TX

D-

2

RX

D+

3

RX

D-

6R

XD

-CT

5

S0 14S1 13

LED

1+9

LED

1-10

LED

2-12

LED

2+11

R2

59

360

C2

58

.1uF

R2

57

0E

IA0

402

C30

3

.1u

F

L32

BLM

41P

750S

PT

R2

58

NO

-PO

PC

248

10

pF

R2

76

100

C2

47.1

uF

R2

781

0k

R2

86N

O P

OP

R4

07

10K

R2

60N

O P

OP

C2

26

.1u

F

R2

74

0E

IA0

402

R2

75

100

C2

61

.1u

F

L31

EX

C-3

BB

102

H

1 2

R2

2236

0



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TV

P51

46V

IDE

O4

TV

P51

46V

IDE

O3

TV

P51

46V

IDE

O2

TV

P51

46V

IDE

O1

TV

P51

46V

IDE

O0

TV

P51

46V

IDE

O6

TV

P51

46V

IDE

O7

TV

P51

46V

IDE

O5

YI0

YI1

YI2

YI3

YI4

YI5

YI6

YI7

B.Y

I0B

.YI1

B.Y

I2B

.YI3

B.Y

I4B

.YI5

B.Y

I6B

.YI7

VC

C_

3.3

VV

CC

_1.

8V

VC

C_

1.8

V

TV

P5

14

6VID

EO

[0:7

]20

TV

P51

46

HS

YN

C2

0T

VP

51

46

VS

YN

C2

0T

VP

5146

PC

LK20

YI3

5,2

6Y

I45

,26

YI5

5,2

6

YI7

5,2

6

YI0

5,2

6Y

I15

,26

HD

5,2

6V

D5

,26

CA

PT

UR

E_

EN

26

YI2

5,2

6

1.8

V_

DC

3_P

CL

K27

YI6

5,2

6

PC

LK

5,2

6

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

193

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

TV

P51

46

LE

VE

L S

HIF

TE

R

DIR BUS

L B->A

H B<-A

U66 is a tri-stateable logic translator used for DC4

to allow the TVP5146 to be disconnected

from on-board circuitry.Signal levels are at 1.8V logic

levels on B side and 3.3V on A sides of translator.

U6

6

SN

74

AV

CB

164

245

VR

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1A1

47

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A1

36

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

1DIR

1

1OE

n48

2DIR

24

2OE

n25

VC

CB

7

VC

CB

18V

CC

A42

VC

CA

31

GN

D28

GN

D34

GN

D39

GN

D45

GN

D4

GN

D10

GN

D15

GN

D21

C6

80

.1uF

R2

31

0

C6

10

.1u

F

RN

32

RP

AC

K4

-33

12345 6 7 8

C6

70

.1u

F

R2

64

10K

RN

33

RP

AC

K8

-33

1 2 3 4 5 6 7 8910111213141516

C6

20

.1u

F

R2

26

0

R6

436

0


A-21

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

LU

MA

TV

P5

146

VID

EO

4T

VP

514

6V

IDE

O3

TV

P5

146

VID

EO

1T

VP

514

6V

IDE

O0

TV

P5

146

VID

EO

6T

VP

514

6V

IDE

O7

TV

P5

146

VID

EO

5

TV

P5

146

VID

EO

2

3.3

VA

_D

DE

C3

.3V

D_

DD

EC

1.8

VD

_D

DE

C

3.3

VD

_D

DE

C

3.3

VA

_D

DE

C

3.3

VD

_D

DE

C

1.8

VA

_D

DE

C

3.3

VD

_DD

EC

3.3

VD

_D

DE

C

1.8

VD

_D

DE

C

1.8

VA

_D

DE

C

3.3

VA

_D

DE

C

3.3

VD

_D

DE

C1

.8V

D_

DD

EC

1.8

VA

_D

DE

CV

CC

_1.

8V

VC

C_

3.3

V

VC

C_

1.8

VV

CC

_3

.3V

DDEC_GND

DDEC_GND

DDEC_GNDDDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GNDDDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

DDEC_GND

3V

3.S

YS

_RE

SE

Tz

14

,18,

24,2

7

TV

P5

146

VID

EO

[0:7

]19

TV

P5

14

6V

SY

NC

19

TV

P5

146P

CLK

19

TV

P51

46

HS

YN

C19

3V

3.I

2C

_C

LK

6,2

3,2

43V

3.I

2C

_D

AT

A6

,23

,24

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

203

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

TV

P5

146

VID

EO

DE

CO

DE

R

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

R3

30

2K

R3

32

100

K

C2

88

0.1

uF

C3

33

.1uF

C3

27

0.1

uF

C3

47

0.1

uF

C3

34

0.1

uF

C3

67

33

0pF

C2

86

0.1

uF

C3

45

0.1

uF

C3

35

0.1

uF

Y4 14

.318

18m

hz

C3

40

68

0pF

C3

38

33

0pF

R3

3122

C2

92

33

pF

L41

2.7

uH L28

BLM

41P

750S

PT

12

L43

2.7

uH

L44

2.7

uH

R3

3522

C2

87

0.1

uF

RN

35

RP

AC

K8

-33

1 2 3 4 5 6 7 8910111213141516

C3

323

30

pF

L38

BLM

41P

750S

PT

12

C3

31

0.1

uF

C2

50

0.1

uF

C3

36

0.1

uF

R3

74

75

C2

90

0.1

uF

C2

910

.1u

F

J11

7491

81-1

34 2

1

56

J12

RC

A J

AC

K

1

2

L23

BLM

41P

750

SP

T1

2

C3

39

.1u

F

R3

27

NO

PO

P

R3

360

L37

BLM

41P

750

SP

T1

2

C3

410

.1uF

L39

2.7

uH

C3

370

.1u

F

C3

48

0.1

uF

R3

28

NO

PO

P

C3

446

80p

F

C3

46

0.1

uF

R3

75

75

R2

65

4.7

K

C2

85

0.1

uFC

284

0.1

uF

C3

30

0.1

uF

C3

28

.1u

F

C3

43

.1u

F

C3

263

30pF

U5

1T

VP

514

6

VI_

3_B

17

VI_

3_A

16

VI_

2_B

8

VI_

2_C

9

Y8

44Y

943

Y7

45

TH

ER

MA

L81

CH3_A18GND 15

CH4_A18GND 24

CH1_A18GND 79

DGND4 56

CH1_A33GND 3

CH3_A33GND 19CH2_A33GND 6

VI_

3_C

18

VI_

4_A

23

Y2

52Y

351

Y6

46

CH4_A33GND 22

DGND2 32

DGND3 42

IOGND1 39

IOGND2 49

IOGND3 62

PLL_A18GND 77

DGND1 27

DGND5 68

A18GND_REF 13AGND 26

CH2_A18VDD11

CH3_A18VDD14

CH4_A18VDD25

CH1_A18VDD78

CH1_A33VDD4

CH2_A33VDD5

CH3_A33VDD20

CH4_A33VDD21

A18VDD_REF12

DVDD131

DVDD241

DVDD355

DVDD467

IOVDD138

IOVDD248

IOVDD361

PLL_A18VDD76

VI_

2_A

7

VI_

1_C

2

VI_

1_B

1

VI_

1_A

80

SC

L28

SD

A29

Y5

47

Y4

50

Y1

53

Y0

54

C9

57

C8

58

C7

59

C6

60

C5

63

C4

64

C3

65

C2

66

C1

69

C0

70

XT

AL1

74

XT

AL2

75

DA

TA

CLK

40

RE

SE

TB

34

PW

RD

WN

33

INT

RE

Q30

FS

S/G

PIO

35

GLC

O/1

2CA

37

HS

/CS

/GP

IO72

VS

/VB

LK/G

PIO

73

FID

/GP

IO71

AV

ID/G

PIO

36

CH2_A18GND 10

C3

42

33

0pF

R3

34

2.2

K

C3

49

33p

F

L40

2.7

uH

R3

33

4.7

K

R3

7675

C3

256

80

pF

C32

90

.1u

FC

283

0.1

uF

R3

29

2K

L42

2.7

uH

R2

66

22

TP

62

1

C2

89.1

uF

TP

571

C3

68

33

0pF

TP

561



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

3V3

A_V

OU

T

VO

UT

_O

N

VC

C_3

.3V

DA

C_

3V

3

DA

C_

3V

3

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DENC_GND

DA

C_

3V

3

DENC_GND

DA

C_I

OU

TA

5

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

213

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

VID

EO

OU

TP

UT

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

1812LS-273XJB

1812LS-273XJB

C3

54

10

pF

R3

391

300

1%

J8R

CA

JA

CK

1

2

L27

12u

H

C3

520

.1uF

+C

64

22

0uF

R34

12

67

1%

R3

8010

K

-+

U50

OP

A35

7A

IDB

V

3 4

526

1

+C

63

10

uF

C3

53

10

pF

C3

79

22

0pF

R33

875

L20

12

uH

C3

78

39

pF

L36

1u

H

R2

69

1KR

34

01

K

L12

BLM

41P

750S

PT

C2

51

27

pF

R3

81N

O-P

OP

C2

550

.01

uF

L16

BLM

41P

750S

PT

C2

560

.1u

F

R4

5075


A-23

VC

C_1

.8V

VC

C_

1.8

V

VC

C_

3.3

V

VC

C_

1.8

V

B_

CL

KR

7

B_

FS

R7

B_

DR

7

B_D

X7

B_F

SX

7

B_C

LKX

7

1V

8.I

2C

_D

AT

A6

,26,

27

1V

8.I

2C

_C

LK

6,2

6,2

7

AU

DIO

_C

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5,2

7

1.8

V.S

YS

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SE

Tz

8,1

4,2

5,2

6,2

7,2

9

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5114

52-

0001

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nd

ay,

No

vem

be

r 0

3,

200

822

30

B

TM

S3

20D

M35

7 E

VA

LU

AT

ION

MO

DU

LE

AIC

33

AU

DIO

IN

TE

RF

AC

E

MIC_IN

LINE_IN

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

L49

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21P

G2

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+

C7

61

0uF

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V

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26N

O-P

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22

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F

L50

BLM

21P

G2

21S

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D

C27

9.1

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R3

210

R3

85

5.6

K

R3

88

5.6

K

C2

82

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F

R3

230

R3

151

0

R3

19

20K

C3

16

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F

R3

1210

TP

69

1

C31

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R3

8220

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C3

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C31

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R3

11

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141

0

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86

5.6

K

L48

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76

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172

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R3

161

0

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832

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66

22

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810

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77

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AD

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01

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221

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e O

ut

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24

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AC

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2

1

3

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41

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1

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4

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5

MIC

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2

WC

LKF

9

DO

UT

F8

MP

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MC

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8

SE

LEC

TE

8

SD

AD

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RIG

HT

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DE

TB

2

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81

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F

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1010

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49

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171

0

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75

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20

10

+

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33

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71

330

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80

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F

TP

65

1

L45

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21P

G2

21S

N1D

+

C7

23

3uF

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V

R3

2210

K

R3

723

30C31

9.1

uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_

3.3

V

VC

C_

3.3

V

3V

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2C

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6,2

0,2

43

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AT

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Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mon

da

y, N

ove

mbe

r 0

3,

20

08

233

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

SP

DIF

OU

TP

UT

S &

US

ER

LE

DS

USER CONTROLLED LEDS

C7

9.1

uF

DS

5

LE

DU

2

PC

F8

574

A

GN

D8

P3

7

A0

1

A1

2

A2

3

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4

P2

6P

15

VD

D16

SD

A15

SC

L14

INT

13

P7

12

P6

11

P5

10

P4

9

DS

1

LE

D

DS

6

LE

D

R7

233

0R

71

330

R6

733

0R

6933

0R

70

330

R6

833

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65

330

DS

7

LE

D

DS

8

LE

D

DS

3

LE

D

DS

2

LE

D

DS

4

LE

D

R6

633

0


A-25

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

430_

TE

ST

/VP

P

430_

TM

S

MS

P43

0_3V

3

430_

TD

O

430

_TD

I

430

_TD

I43

0_T

DO

430_

TM

S43

0_T

ES

T/V

PP

430_

TC

K

430_

TC

K

VD

DIM

X_

EN

MS

P43

0_3

V3

VD

DIM

X_E

NP

IO_

0

PIO

_0

PIO

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IO_3

PIO

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IO_5

PIO

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IO_7

PIO

_2

PIO

_3

PIO

_4

PIO

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PIO

_7

PIO

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VC

C_

3.3

VV

CC

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VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_3

.3V

VC

C_

3.3

V

3V

3.I

2C

_DA

TA

6,2

0,2

3

3V

3.S

YS

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ES

ET

z1

4,1

8,2

0,2

7

3V

3.I

2C_

DA

TA

6,2

0,2

33

V3

.I2C

_C

LK

6,2

0,2

3

3V

3.U

AR

T_R

XD

11

4,2

7

3V

3.U

AR

T_T

XD

11

4,2

7

SD

/MM

C.W

P15

SD

/MM

C.I

NS

15

VD

DIM

X_

EN

30

3V

3.I

2C

_C

LK6,

20

,23

MS

P4

30_

INT

14

PL

L.F

S1

5P

LL

.SR

5P

LL

.CS

EL

5

PL

L.F

S2

5

3V

3.I

2C

_D

AT

A6

,20

,23

3V

3.I

2C

_C

LK6

,20

,23

US

ER

_S

W1

0

SP

AR

EIO

114

SP

AR

EIO

214

SP

AR

EIO

314

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

243

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

MS

P4

30

& I

R I

NT

ER

FA

CE

R7

410

K

Y1

32.7

68K

Hz

RN

25

RP

AC

K4

-10

K

12345

678

R9

80

C1

00.1

uF

R1

030

RN

22

RP

AC

K8-

10

K

123456789

10111213141516

R7

510

0D

4B

AT

17

C8

5

0.1

uF

L1

BLM

41P

750

SP

T

BH

T1

BA

203

2SM

2 1

U3

TS

OP

3484

0

23 1

U4

MS

P43

0F

123

2IP

W

VCC2

P2.

0/A

CLK

8

P2.

1/IN

CLK

9

XIN

6

XO

UT

5

VSS 4

P1.

0/T

AC

LK21

TE

ST

1

P2.

2/C

AO

UT

/TA

010

RS

T/N

MI

7

P1.

1/T

A0

22

P1.

2/T

A1

23

P1.

3/T

A2

24

P1.

4/S

MC

LK/T

CK

25

P1.

5/T

A0/

TM

S26

P1.

6/T

A1/

TD

I27

P1.

7/T

A2/

TD

O28

P2.

3/C

A0/

TA

119

P2.

4/C

A1/

TA

220

P2.

5/R

OS

C3

P3.

0/S

TE

0/A

511

P3.

1/S

IMO

012

P3.

2/S

OM

I013

P3.

3/U

CLK

014

P3.

4/U

TX

D0

15

P3.

5/U

RX

D0

16

P3.

6/A

617

P3.

7/A

718

R9

7N

O-P

OP

R1

04

47K

U3

5

PC

F8

574

A

GN

D8

P3

7

A0

1

A1

2

A2

3

P0

4

P2

6P

15

VD

D16

SD

A15

SC

L14

INT

13

P7

12

P6

11

P5

10

P4

9

J2

HE

AD

ER

7X

2

TD

O/T

DI

1N

C2

2T

DI/V

PP

3V

CC

_MS

P4

TM

S5

XO

UT

6T

CK

7T

ES

T/V

PP

8G

ND

9A

CLK

10R

ST

/NM

I11

AC

LKE

N12

NC

113

TC

LKE

N14

D3

BA

T1

7

J18

HE

AD

ER

8-2

MM1 2 3 4 5 6 7 8

C8

4.1

uF

J19

HE

AD

ER

8-2

MM

1 2 3 4 5 6 7 8

U1

8

PC

F85

74A

GN

D8

P3

7

A0

1

A1

2

A2

3

P0

4

P2

6P

15

VD

D16

SD

A15

SC

L14

INT

13

P7

12

P6

11

P5

10

P4

9

+C

13

10

uF

6.3

V

TP

41

R1

0510

0K

R9

6N

O-P

OP

+C

11

0u

F 6

.3V

C83

.1u

F C1

93.1

uF

R2

73

0



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

_A16

EM

_A18

EM

_A12

EM

_A7

EM

_A14

EM

_A21

EM

_A5

EM

_A9

EM

_A8

EM

_A11

EM

_A6

EM

_A17

EM

_A10

EM

_A3

EM

_A13

EM

_A19

EM

_A15

EM

_A20

EM

_A4

EM

_D

14

EM

_D

10

EM

_D

12

EM

_D

8

EM

_D

4E

M_

D6

EM

_D

2E

M_

D0

EM

_D

15

EM

_D

11E

M_

D13

EM

_D

9

EM

_D

5E

M_

D7

EM

_D

3E

M_

D1

VC

C_

1.8

VV

CC

_5

V

VC

C_

3.3

VV

CC

_3.3

V

EM

_BA

13

,14

GP

IO5

13

,14 W

RIT

E_

WE

3,1

2,1

4R

EA

D_

OE

3,1

2,1

4E

M_

RN

W3

,14

EM

_BA

03

,14

GP

IO5

23

,14

ALE

_EM

_A1

3,1

2,1

4C

LE

_E

M_A

23,

12

,14

EM

_A0

3,1

4

DC

_E

M_

CS

210

WA

IT/B

US

Y3

,14

EM

_CS

33

,14

CL

KO

UT

08

1.8

V.S

YS

_R

ES

ET

z8

,14

,22

,26

,27

,29

EM

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3,1

2,1

4E

M_

D1

3,1

2,1

4E

M_D

23

,12

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EM

_D

33,

12

,14

EM

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3,1

2,1

4E

M_

D5

3,1

2,1

4E

M_D

63

,12

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EM

_D

73,

12

,14

EM

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3E

M_

D9

3

EM

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3E

M_D

113

EM

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3E

M_D

133

EM

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3E

M_D

153

EM

_A3

3,1

4E

M_A

43

,14

EM

_A5

3

EM

_A6

3E

M_A

73

EM

_A8

3E

M_A

93

EM

_A10

3E

M_

A1

13

EM

_A12

3E

M_

A1

33

EM

_A14

3E

M_

A1

53

EM

_A16

3E

M_

A1

73

EM

_A18

3E

M_

A1

93

EM

_A20

3E

M_

A2

13

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

253

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

EM

IF E

XP

AN

SIO

N C

ON

NE

CT

OR

EMIF CONNECTOR

DC

1

HE

AD

ER

35x

2

11

33

55

77

99

1111

1313

1515

1717

1919

2121

2323

2525

2727

2929

3131

3333

3535

3737

3939

4141

4343

4545

4747

4949

5151

5353

5555

5757

5959

6161

6363

6565

6767

6969

22

44

66

88

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

4646

4848

5050

5252

5454

5656

5858

6060

6262

6464

6666

6868

7070


A-27

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_1

.8V

VC

C_

1.8

V

VC

C_

1.8

VV

CC

_1.8

V

VC

C_

5VV

CC

_5

V

VC

C_

5V

VC

C_

5V

VC

C_

3.3

VV

CC

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V

VC

C_

3.3

VV

CC

_3.

3V

GIO

36

GIO

66

CO

UT

05

,10

CO

UT

25

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GIO

06

CO

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45

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26

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56

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YN

C5

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UT

15

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65

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05

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UT

25

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UT

45

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UT

35

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YN

C5

CO

UT

75

CO

UT

55

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UT

15

,10

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UT

35

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YO

UT

55

YO

UT

75

YI0

5,1

9

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5,1

9

CI0

5C

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PC

LK

5,1

9

YI4

5,1

9Y

I25

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5,1

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I35

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5,1

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I35

GIO

46

PW

M2

5

HD

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9V

D5

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AT

A6

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16

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E_

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19

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ET

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29

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

263

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

VID

EO

IN

PU

T/O

UT

PU

T C

ON

NE

CT

OR

S

VIDEO INPUT CONNECTOR

VIDEO OUTPUT CONNECTOR

DC

4

HE

AD

ER

25X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

R2

68N

O-P

OP

R2

67N

O-P

OP

DC

5

HE

AD

ER

25X

2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

R2

25

NO

-PO

P



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_

5V

VC

C_

3.3

V

VC

C_

5V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_3

.3V

VC

C_

5V

VC

C_

1.8

V

VC

C_

1.8

V

GIO

V33

_16

,18

GIO

V33

_36

,18

GIO

V33

_56

,18

GIO

V33

_76

,18

GIO

V33

_96

,18

GIO

V33

_1

16

,18

GIO

V33

_1

36

,18

GIO

V33

_1

56

,18

GIO

V33

_0

6,1

8G

IOV

33_

26

,18

GIO

V33

_4

6,1

8

GIO

V33

_6

6,1

8G

IOV

33_8

6,1

8G

IOV

33_

106

,18

GIO

V3

3_12

6,1

8G

IOV

33_

146

,18

GIO

V3

3_16

6,1

8

SP

I_C

LK

6

CLK

R7

FS

R7

DR

7

SP

I_D

O6

DX

7

FS

X7

CLK

X7

SP

I_E

N0

6S

PI_

DI

6S

PI_

EN

16

SD

_C

LK

7,1

5 SD

_D

AT

A2

7,1

5

SD

_C

MD

7,1

5

SD

_DA

TA

17

,15

SD

_DA

TA

37

,15

SD

_D

AT

A0

7,1

5

1V

8.I

2C

_DA

TA

6,2

2,2

6

EN

ET

_EN

AB

LEz

18

AU

DIO

_C

LK

5,2

21

.8V

_D

C3

_P

CL

K19

McB

SP

_E

N7

1V

8.I

2C

_C

LK

6,2

2,26

1.8

V.S

YS

_R

ES

ET

z8

,14

,22

,25

,26,

29

TIM

ER

_IN

_DC

314

3V

3.S

YS

_R

ES

ET

z1

4,1

8,2

0,2

4

3V3

.UA

RT

_TX

D1

14

,24

3V

3.U

AR

T_

RX

D1

14

,24

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

273

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

EM

AC

/GIO

& M

cBS

P/S

PI

& S

D C

ON

NE

CT

OR

S

DC

2

HE

AD

ER

20

X2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

DC

6

HE

AD

ER

5X

2

2 4 6 8 10

1 3 5 7 9

R2

63

NO

-PO

P

DC

3

HE

AD

ER

15

X22 4 6 8 10 12 14 16 18 20 22 24 26 28 30

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29


A-29

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TI_

EM

U0

TI_

PW

R_

DE

CT

TI_

TC

K_

RE

TT

I_T

CK

TI_

EM

U1

B_ARM_TCKRET

AR

M_

TD

I

AR

M_T

DO

AR

M_

TC

K

AR

M_T

RS

Tn

AR

M_T

MS

ARM_TDO

AR

M_

TC

KR

ET

TI_

TR

ST

n

TI_

TM

ST

I_T

DI

TI_

TD

O

AR

M_R

ST

n

ARM_TCK

ARM_TRSTn

ARM_TDI

ARM_TMS

VC

C_1

.8V

VC

C_3

.3V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_3

.3V

VC

C_

3.3

VV

CC

_1.

8V

VC

C_

3.3

VV

CC

_1.

8V

VC

C_

3.3

V

VC

C_

3.3

V

DS

P_

EM

U0

8D

SP

_E

MU

18

DS

P_T

DO

8D

SP

_R

TC

K8

DS

P_

TD

I8

DS

P_T

MS

8

DS

P_T

RS

T#

8D

SP

_T

CK

8

EM

ULA

TO

R_R

ST

n29

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

283

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

DA

VIN

CI

EM

UL

AT

ION

HE

AD

ER

KEY

14 PIN TI JTAG INTERFACE

OE DIR FUNCTION

L L B->A

L H A->B

C2

52.1

uF

R9

033

R44

3N

O-P

OP

C3

05

.1u

F

U7

0

74

AV

C4T

245

VC

CA

1

1DIR

2

2DIR

3

1A1

4

1A2

5

2A1

6

2A2

7

GN

DA

8G

ND

B9

2B2

102B

111

1B2

121B

113

2OE

n14

1OE

n15

VC

CB

16

R4

48

33

R9

133

S1

CA

SD

20T

B

1 2 3

4 5 6

R8

520

KR

8620

K

C2

53

.1u

F

R44

210

K

R4

49

33

R8

42

.2K

J13

TS

W-1

07-1

4-G

-D-0

06

TR

ST

2

GN

D4

nc6

GN

D8

GN

D10

GN

D12

EM

U1

14

TM

S1

TD

I3

PD

5

TD

O7

TC

KR

ET

9

TC

K11

EM

U0

13

R8

210

K

R8

90

R83

2.2

K

R9

333

R1

32

33

R8

70

J15

SA

MT

EC

-TS

M-1

10-D

V

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

R9

533

R4

44N

O-P

OP

R9

233

R44

50

R9

433

R8

1N

O-P

OP

U6

9

74

AV

C4T

245

VC

CA

1

1DIR

2

2DIR

3

1A1

4

1A2

5

2A1

6

2A2

7

GN

DA

8G

ND

B9

2B2

102B

111

1B2

121B

113

2OE

n14

1OE

n15

VC

CB

16

R8

833

C2

54.1

uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PB

SW

_RS

Tz

VC

C_

5V

AG

ND

VC

C_

5V

VC

C_

3.3

V

VC

C_

3.3

VV

CC

_1.

8V

VC

C_3

.3V

VC

C_3

.3V

VC

C_

3.3

V

VC

C_

3.3

V

CO

RE

_V

DD

VC

C_

3.3

V

VC

C_

3.3

V

VC

C_

1.8

V

1.8

V.S

YS

_R

ES

ET

z8

,14

,22

,25

,26

,27

EM

UL

AT

OR

_R

ST

n28

3V3

_PW

R_

OK

30

1V8

_PW

R_

OK

30

1V2

_PW

R_

OK

30

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

293

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

PO

WE

R S

UP

PL

Y (

3.3

V )

& S

YS

TE

M R

ES

ET

LO

GIC

3.3 sq in AGND,

min

thermal pad

Connect

at pin 1

Sets

Voltage

3.3V @1.5Amp Max

2.5

MM

JA

CK

PO

WE

R IN

PUT

BBB

AAA

SENSE THRESHOLD FOR TPS3808G01 IS 0.405 VOLTS

BOXMOUNTING HOLES

CASE SHIELDING TABS FOR POWER SUPPLY

SENSE THRESHOLD FOR TPS3808G09 IS 0.840 VOLTS

X1

1

C9

81

000p

F

R2

90

.025

R2

50

10K

R1

60N

O-P

OP

U19

TP

S5

431

0PW

P

AG

ND

1

VS

EN

SE

2

CO

MP

3

PW

RG

D4

BO

OT

5

PH

16

PH

27

PH

38

PH

49

PH

510

PG

ND

111

PG

ND

212

PG

ND

313

VIN

114

VIN

215

VIN

316

VB

IAS

17S

S/E

NA

18S

YN

C19

RT

20P

OW

ER

PA

D21

C2

41

NO

-PO

P

TP

1 1

L4

BLM

41P

750S

PT

C2

1

0.0

47

uF

C2

38

0.1

uF

R2

480

R2

53

10K

R2

541

0K

L33

.3 u

H

TP

28

1

TP

68 1

R2

56

0

X4

1

R2

45

33

C2

5

0.1

uF

R3

89

no-p

op

+C

144

7u

F

TP

34

1

R1

281

07

1%

C9

9

NO

-PO

P

TP

13 1

X5

1

TP

27

1

Z4

1

R2

5210

KZ

51

TP

15

1

X3

1

+C

24

10

uF

LE

SR

C2

333

00pF

C2

39

NO

-PO

P

F1

F_

4.0

A

12

U4

5

TP

S3

808

G0

9DB

VR

VD

D6

MR

3

SE

NS

E1

5

CT

4

GN

D2

RE

SE

T1

Z1

1

C2

24

70

pF

R2

46

10K

TP

5

1

C2

6

0.0

39

uF

R3

03

.74

K 1

%

C2

37

NO

-PO

P

U4

6

TP

S38

08G

09D

BV

R

VD

D6

MR

3

SE

NS

E1

5

CT

4

GN

D2

RE

SE

T1

TP

33

1

R1

00

220

R2

47

10K

TP

2 1

R2

4910

KR2

55

1K

TP

70 1

C3

9

0.1

uF

C9

60

.1u

F

R2

51

10K

TP

14

1

D7

SM

CJ6

A

C2

36

1u

F

+

C3

6910

0u

F 4

V

C9

782

00p

F C2

400

.1u

F

R15

9N

O-P

OP

DS

9

GR

EE

N

+

C2

01

00u

F 4

V

U4

4

TP

S3

808

G0

9DB

VR

VD

D6

MR

3

SE

NS

E1

5

CT

4

GN

D2

RE

SE

T1

TP

3 1D

5B

AS

16-7

C2

42

0.1

uF

Z2

1

R3

1

71

.5K

1%

R1

291

0K

1%

R1

302

K 1

%

S4

PU

SH

BU

TT

ON

SW

TP

16

1

J14

RA

SM

712

CE

NT

ER

SH

UN

TS

LEE

VE

SW

1S

WIT

CH

3

1

6

4

52 78

J6 HE

AD

ER

21 2

R1

31

10K

+C

19

10

0 u

F

Z3

1

X2

1


A-31

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

3V

3_P

WR

_O

K

1V

8_P

WR

_OK

1V2_

PW

R_

OK

1V2

_PW

R_

OK

1V8

_PW

R_

OK

3V3

_PW

R_

OK

VC

C_

1.8

V

AG

ND

AG

ND

CO

RE

_V

DD

VC

C_

5V

VC

C_

5V

CO

RE

_V

DD

MIX

VC

C_5

VV

CC

_5

V

VC

C_

1.8

VV

CC

_1

.8V

CO

RE

_S

UP

PL

Y

CO

RE

_S

UP

PL

YC

OR

E_

SU

PP

LY

VC

C_

5V

VC

C_

3.3

V

VC

C_

5V

VD

DIM

X_

EN

24

VD

DIM

X_E

N2

4

3V3_

PW

R_

OK

29

1V8

_PW

R_

OK

29

1V2_

PW

R_O

K29

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5114

52-0

001

Mo

nda

y, N

ove

mb

er

03

, 2

008

303

0

B

TM

S32

0D

M3

57 E

VA

LUA

TIO

N M

OD

ULE

PO

WE

R S

UP

PL

Y (

1.8

V &

DS

P_

CO

RE

) &

EV

M P

OW

ER

CO

NN

3.3 sq in AGND,

min

thermal pad

Connect

at pin

1

Sets

Voltage

3.3

sq

in A

GN

D,

min

the

rma

l pad

Co

nn

ect

at

pin

1

1.2V -> 28.0K 1%

1.05V -> 56.0K 1%

CORE VOLTAGE SUPPORT FOR 0.95 TO 1.2 VOLTS

0.95V -> 150K 1%

C42

56

0pF

R14

51

07

1%

C1

61

100

0pF

R1

461

0K

1%

TP

351

R1

63

NO

-PO

P

TP

361

R1

10K

L9

BLM

41P

750S

PT

+C

32

10

0 u

F

C1

60

NO

-PO

P

C3

7

0.1

uF

R1

85

1.6

5K

1%

TP

37

1U

27

TP

S54

310P

WP

AG

ND

1

VS

EN

SE

2

CO

MP

3

PW

RG

D4

BO

OT

5

PH

16

PH

27

PH

38

PH

49

PH

510

PG

ND

111

PG

ND

212

PG

ND

313

VIN

114

VIN

215

VIN

316

VB

IAS

17S

S/E

NA

18S

YN

C19

RT

20P

OW

ER

PA

D21

+C

54

10

uF L

ES

R

R18

31

07 1

%

TP

12

1

+C

44

10

uF L

ES

R

U31

AO

340

4

G G

SS

DD

C12

20

.1u

F

R1

88

100K

C4

6

0.0

39u

F

L7

BLM

41P

750S

PT

C53

0.0

47u

F

R4

23

0

C1

590

.01u

F

C1

92 NO

-PO

P

R3

95

10K

R1

62

NO

-PO

P

C5

6

0.1

uF

C34

0.0

47u

F

R1

86

10K

R3

91

0.2

K 1

%

C4

5

0.1

uF

U3

6A

O34

04

G G

SS

DD

R18

7N

O-P

OP

C1

96

NO

-PO

P

C1

238

200

pF

R2

10K

C1

911

000

pF

U3

7 UM

C2

N

DT

R2C

4D

TR

2E3

DT

R1B

2

DT

R1C

/DT

R2B

6D

TR

1E1

R50

71

.5K

+C

41

10

0u

F 4

V

TP

26

1

C5

5

0.1

uF

+C

33

100

uF

C3

8

0.0

39

uF

C12

4

100

0pF

R1

47

2K

1%

C35

47

0pF

+C

50

10

0 u

F

R1

84

10

K 1

%

R4

0

71.5

K 1

%

C15

80

.1u

F

R4

928

.0K

1%

+C

52

100

uF

4V

R2

0910

K

+C

51

10

0 u

F

L8

2.7

uH

DC

7

HE

AD

ER

5X

2

2 4 6 8 10

1 3 5 7 9

TP

25

1

R1

890

TP

43

1L

112

.7 u

H

R3

80

.025

C4

33

300p

F

U3

8

TP

S54

310P

WP

AG

ND

1

VS

EN

SE

2

CO

MP

3

PW

RG

D4

BO

OT

5

PH

16

PH

27

PH

38

PH

49

PH

510

PG

ND

111

PG

ND

212

PG

ND

313

VIN

114

VIN

215

VIN

316

VB

IAS

17S

S/E

NA

18S

YN

C19

RT

20P

OW

ER

PA

D21

C3

63

300

pF

R5

90

.025

R2

10

NO

-PO

P

TP

441

R1

64

NO

-PO

P

TP

291

B-1

Appendix B

Mechanical Information

This appendix contains the mechanical information about the DM357EVM produced by Spectrum Digital.


B-2 DM357 EVM Technical Reference

TH

IS D

RA

WIN

G IS

NO

T T

O S

CA

LE


B-3


B-4 DM357 EVM Technical Reference

Printed in U.S.A., December 2008511455-0001 Rev A