Introductory Lectures in VLSI Physical Design Algorithms Jens Lienig, Springer Verlag Berlin Heidelberg New York, 2006 1 Introduction 3 1.1 Electronic Design Automation (EDA) 3 1.2 About this Book 4 1.3 Impact of Electronic Design Automation 6 1.4 History of Electronic Design Automation 7 1.5 VLSI Design Cycle 9

1.5.1 System Specification 9 1.5.2 Architectural Design 10 1.5.3 Functional Design 10 1.5.4 Logic Design 10 1.5.5 Physical Design 11 1.5.6 Layout Verification 12 1.5.7 Fabrication 13 1.5.8 Packaging, Testing 13

1.6 Layout Design Styles 14 1.6.1 Full-Custom 14 1.6.2 Standard Cells 15 1.6.3 Macro Cells 17 1.6.4 Gate Arrays 17

1.7 Layout Layers 19 1.8 Design Rules 20 1.9 Optimization Problems of Physical Design 21 1.10 Computational Complexity of Physical Design 23 1.11 Classification of Physical Design Algorithms 25 1.12 Solution Quality 27 1.13 Basic Terms and Definitions in Graph Theory 27 1.14 Terminology 30 Bibliography 34 2 Partitioning 37 2.1 Introduction 37 2.2 Terminology 38 2.3 Objective Functions 39

2.3.1 External Wiring 39 2.3.2 Bounded Size Partitioning 40

2.4 Partitioning Algorithms 40 2.4.1 Kernighan-Lin (KL) Algorithm 41 2.4.2 Extensions of Kernighan-Lin Algorithm 45 2.4.3 Fiduccia-Mattheyses (FM) Algorithm 46 2.4.4 Simulated Annealing (SA) Algorithm 54

Exercises 60 Bibliography 60 3 Floorplanning 63 3.1 Introduction 63 3.2 Objective Functions 65

3.2.1 Area of the Bounding Box 65 3.2.2 Overall Wirelength 65 3.2.3 Area and Overall Wirelength 66 3.2.4 Signal Delays 66

3.3 Terminology 66 3.4 Floorplanning Algorithms 70

3.4.1 Floorplan-Sizing Algorithm 70 3.4.2 Cluster Growth 76 3.4.3 Other Floorplanning Algorithms 80

3.5 Pin Assignment 81 3.5.1 Problem Definition 81 3.5.2 Concentric Circle Mapping 82 3.5.3 Topological Pin Assignment 84

Exercises 86 Bibliography 88 4 Placement 91 4.1 Introduction 91 4.2 Objective Functions 92

4.2.1 Overall Weighted Wirelength 93 4.2.2 Maximum Cut 95 4.2.3 Local Density 97 4.2.4 Signal Delays 98

4.3 Placement Algorithms 99 4.3.1 Min-Cut Placement 100 4.3.2 Min-Cut Placement with Terminal Propagation 104 4.3.3 Force Directed Placement 106 4.3.4 Simulated Annealing 110 4.3.5 Quadratic Assignment 114 4.3.6 Other Placement Algorithms 117

Exercises 123 Bibliography 124 5 Global Routing 129 5.1 Introduction 129

5.1.1 General Routing Problem 129 5.1.2 Global Routing 130

5.2 Terminology 131 5.3 Objective Functions 135

5.3.1 Full-Custom 135 5.3.2 Standard Cells 136 5.3.3 Gate Arrays 138

5.4 Routing Regions Representation 138 5.5 Outline of Global Routing 140 5.6 Global Routing Algorithms 141

5.6.1 Steiner Tree Routing 142 5.6.2 Graph-based Global Routing by Maze Running 146 5.6.3 Path Search with Dijkstra Algorithm 150

Exercises 155 Bibliography 156 6 Detailed Routing 159 6.1 Introduction 159 6.2 Terminology 159 6.3 Constraint Graphs 163

6.3.1 Horizontal Constraint Graph 163 6.3.2 Vertical Constraint Graph 164

6.4 Objective Functions 167 6.5 Algorithms for Channel Routing 167

6.5.1 Left-Edge Algorithm 167 6.5.2 Dogleg Left-Edge Algorithm 169 6.5.3 Greedy Channel Router 172

6.6 Switchbox Routing 176 6.6.1 Problem Formulation 176 6.6.2 Algorithms for Switchbox Routing 177

6.7 OTC Routing 178 6.7.1 Problem Formulation 178

6.7.2 Algorithms for OTC Routing 180 Exercises 182 Bibliography 183 7 Area Routing 187 7.1 Introduction 187 7.2 Terminology 189 7.3 Ordering of Nets 191 7.4 Manhattan and Euclidean Metrics 193 7.5 Routing of Power and Ground Nets 194 7.6 Objective Functions 196 7.7 Sequential Routing Algorithms 197

7.7.1 Lee Algorithm 197 7.7.2 Maze Routing with Weighted Paths 203 7.7.3 Line Search Algorithms 207

7.8 Semi-Parallel Routing 211 7.8.1 Hierarchical Routing 211 7.8.2 Rip-Up and Reroute 212

7.9 Three-Dimensional Routing 215 7.9.1 Maze Routing 216 7.9.2 Multiple Stage Routing 217 7.9.3 Planar Routing 217 7.9.4 Tower Routing 218

7.10 X-Routing 220 7.10.1 Octilinear Minimum Steiner Trees 220 7.10.2 Octilinear Path Search 222

Exercises 223 Bibliography 225 8 Compaction 229 8.1 Introduction 229 8.2 Terminology 230 8.3 Symbolic Layout 232 8.4 Compaction Algorithms 233

8.4.1 Virtual Grid Compaction 233 8.4.2 Constraint Graph Compaction 236

Exercises 242 Bibliography 243 Appendix A Solutions to the Exercises 247

Chapter 2. Partitioning 247 Chapter 3. Floorplanning 249 Chapter 4. Placement 251 Chapter 5. Global Routing 253 Chapter 6. Detailed Routing 254 Chapter 7. Area Routing 257 Chapter 8. Compaction 259

Appendix B Terminology, Symbols, File Formats 263

B.1 Abbreviations and Terminology in Physical Design 263 B.2 Schematic Symbols of Devices and Cells 266 B.3 Layout Examples of CMOS Standard-Cells 269 B.4 Layout File Formats 270

Subject Index