tomasulotutorial

8/3/2019 tomasuloTutorial

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Tomasulo Algorithm

Register renaming provided

-by reservation stations, which buffer the operands of instructions waiting to issue

-by the issue logic

Basic idea:-a reservation station fetches and buffers an operand as soon as it is available, as eliminating the needthe operand from a register (WAR)-pending instructions designate the reservation station that will provide their input (RAW)-when successive writes to a register overlap in execution only the last one is actually used to updateregister (WAW)

As instructions are issued, the register markers for pending operands are renamed to the names of thereservation station, which provides register renaming (more reservation stations than real registers)

Properties of Tomasulo Algorithm

1. Control & Buffers distributed with Function Units (FU)-Hazard detection and execution control are distributed-FU buffers called, reservation stations have pending operands-Registers in instructions replaced by values or pointers to reservation stations (RS)

2. Bypassing: Results passed directly to FU from RS, not through registers, over common data b(CDB)

-that broadcasts results to all FUs, so allows all units wait for an operand to be loadedsimultaneously

Components of Reservation Station

Op: Operation to perform in the unitQj, Qk: Reservation stations producing the corresponding source operand.

If a value of Qj or Qk is zero, the source operand is already available in Vj or Vkor not necessary.

Vj, Vk: Value of Source operands

-only one of V field or the Q field is valid-store buffers has V field, result to be stored

A: Used to hold information for the memory address calculation for a load or a storeBusy: Indicates reservation station or FU is busyRegister result status Qi: Indicates which functional unit will write each register, if one exists. Blankno pending instructions that will write that register

Three stages of Tomasulo Algorithm


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1. Issue get instruction from FP OP Queue

If reservation station is free (no structural hazard), control issues instructions and sends opera(renames registers).

2.

Execute operate on operandsWhen both operands are ready, then execute; if not ready, watch Common Data Bus (CDB) foresult.

3. Write result (commit) finish executionWrite on CDB to all awaiting units; mark reservation station available.

Note: Some other books or journals use commit instead of write result thatam really confused, especially in Tomasulo algorithm tables. The are bas

same words.

Basic Structure of a MIPS FU unit using Tomasulos algorithm


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Tomasulo example (Loop)

Loop:

mul $t4,$t2

mflo $t4

subi $t3,$t3,1

bgtz $t3,loop ! branch on greater than zero

this code calculate $t4 = $t2 ^ $t3, and initially $t4 = 1 and $t2 = 5 and $t3 = 2

add/sub/move takes 1 cycle of executemultiply takes 2 cycles

branch takes 2 cycles

two instructions are issued per cycle in this tomasulo example.

When I try to understand Tomasulo tables, I am so confused to understand each tables and the

fields, so I will explain them in here before I following the tables in each cycle .

Reorder Buffer

Entry Busy Instruction State Destination Value------

Reorder Buffer

-Allows instructions to execute out of order, but complete in order

--Each instruction is allocated a reorder buffer entry at the tail of the buffer--Instructions write into their entry--Instructions complete out of the buffer in-order

Entry->The number of order the machine is reading in

Busy->If the register is in use, yes

Instruction->The actual instruction goes here

State->Three states go here

Issue - Issue the instruction if there is an empty reservation station and an empty slot in


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Reorder buffer. If they are in the register file or reorder buffer, send the operan

to the reservation station. Store the reorder buffer entry in the reservation stati

the result can be tagged when it is written to the CDB

Execute-Monitor CDB for results and execute operations from reservation stations when

Operands are ready

Commit-When both the address and data value are available, they are sent to the memoUnit and the store complete. Then mark reservation stations available.

Destination->The location of the register where the result will go

Value->Value will be generated in the commit state

Registers

Field Data Reorder Busy$t0$t1

---Field the register locationData value stored in the registerReorder The entry line of code from Reorder Buffer associated with the registerBusy yes if the register is in use

Reservation Station

Name Busy Op V1 V2 S1 S2 Dest A-

---Name This is just name tag for the operand where you can keep track of operations.

The generic names are load, add, mult, br, shift(sub/div/mflo/mfhi dont havetheir own name tags. When sub needed, it goes to add, as div to mult, mflo/mfhi

to add)Busy yes if the register is in useOp this is actual Op working onV1/V2(Vj and Vk in our Textbook) These contain the value sof the source operands.

Only one of the V field or S field is valid for each operand

S1/S2(Qj and Qk in our Textbook) The reservation stations that will produce the correspondingSource operand. A value of zero indicates that the sourceOperand is already available in V1 or V2 or unnecessary

Dest The location of the register that the resulting calculation will go

A holding information for the memory address calculation for load and store


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cycle 1

Reorder Buffer Registers

Entry Busy Instruction State Destination Value Field Data Reorder Bus1 y mul $t4,$t2 issue $Hi, $Lo $t02 y mflo $t4 issue $t4 $t13 $t2 54 $t3 25 $t4 1 #2 y6 $t57 $t68 $t79 $t810 $t9

Reservation Station

Name Busy Op V1 V2 S1 S2 Dest A

Add1 mflo #1 #2Add 2Add3Add4

Mul1 mul 1 5 #1Mul2

Br1

Br2

In cycle 1, we issue the mul and mflo. As we explained in the Reservation Station, mflo goes to Addraw and its source from entry 1 and destination is entry 2($t4). mul goes Mul1 raw and itsdestination is entry 1 which is Hi/Lo, and will stall the mflo in the second cycle.Register also shows initial values like$t4 = 1, $t2 = 5, and $t3 = 2.


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cycle 2


Entry Busy Instruction State Destination Value Field Data Reorder Bus1 y mul $t4,$t2 exec $Hi, $Lo $t02 y mflo $t4 issue $t4 $t13 y subi $t3,$t3,1 issue $t3 $t2 54 y bgtz $t3,loop issue $t3 2 #3 y5 $t4 1 #2 y6 $t57 $t68 $t79 $t810 $t9

Reservation Station


Add1 mflo #1 #2Add 2 subi 2 1 #3Add3Add4

Mul1 y mul 1 5 #1Mul2

Br1 bgtz #3 #1

Br2

In cycle 2, we issue subi andbgtz. We put subi to Add2 andbgtz to Br1.Then we check to see ifmul is ready to execute. Since no other operands use Hi/Lo, it willgo to execute state, but this stage makes mflo must wait till mul completes executewhich creates RAW hazard. Then, entry 2 is handled by $t4 and entry 3 is by $t3.


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cycle 3


Entry Busy Instruction State Destination Value Field Data Reorder Bus1 y mul $t4,$t2 exec $Hi, $Lo $t02 y mflo $t4 issue $t4 $t13 y subi $t3,$t3,1 exec $t3 $t2 54 y bgtz $t3,loop issue $t3 2 #3 y5 y mul $t4,$t2 issue $Hi,$Lo $t4 1 #6 y6 y mflo $t4 issue $t4 $t57 $t68 $t7

9 $t810 $t9

Reservation Station


Add1 mflo #1 #2Add 2 y subi 2 1 #3Add3 mflo #5 #6Add4

Mul1 y mul 1 5 #1

Mul2 mul 5 #2 #5Br1 bgtz #3 #4Br2

In cycle 3, subi is executed because of t3 is free. Second mul/mflo instructions are issued.


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cycle 4


Entry Busy Instruction State Destination Value Field Data Reorder Bus1 no mul $t4,$t2 commit $Hi, $Lo 5 $t02 y mflo $t4 exec $t4 $t13 n0 subi $t3,$t3,1 done $t3 1 $t2 54 y bgtz $t3,loop exec $t3 1 #7 y5 y mul $t4,$t2 issue $Hi,$Lo $t4 1 #6 y6 y mflo $t4 issue $t4 $t57 y subi $t3,$t3,1 issue $t3 $t68 y bgtz $t3,loop issue $t79 $t8

10 $t9

Reservation Station


Add1 yes mflo 5 #2Add 2 subi 1 1 #7Add3 mflo #5 #6Add4

Mul1Mul2 mul 5 #2 #5

Br1 yes bgtz 1 #4Br2 bgtz #7 #8

In cycle 4, mul is now in commit state and of value 5 is stored. subi is also done and stores value 1.


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cycle 5


Entry Busy Instruction State Destination Value Field Data Reorder Bus1 $t02 n mflo $t4 commit $t4 5 $t13 n subi $t3,$t3,1 commit $t3 1 $t2 54 y bgtz $t3,loop exec $t3 1 #7 y5 y mul $t4,$t2 exec $Hi,$Lo $t4 5 #10 y6 y mflo $t4 issue $t4 $t57 y subi $t3,$t3,1 exec $t3 $t68 y bgtz $t3,loop issue $t79 y mul $t4,$t2 issue $Hi, $Lo $t810 y mflo $t4 issue $t4 $t9

Reservation Station


Add1 mflo 5 #9 #10Add 2 yes subi 1 1 #7Add3 mflo #5 #6Add4

Mul1 mulMul2 mul 5 #2 #5

Br1 yes bgtz 1 #4

Br2 bgtz #7 #8

In this cycle 5, first mul is cleared in entry 1, and second mul is in execute.third mul/mflo instructions are issued. First subi is commit state, and second subi isexecuted. Second mflo is waiting for entry 5 to use t4.


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cycle 6


Entry Busy Instruction State Destination Value Field Data Reorder Bus1 y subi $t3,$t3,1 issue $t3 $t02 y bgtz $t3,loop issue $t13 $t2 54 n bgtz $t3,loop commit $t3 1 #1 y5 y mul $t4,$t2 exec $Hi,$Lo $t4 5 #10 y6 y mflo $t4 issue $t4 $t57 n subi $t3,$t3,1 done $t3 0 $t68 y bgtz $t3,loop issue $t7

9 y mul $t4,$t2 issue $Hi, $Lo $t810 y mflo $t4 issue $t4 $t9

Reservation Station


Add1 mflo #9 #10Add 2 subi 0 1 #1Add3 mflo #5 #6Add4

Mul1 mul 5 #6 #9

Mul2 yes mul 5 5 #5Br1 bgtz #2 #2Br2 yes bgtz 0 #8

Third subi/bgtz is issued in entry 1 and 2. First subi in entry 3 is cleared.


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cycle 7


Entry Busy Instruction State Destination Value Field Data Reorder Bus1 y subi $t3,$t3,1 issue $t3 $t02 y bgtz $t3,loop issue $t13 $t2 54 $t3 1 #1 y5 n mul $t4,$t2 commit $Hi,$Lo 25 $t4 5 #10 y6 y mflo $t4 exec $t4 $t57 n subi $t3,$t3,1 done $t3 0 $t68 y bgtz $t3,loop exec $t79 y mul $t4,$t2 issue $Hi, $Lo $t8

10 y mflo $t4 issue $t4 $t9

Reservation Station


Add1 mflo #9 #10Add 2 subi 0 1 #1Add3 y mflo 25 #6Add4

Mul1 mul 5 #6 #9Mul2

Br1 bgtz #2 #2Br2 yes bgtz 0 #8

In cycle 7, mul in entry 5 is committed and value 25 is stored. Seond subi is also done andvalue 0 is stored.


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cycle 8


Entry Busy Instruction State Destination Value Field Data Reorder Bus1 y subi $t3,$t3,1 exec $t3 $t02 y bgtz $t3,loop issue $t13 y mul $t4,$t2 issue $t2 54 y mflo $t4 issue $t3 0 #1 y5 $t4 25 #4 y6 $t57 $t68 n bgtz $t3,loop flush $t79 y mul $t4,$t2 exec $Hi, $Lo $t810 y mflo $t4 issue $t4 $t9

Reservation Station


Add1 mflo #9 #10Add 2 y subi 0 1 #1Add3 mflo #3 #4Add4

Mul1 y mul 25 5 #9Mul2

Br1 bgtz #2 #2

Br2

In cycle8,bgtz in entry 8 is flushed due to t3 = 0. Stations are also flushed. And any executecancelled. No more update! Registers got their final values like t2=5, t3=0 and t4=25.

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