tools for discovery
DESCRIPTION
Tools for Discovery. Digital Pulse Processing for Physics Applications PSI - March 15th 2011 Carlo Tintori. Outline. Description of the hardware of the waveform digitizers Overview on the CAEN Digitizer family Use of the digitizers for physics applications - PowerPoint PPT PresentationTRANSCRIPT
Tools for Discovery
Digital Pulse Processing for Physics Applications
PSI - March 15th 2011
Carlo Tintori
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Outline
• Description of the hardware of the waveform digitizers
• Overview on the CAEN Digitizer family
• Use of the digitizers for physics applications
• Comparison between the traditional analog acquisition chains and the new fully digital approach
• DPP algorithms:• Pulse triggering
• Zero suppression
• Pulse Height Analysis
• Charge Integration
• Gamma-Neutron discrimination
• Time measurement
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• The principle of operation of a waveform digitizer is the same as the digital oscilloscope: when the trigger occurs, a certain number of samples is saved into one memory buffer (acquisition window)
• However, there are important differences:– no dead-time between triggers (Multi Event Memory)– multi-board synchronization for system scalability– high bandwidth data readout links– on-line data processing (FPGA or DSP)
PRE POST TRIGGER
ACQUISITION WINDOW
Sampling Clock
TRIGGER
Time
TIME STAMPS[0]
S[n-1]
S[1]S[2]S[3]
Memory Buffer
Digitizers vs Oscilloscopes
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Highlights
• VME, NIM, PCI Express and Desktop• VME64X, Optical Link (CONET), USB 2.0,
PCI Express Interfaces available• Memory buffer: up to 10MB/ch (max. 1024
events)
• Multi-board synchronization and trigger distribution
• Programmable PLL for clock synthesis• Programmable digital I/Os• Analog output with majority or linear sum• FPGA firmware for Digital Pulse Processing• Software for Windows and Linux
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Digitizers Table
MO
DE
L
For
m F
acto
r
Num
ber
of
chan
nels
Max
. S
ampl
ing
Fre
quen
cy (
MS
/s)
N.
Bit
Inpu
t D
ynam
ic
Ran
ge (
Vpp
)
Sin
gle
End
ed /
D
iffer
entia
l Inp
ut
Ban
dwid
th (
MH
z)
Mem
ory
(Msa
mpl
e/ch
)
DP
P f
irmw
are
VME 8 SE, D
Desktop/NIM 4 SE
PCIe 2 SE
VME 8 SE, D
Desktop/NIM 4 SEPCIe 2 SE
x721 VME 8 500 8 2 SE, D 250 2 no
VME 8/4 SE, D
Desktop/NIM 4/2 SE 2/4
PCIe 2 SE
VME 8/4 SE, D
Desktop/NIM 4/2 SE
VME 2 SE, D
Desktop/NIM 1 SE
VME 64
Desktop/NIM 32
VME 32+2
Desktop/NIM 16+1
1101000/2000
no
12 1 SE no
no500
0.19; 1.5
7.2; 57.6
1.8; 14.4 / 3.6; 28.8
0.128
tbd
30
x742 5000
x740 65 12 2 SE
600
no
nox761 4000
x751
x731 500/1000 8 2
10
125
1
100 14 0,5; 2.25; 10
250/500
x724 40 TF, SG
CI, NGx720 250 12 2
0.5; 4
1.25; 10
ADC
FIXED GAINAMPLIFIER
+
DAC
FPGA(AMC)
SRAMMEMORY
DAUGTHER BOARDS
FPGA(VME)
LOCAL BUS
PLL
CONET
CLK-IN
INT. OSCILL.
MOTHER BOARD
TRG-IN
SYNC-IN
TRG-OUT
GLOBAL TRG
SYNC
SELF TRG
I/Os
CLK-OUT
SAMPLING CLOCK
DAC MONITOR
ANALOGINPUTs
VME/USB
n CHANNELS
Architecture
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Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited
• Traditionally, the acquisition chains for radiation detectors are made out of mainly analog circuits; the A to D conversion is performed at the very end of the chain
• Nowadays, the availability of very fast and high precision flash ADCs permits to design acquisition systems in which the A to D conversion occurs as close as possible to the detector
• The data throughput is extremely high: it is no possible to transfer row data to the computers and make the analysis off-line!
• On-line digital data processing in needed to extract only the information of interest (Zero Suppression & Digital Pulse Processing)
• The aim of the DPP for Physics Applications is to provide FPGA algorithms able to make in digital the same functions of analog modules such as Shaping Amplifiers, Discriminators, Charge ADCs, Peak Sensing ADCs, TDCs, Scalers, Coincidence Units, etc.
Digitizers for Physics Applications
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Traditional chain: example 1charge sensitive preamplifiers
DECAY TIMERISE TIME
TIME Q = ENERGY
PEAK AMPLITUDE = ENERGY
ZERO CROSSING
This delay doesn’t depend on the pulse amplitude
DETECTOR
PREAMPLIFIER
SHAPING AMPLIFIER
TIMING AMPLIFIER
CFD
CFD OUTPUT
DETECTOR
Charge SensitivePreamplifier
SHAPINGAMPLIFIER
ENERGY
POSITION,IDENTIF.
TIMING
COUNTINGSHAPING TIME,GAIN THRESHOLDS
PEAK SENSING ADC
DISCRIMINATOR
TDC
SCALER
LOGICUNIT
Trigger, Coincidence
Fast Out
• Typically used with semiconductor detectors (Si, Ge)
• The preamp. output signal is rather slow (typ. decay time = 50us)
• Very high energy resolution (good S/N ratio)
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TIME Q = ENERGY
ZERO CROSSING
DETECTOR
CFD
GATE
DELAYED SIGNALCHARGE
INTEGRATION
• Typ. used with scintillators + PMTs or SiPMs
• The preamplifier is optional (the gain is already in the PMT)
• Fast signals (typ. 10-100ns)
TransimpedancePreamplifier
(optional)
SPLITTER
DETECTOR
ENERGY
POSITION,IDENTIF.
TIMING
COUNTINGTHRESHOLDS
DISCRIMINATOR
TDC
SCALER
LOGICUNIT
Gate
QDCDelayLine
Traditional chain: example 2trans-impedance (current sensitive)
preamplifier
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• One single board can do the job of several analog modules
• Full information preserved: A/D conversion as early as possible, data reduction as late as possible
• Reduction in size, cabling, power consumption and cost per channel
• High reliability and reproducibility
• Flexibility (different digital algorithms can be designed and loaded at any time into the same hardware)
DETECTORENERGY
SHAPE
TIMING
COUNTINGDPPIN
SAMPLESA/D INTERF
DIGITIZER COMPUTER
VERY HIGH DATA THROUGHPUT
Benefits of the digital approach
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Standard Firmware:• raw waveform mode (event = sequence of samples)• common trigger on all channels simultaneously• trigger time stamp• channels self trigger: digital discriminator with absolute threshold• channel self triggers ORed to make the common trigger • zero suppression (sole data reduction technique)
DPP Firmware• on-line dead-timeless data processing• multi-parametric list mode (event = time stamp, pulse height, charge,
etc…)• combined acquisition mode: list + short waveform for further analysis
off-line• channels can trigger independently• pulse triggering: baseline restore, smooth filters, rise time
discriminator, etc…• pulse time stamp• pulse shape analysis (e.g. gamma neutron discrimination)• individual trigger propagation on channel basis, also from board to
board
Standard vs DPP firmware
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Raw waveform mode vs DPP events
INPUT
TIMINGFILTER
MEAN
ZCROSS
SUM
Trigger
TIME STAMP
CHARGE
BASELINE
S1
S2
S3
S4
TIME STAMP
BASELINE
CHARGE
EVENT DATA
Threshold
Leading Edge
TRAPEZ HEIGHT
SAMPLES
HEIGHT
INPUT
S1
S2
S3
S4
S5
S6
S7
Sn
Threshold
Trigger
Acquisition Window
EVENT DATASTD FW
DPP FW
Typ. Nsample > 1K
Typ. Nsample < 100
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Coincidence and Event correlation
• When running in list mode, the bandwidth requirement is much lower than in raw waveform mode. Example: time stamp + energy = 8 bytes; 8 channels @ 1Mcps = 64 MB/s; fits the CONET bandwidth.
• General Rule: read all events as long as you have enough bandwidth (i.e. make data suppression as late as you can)
• Coincidence and anticoincidence applied off-line using the time stamps
• When hardware coincidence is needed, you can:
• Use internal coincidence between the channels of a board to make a common trigger (STD FW only)
• Use analog sum or majority on the DAC output (only for VME board with STD FW)
• Use on-line coincidence in the x720+DPP-CI (only between couples of channels)
• Use GPIOs on the front panel to propagate trigger inputs/outputs from/to external logic (e.g. V1495)
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Trigger and timing filter (I)
• Pulse triggering is the basis for all DPP and Zero Suppression algorithms
• Fast Shaping filter: digital version of the RC-CRN filter (N=1, 2)
• Immune to baseline fluctuation and low frequency noise (ground loop)
• Pulse identification also with the presence of pile-up
• High frequency noise rejection (RC smoothing filter)
• Can operate as a digital CFD
• Zero crossing for precise timing information
• Off-line interpolation to overcome the sampling period granularity
• Zero crossing of CFD can also be used for rise time discrimination
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Trigger and timing filter (II)
-5000
0
5000
10000
6000 7000 8000 9000 10000 11000
1 B
IN =
1.3
76 K
eV
Time (1 sample = 10ns)
Emulation Mode
CFDInput
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Zero Suppression• Data reduction algorithms can be developed to reduce the
data throughput: – Full event suppression: one event (acquisition window) is discarded if no pulse is detected inside the window– Zero Length Encoding: only the parts exceeding the threshold (plus a certain number of samples before and after) are saved.
• The zero suppression is available also with the standard FW (no DPP)
suppressed suppressed suppressed
ZLE threshold
Look BackWindow
Look AheadWindow
Region ofInterest
SAMPLEST T TSAMPLES SAMPLES
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DPP-TF
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DPP-TF topics
• Digital implementation of the shaping amplifier + peak sensing ADC (Multi-Channel Analyzer)
• Charge sensitive preamplifier directly connected to the digitizer
• Implemented in the 14 bit, 100MSps digitizers (mod. 724)
• Use of trapezoidal filters to shape the long tail exponential pulses
• Pile-up rejection, Baseline restoration, ballistic deficit correction
• Low dead time => high counting rate
• Energy and timing information can be combined
• Best suited for high resolution spectroscopy (HPGe and Si detectors)
• Also suitable for homeland security and biomedical applications
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DPP-TF Block Diagram
DECIMATOR
RC-(CR)N
N = 1,2
COMP
TRAPEZOIDALFILTER
TRG & TIMING FILTER
COMP
ARMED
ZERO
TRIGGER
BASELINEMEAN
a b N
k m M
D
D = 1,2,4,8
Nsbl
Thr
SUB
INPUT
TIME STAMP
ENERGY
ftd Nspk
CLK
PEAKMEAN
COUNTER
b = RiseTime
Nsbl = Baseline Mean
Nspk = Peak meanftd = Flat Top Delay (ballistic deficit)
m = Flat Top
Thr = TRG Threshold
a = Low Pass mean
zero crossing
M = Time Constant (PZ cancellation)K = Shaping Time
TRAPEZOIDTIMINGFILTER
-15000
-10000
-5000
0
5000
10000
8000 10000 12000 14000 16000 18000
1 B
IN =
1.3
76 K
eV
Time (1 sample = 10ns)
Emulation Mode
TrapezoidInput
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Example of trapezoidal filter output
Pile-upTrapezoid Height = Energy
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DPP-TF vs Analog Chain set-ups
N1470High
VoltageN968
ShapingAmplifier
N957Peak
Sensing ADC
DT572414bit @ 100MSpsDigitizer + DPP-TF
Energy
Energy
Time
Ge / SiC.S. PRE
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Dead Time in the DPP-TF • Unlike the analog chain, in the DPP-TF there is no conversion time
• The A/D conversion and the pulse processing is always alive; dead time in the energy filter is only given by the trapezoid overlap (Trise + Tflat)
• Although pile-up causes the loss of energy values, the timestamps is given for almost all pulses: true rate can be calculated
• Double pulse resolution Rise Time (two pulses separated by at least the rise time can be distinguished)
• The rise time discriminator allows double pulses piling up on the rising edge to be detected and counted twice
• Residual multiple pulses that cannot be distinguished (despite the RTD) can be taken into account on a statistical basis
• Histogram (spectrum) calculated off-line: easy implementation of techniques for the ‘dead-time’ correction (loss of energy counts)
• The number and the timing of lost counts is known: they can be dynamically re-distributed on the histogram. This is very important in the cases where the activity is not constant in time.
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Individual inter-channel triggering
• Feature developed for the project Prospectus (compton camera)
• Mainly needed in segmented or clove detectors
• One channel triggers itself and also neighbour channels (also from board to board
• Individual TRG-IN and TRG-OUT lines from each channel to the Front Panel GPIO connector (8 inputs + 8 outputs)
• External trigger unit (V1495) for the coincidence matrix implementation
• Available in the new DPP-TF (x724 series)
• Can be implemented in the x720 and x751 series as well
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Example of System Integration
TRIGGERLOGIC(V1495)
VME
CLOCK DISTRIB.Progr. Phase shift
INDIVIDUAL TRIGGER IN/OUT
TRIGGER / SYNC
TRIGGERSYNC START/STOP
CONET A3818 PCIe
CONET OPTICAL LINKReadout and/or control80MB/s, up to 4x8 boards
ANALOG OUTDISCRIM
Thr
ANALOG OUTPUTLinear Sum,Majority
V1718
VME-USB
SLOW CONTROL
One PC can read up to 32 boards (256 channels!)
CLOCK MASTERBOARD
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Test Results with HPGe detectors• Preliminary tests performed at LNL (Legnaro - Italy) on Nov-2008 and Feb-
2009
• Further tests at Duke University on Jul-2010
• Last test at University of Palermo (Dep. Of Phisycs) on Jan 2011: the detector is an Ortec HP-Ge mod. GEM40P4 cooled with an X-cooler (Peltier). The preamp is an A257P with a time constant of 100s.
• Source = 60Co (count rate = 0.8 KHz)
FWHM @ 1.33 MeV: 1.98 KeV
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Test Results with CdTe at high rate (I)
• Tests executed at University of Palermo on February 2011
• Detector: CdTe from Amptek with embedded FET integrator
• Rise Time = 140 ns, Decay Time = 100 s
• Source = 109Cd, X-ray peaks at 22 and 25 KeV
• Tested at 70, 200 and 800 KHz with different DPP parameters
70 KHz
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Test Results with CdTe at high rate (II)
200 KHz
200 KHz
with Rise Time Discriminator
SUM PEAKS
NO SUM PEAKS
800 KHz
800 KHz
with Baseline Hold-off
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DPP-CI
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DPP-CI topics
• Digital implementation of the QDC + discriminator and gate generator
• Implemented in the Mod. x720 - 12 bit, 250MS/s and Mod x751 - 10 bit, 1GS/s or 2GS/s (*)
• Self-gating integration; no delay line to fit the pulse within the gate
• Baseline restoration (pedestal cancellation)
• Extremely high dynamic range
• Dead-timeless acquisition (no conversion time)
• Energy and timing information can be combined
• Typically used for PMT or SiPM/MPPC readout(*) Implementation in the Mod. x751 will be ready by April 2011
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DPP-CI Block Diagram
INPUT
a = Low Pass mean
b = RiseTimeThr = TRG Threshold
W = Gate width
Nsbl = Baseline mean
TIMING FILTER
GATE
DELAYED INPUT
D = Delay (Pre-Gate) COMP
DELAY
TRG & TIMING FILTER
TRIGGER
BASELINEMEAN
a b
Nsbl
Thr
SUB
INPUT
TIME STAMP
CHARGE
W
CLK COUNTER
ACCUMULATOR(INTEGRATOR)
DMONOSTABLE
GATE
QLSB = TS * VLSB / 50 = 40 fC (Mod 720)
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DPP-CI vs Analog Chain set-up
N1470High
Voltage
DT572012bit @ 250MSpsDigitizer + DPP-CI
Charge
Charge
Time
NaI(Tl)
PMT
Dual TimerN93B
DelayN108A
QDCV792N
CFDN842
TDC V1190 Time
SplitterA315
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DPP-CI: Test Results with NaI+PMT
DPP-CI Analog QDC
Energy (MeV) Res (%) Res (%)
0.481 (137Cs Compton edge)
9.41 1.18 12.80 0.70
0.662 (137Cs Photopeak) 7.01 0.04 8.17 0.04
1.33 (60Co Photopeak) 5.67 0.03 6.66 0.18
1.17 (60Co Photopeak) 5.46 0.02 5.89 0.13
2.51 (60Co Sum peak) 3.82 0.11 4.10 0.24Resolution = FWHM * 100 / Mean
NaI detector and PMT directly connected to the QDC or digitizer
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DPP-CI: Test Results with SiPM kit SP5600
•0.5 ph
•1.5 ph
•2.5 ph
•Th
resho
ld scan
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DPP-CI: Test Results with LaBr
• Project: SLIM.CHECK (detection of illicit radioactive material)
• Test performed at JRC Ispra by INFN PD (acknowledges: G. Visti)
• 4 detectors: LaBr, NaI(Tl), NE213, 3He, all read by a V1720 with DPP-CI
• Source 238U (348 Kg)
LaBr
NaI
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DPP-NG
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DPP-NG topics
• Digital implementation of the E/E analysis (double gate charge integration)
• Implemented in the Mod. x720 - 12 bit, 250MS/s and Mod x751 - 10 bit, 1GS/s or 2GS/s (*)
• PSD = (QLONG - QSHORT)/ QLONG
• Typically used with organic liquid scintillators (e.g. BC501)
• Dead-timeless acquisition (no conversion time)
• Alternative analysis (not implemented yet) based on the Rise Time Discrimination technique: T in the Zero Crossing of two CFDs at 25% and 75%; applied to integrated output (either from C.S. preamp or digital integrator)
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-n Discrimination Block Diagram (I)
SHORT GATE
LONG GATE
DELAY
BASELINE
BLns
TRGthr
SUBINPUT
TIME STAMP
Q-FAST
CLKTIME
COUNTER
GATE1
ACCUMULATOR(INTEGRATOR)
COMPTRIGGER
BLthr GateWidth1
WAVEFORM
PULSE SHAPEDISCRIMINATOR
GATE2
EV
EN
T B
UIL
DE
R
PSDthr
Q-SLOW
PreTrigger
GateWidth2
OUTDATA
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-n Discrimination Block Diagram (II)
T
Algorithms tested off-line
Not yet implemented in FW
DELAY
BASELINE
BLns
TRGthr
SUBINPUT
TIME STAMPCLK
TIME COUNTER
COMP
T1
BLthr
WAVEFORM
PULSE SHAPEDISCRIMINATOR
PreTrigger
CFD DELAY
25% ATTEN
75% ATTEN
SUB
SUB
ZC
ZC
EV
EN
T B
UIL
DE
R
T2
OUTDATA
PSDthr
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-n Discrimination: test results (I)
Detector: BC501A 5x2 inches,
PMT: Hamamatsu R1250
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-n Discrimination: test results (II)
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-n Discrimination: test results (III)
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-n Discrimination: test results (IV)
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-n Discrimination: test results (V)
-50
0
50
100
150
200
250
300
350
400
450
500
-50 0 50 100 150 200 250 300 350 400 450 500
'histogram2d.txt'
-50
0
50
100
150
200
250
300
350
400
450
500
-50 0 50 100 150 200 250 300 350 400 450 500
'histogram2d.txt'
12bit 250MS/s
10bit 1GS/s (off-line)
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-n Discrimination: test results (VI)
E/E (dual gate)
t CFD (25%, 75%)
(off-line)
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Practical example of off-line coincidence
0
5000
10000
15000
20000
25000
0 50 100 150 200 250 300 350 400
ALL
0
500
1000
1500
2000
0 50 100 150 200 250 300 350 400
COINC
• Detectors: 2 BC501A
• Source: Na22
• 740.000 events acquired in list mode (energy+time stamp) from both detectors
• Off-line analysis: search for time-stamp coincidence within 50 ns
• Energy spectrum of all events (up) and after coincidence (down)
• Energy vs Time of Flight 2-D plot (below)
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TIMING
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Conventional TDCs vs Digitizers
• Conventional TDC boards:V1190: 128 channel, 100 ps Multi-Hit TDCV1290: 32 channel, 25 ps Multi-Hit TDCV775: 32 channel, 35 ps Start-Stop TDC
• TDC in a digitizer can't compete in terms of density and cost, but…
• There are cases where the implementation of a TDC in a digitizer is profitable:Time measurement (at medium-low resolution) combined with energy or other parameters
Extremely high timing resolution (better than 10 ps)
Bursts of very close pulses (e.g. Free Electron Lasers)
Signals unsuitable for the conventional Constant Fraction Discriminators
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Algorithms for the Time Measurements
• DPP time stamp LSB equals the sampling period (Resolution = Ts/12);
• Interpolation between samples improves timing resolution
• It is not worth doing on-line interpolation (floating point consumes FPGA resources and has no significant data size reduction)
• DPP can make on-line digital CFD or LED and save just 2 (or more) points for the interpolation to be performed off-line
• Big dependence of the resolution on the rise-time and amplitude of the pulses (V/ T)
S1
S2
S3
S4S4 = ZC time stampResolution = Ts / 12
High Resolution ZC aftermath. Interpolation
Time
INPUT
Timing Filter
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ZC timing errorsTiming resolution affected by three types of noise:– Electronic noise in the analog signal (here ignored)– Quantization error Eq– Interpolation error Ei
There are 2 different cases:
Rise Time > 5*Tslinear interpolation is good: Ei << Eq The resolution is proportional to V/T and to the number of bits of the ADC.
Rise Time < 5*Ts approximation to a straight line is too rough: Ei is the dominant error (Eq is negligible). Such a geometric error varies with the position of the signal respect to the sampling clock giving non gaussian spectra and other non-physical effects.The resolution becomes inversely proportional to the rise time.
Optimum Rise Time = 5*Tsfor any type of digitizer!SN-1
SN
TSAMPL
LSBADC
zero
Eq
Ei
ANALOG SIGNAL
LINEAR INTERPOLATION
TRUE TIME
MEASURED TIME
TIME STAMP
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Sampling Clock phase effect (RT<5Ts) (I)
ERRA
CHA CHB
ERRB
DELAYA-B = N*TS
CHA CHB
ERRA ERRB
DELAYA-B = (N+0.5)*TS
DELAYAB = N * Ts: same clock phase for A and B same interpolation error ERRA ERRB Error cancellation in calculating TIMEAB
TIMEAB = (ZCA + ERRA) – (ZCB + ERRB) = ZCA– ZCB + (ERRA - ERRB )
DELAYAB = (N+0.5) * Ts:rotated clock phase for A and B different interpolation error ERRA ERRB No error cancellation. ERRA and ERRB are symmetric: twin peak distribution
When rise time < 5*Ts, the interpolation error has a big variation with the phase between the rising edge and the sampling clock.
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Sampling Clock phase effect (RT<5Ts) (II)
0
100
200
300
400
500
600
700
800
900
0 200 400 600 800 1000 1200 1400 1600
'histo_Mod724_dt10n.txt'
'histo_Mod724_dt15n.txt'
DELAY = N * Ts
DELAY = (N + 0.5) * Ts
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Sampling Clock phase effect (RT<5Ts) (III)
Vpp = 100mV
Mod720: 12bit 250MSps
Emulation
0.01
0.1
1
10
3 4 5 6 7 8 9
Std
_D
ev[
ns]
Delay[ns]
RiseTime 5ns
RiseTime 10ns
RiseTime 15ns
RiseTime 20ns
RiseTime 30ns
5 ns10 ns15 ns20 ns30 ns
Rise Time
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Preliminary results: Mod724
50 mV
100 mV
200 mV
500 mV
(14 bit, 100 MS/s)
RiseTime (ns)
Std
Dev
(n
s)
5*T
DELAY = N * Ts
DELAY = (N + 0.5) * Ts
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Preliminary results: Mod720
50mV
100mV
200mV
500mV
(12 bit, 250 MS/s)
RiseTime (ns)
Std
Dev
(n
s)
5*T
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Preliminary results: Mod751
50mV
100mV
200mV
500mV
(10 bit, 1 GS/s)
NOTE: the region with Rise Time < 5*Ts (5 ns) is missing in this plot
RiseTime (ns)
Std
Dev
(n
s)
5*T
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Mod724 vs Mod720 vs Mod751
10 bit, 1 GS/s
12 bit, 250 MS/s
14 bit, 100 MS/s
RiseTime (ns)
Std
Dev
(n
s)
Amplitude = 100 mV
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Mod751 @ 2 GS/sS
tdD
ev (
ns)
Amplitude (mV)
5 ps !
RT = 1 ns - worst case
RT = 1 ns - best case
RT = 5 ns
The cubic interpolation can reduce the gap between best and worst case as well as increase the resolution for small signals!
DIGITAL SIGNAL (NIM or ECL)
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Work in progress
• We are currently making tests with the x742 series (5 GS/s, 12 bit)
• The use of the x742 is the only way to get a high density, low cost digitizer giving high energy and timing resolution in one single board
• There is no DPP on-line for the moment; however, the need of DPP for this board is less important because of the dead-time
• Timing calibration (applied off-line) seems effective
• Linear interpolation between two points gave a timing resolution of about 30 ps
• We are investigating other types of signal interpolations such as cubic (4 points) or best fit curves with a signal template
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Software for Digitizers
WaveDump
VME Digitizers
VM
E
CONET2 (Optical Link)
Desktop Digitizers
A2818 A3818
V2718
V1718
NIM Digitizers
PCIe Digitizers
DPPRunner Other Application
CAENDigitizer Library
CAENComm Library
A2818 driver A3818 driver V1718 driver USB driver P72XX driver
PC
I
PC
Ie
PC
Ie
USB 2.0 USB 2.0 USB 2.0
SBC
3rd part driver