topic 3 processor function
TRANSCRIPT
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Processor Function
Topic 3
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After studying this chapter
you should be able to - describe the structure of typical assembly
language instructions using the terms op-code andoperand
describe and give examples of assembly languageinstructions of the following types data transfer arithmetic logical
shift and rotate branch
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Revision Question 1Machine code isA. a common programming language which
can be used on any machine
B. the low level language specific to aparticular microprocessorC. the number which identifies a particular
type of computer
D. any high level language which can becompiled for use by a microprocessor
B
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Revision Question 2The processor register which holds theaddress of the next instruction to befetched is the
A. memory address register (MAR)B. instruction register (IR)C. program counter (PC)
D. memory data register (MDR)
C
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Revision Question 3The correct sequence of steps in the fetch-executecycle isA. fetch instruction increment PC decode
instruction execute instructionB. increment PC fetch instruction decode
instruction execute instructionC. fetch instruction decode instruction
increment PC execute instruction
D. fetch instruction
decode instruction
execute instruction increment PC
A
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Revision Question 4Data fetched from memory arrives inA. the memory address register (MAR)B. the instruction register (IR)
C. the program counter (PC)D. the memory data register (MDR)
D
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Revision Question 5In an 8-bit microprocessor,A. the data and address buses must both be
8 bits wide
B. the data bus is 8 bits wide, but theaddress bus may be more than 8 bitswide
C. the address bus must be 8 bits wide, but
the data bus can be any widthD. a single 8 bit wide system bus is used totransfer all data and addresses
B
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Machine Code Processors only understand
instructions in machine code
These are difficult to read andunderstande.g 10101001 00000001
10000101 0111000010100101 01110000
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10101001 0000000110001101 000000111110100010001101 00000011
1110100001101001 0000000110001101 000000111110100100100000 11101110
1111111101100000
LDA #1STA 1000
LDA 1000
ADC #1STA 1001
JSR OSWRCH
RTS
Mnemonic a shortcode replaces themachine codeinstruction
Assembly LanguageMachine Code
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Assembly Language
Instructions
Op-code Operand
Data to be
operatedupon
What the
instruction isto do
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Assembly Language
InstructionsOp-code Operand
LDA #1STA 1DFF
LDA 3C15
Meaning
Load the accumulator with thevalue 1
Store the contents of the accin memory location 1DFF
Load the acc. with thecontents of memory location3C15
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Assembly Language
InstructionsOp-code Operand
LDA #110101001 00000001
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10101001 0000000110001101 000000111110100010001101 00000011
1110100001101001 0000000110001101 000000111110100100100000 11101110
1111111101100000
LDA #1STA 1000
LDA 1000
ADC #1STA 1001
JSR OSWRCH
RTS
Assembly LanguageMachine Code
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Instruction Formats Not all instructions are the same
length e.g. 6502 processor
8-bit Op-code
8-bit operand8-bit Op-code
8-bit Op-code 16-bit operand
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Instruction Formats IBM mainframe instruction set
8-bit Op-code
8-bit Op-code
8-bit Op-code 12-bit operand4-bit operand 4-bit operand
4-bit operand 4-bit operand
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Instruction Formats X86 mainframe instruction set
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Assembly Language
Instructions
Op-code Operand
Data or
address ofdata to beoperatedupon
What the
instruction isto do
Regardless of processor, all instructions the same format -
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Instruction types Data transfer instructions
Arithmetic instructions
Logical instructions Shift and rotate instructions
Branch
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Data transfer Used to move data from one place to
another
Between registers From memory to processor/register
From processor to memory
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Arithmetic Used to carry out simple arithmetic
e.g. +-/x
Add contents of 2 registers Adding 1 to contents of register
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Logical Used to make logical comparisons
Checking whether contents of two
registers are equal to each other
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Shift and rotate Used to manipulate the individual bits
within a register
Shift left 1 bit
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Branch Branch instructions break the normal
sequential flow of execution by
changing the program counter if aspecified condition is met.
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6502 processorSimple processorused in BBC,Apple II and
Atari
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6502 Microprocessor
System
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6502 Microprocessor
System introduced in about 1975 among the first microprocessors to be used in
early home computers. included the usual Arithmetic/Logic Unit with
some internal registers and a Control Unit allon the same chip.
It had an external crystal-controlled clock togenerate timing signals
http://courses.scholar.hw.ac.uk/vle/scholar/session.controller?action=viewGlossary&contentGUID=cdb2a320-14b9-2fbf-89e5-52bd10d79056http://courses.scholar.hw.ac.uk/vle/scholar/session.controller?action=viewGlossary&contentGUID=06acf790-3bdb-2c83-1446-1867f4ae8fd1http://courses.scholar.hw.ac.uk/vle/scholar/session.controller?action=viewGlossary&contentGUID=06acf790-3bdb-2c83-1446-1867f4ae8fd1http://courses.scholar.hw.ac.uk/vle/scholar/session.controller?action=viewGlossary&contentGUID=cdb2a320-14b9-2fbf-89e5-52bd10d79056 -
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6502 Microprocessor
System ROM was used to hold a bootstrapprogram to permit initial operation of thesystem
RAM was used to hold programs and data The interface with the external devices
was via a Programmable Input/Output unit(PIO), which communicated with the
external devices using 16-bit wide I/Obuses.
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6502 Microprocessor
System The external bus was a combination of an
8-bit-wide data bus, a 16-bit-wide
address bus and some control lines thatcarried synchronisation signalsthroughout the system.
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6502 Microprocessor
System Hence only 8 bits of data could be
moved around the system, but 16-bitaddresses could be used to addressmemory.
Memory locations with addresses inthe range 0 to 65535 (216-1) could
be directly addressed Memory was made up of individually
addressable 8-bit words (bytes).
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6502 Microprocessor
System - registers
8 bits used for storing
data16 bits
used for storing 16bit addresses
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6502 Registers8 bit registers A
X Y
SR
IR MDR
16-bit registers
MAR
PC SP
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6502 registers - A A is known as the Accumulator the
main general purpose register in
which data is held during mostarithmetical and logical operations
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6502 registers
X,Y XandYare index registers. They are
designed to hold loop counters or as
gp registers
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6502 registers - SR SR is the status register. It is really
a set of 8 1-bit registers. Each bit
operates independently, and is usedto flag to record the status of theprocessor after each instruction
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6502 registers - SR
N- the negative flag set o 1 if the result of the last operation is zero
V the overflow flag set to 1 if the last result operation is invalid
B
the break bit
set to 1 when a break instruction is executedD the decimal flag when set to 1, the processor will operate usingbinary coded decimal arithmetic
I the interrupt disable flag when set the processor will ignore anyinterrupt signals
Z the zero flag set to 1 when the last result was zero
C the carry flag set to 1 if the result of an operation is a numberthat cannot be stored in a single 8-bit register
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6502 registers - IR IR is the instruction register.
It holds the instruction being
decoded or executed
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6502 registers - MDR MDR is the Memory Data register.
It holds data which has just arrived
along the data bus or is just about tobe sent along the data bus
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6502 registers - MAR MAR is the Memory Address
register.
It holds an address about to be sentout along the address bus
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6502 registers - PC PC is the Program Counter.
It holds the address of the next
instruction to be fetched, decodedand executed
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6502 registers - SP SP is the Stack Pointer.
Temporary data storage. The SP
holds the address of the next freelocation in the stack
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Exercise Copy and complete the table Page 55
Q.7
Complete questions 8-11
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LDA #55 Load the accumulator with the value
55
See scholar animation
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Addressing Modes Refers to the operand
There are many types e.g.
Immediate Direct
Implied
Others such as relative, indirect,indexed
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Immediate Addressing The operand is the actual data to be used
Example LDA #55
Other examples
CMP #27
compare the contents of A with thenumber 27
LDX #A4 load the X register with the valueA4
LDY #00
load the Y register with the number
00
8-bit operand8-bit Op-code
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Direct Addressing The operand is the address to be
used Example LDA 3C15
Other examples JMP 2015 jump to instruction in
location 2015 ADC 2099 add the data in location
2099 to the accumulator
16-bit operand (address)8-bit Op-code
l d dd
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Implied Addressing No operand is required
Example TAX transfer thecontents of A to X
Other examples TYA transfer the contents of the Y-
register to the accumulator
8-bit Op-code
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Other addressing modesAs well as immediate, absolute and implied addressing, the6502 processor has many other addressing modes. Theseinclude:
relative addressing - for example BEQ 09, which means "ifthe zero flag was set by the last operation, branch to the
instruction 9 locations forward in memory" indexed addressing - for example LDA 3C15,Y which means
"load the accumulator with the data to be found at thelocation 3C15+Y, where Y is the value stored in the Yregister
indirect addressing - for example LDA (3C15), which means
"load the accumulator with the data you find at the addresswhich is to be fond at location 3C15"
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Instruction types Data transfer instructions Arithmetic instructions Logical instructions
Shift and rotate instructions Branch instructions Various others Now have a look at the animations in
Scholar
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Program 1 adding two
numbersCLC clear the carry flag, just in caseLDA 2004 fetch the number from location 2004
ADC 2005 add on the number from location 2005STA 2006 store the result in location 2006
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Program 2 Multiplying
by 3CLC clear the carry flag, just in caseLDA 2004 fetch the number from location 2004
ADC 2004 add the number to itselfADC 2004 add the number on again
STA 2005 store the result in location 2005
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Program 3 Multiplying
two numbersLDA 2004 fetch the number from location 2004LDX 2005 load the X register with the number
from location 2005DEX reduce X by 1 (see note 1 below)CLC clear the carry flag just in caseADC 2004 add the number from location 2004 to
the current value in the accumulatorDEX reduce the X register by 1BNE -6 if X is not zero, branch back 6 locations
see note 2 below)
STA 2006 store the result in location 2006
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Exercise Scholar Page 91 Q 12 19
Past Papers 2008 Q14 a-b 2006 Q17 b+c 2010 Q15 2011 Q11