topic 8 sequential circuits

Topic 8 - 1 Nov-27-09 E4.20 Digital IC Design

Topic 8

Sequential Circuits1

Peter Cheung Department of Electrical & Electronic Engineering

Imperial College London

URL: www.ee.ic.ac.uk/pcheung/ E-mail: [email protected]

Rabaey Chapter 7

1 Based on slides from Prentice-Hall


Mux-Based Latches

Negative latch (transparent when CLK= 0)

Positive latch (transparent when CLK= 1)

CLK

1

0 D

Q 0

CLK

1 D

Q


Mux-Based Latch


Mux-Based Latch

NMOS only Non-overlapping clocks


Master-Slave (Edge-Triggered) Register

Two opposite latches trigger on edge Also called master-slave latch pair


Master-Slave Register

Multiplexer-based latch pair


Reduced Clock Load Master-Slave Register


Overpowering the Feedback Loop ─ Cross-Coupled Pairs

NOR-based set-reset


Cross-Coupled NAND

Cross-coupled NANDs Added clock

This is not used in datapaths any more, but is a basic building block for memory cell


Sizing Issues

Output voltage dependence on transistor width

Transient response


Storage Mechanisms

Dynamic (charge-based) Static


Making a Dynamic Latch Pseudo-Static


Master-Slave Static Flip-flop

  Overlapping Clocks Can Cause •  Race Conditions •  Undefined Signals


Two-phase dynamic flip-flop


Use 2-phase non-overlapping clocks


Latch + Logic


Other Latches/Registers: C2MOS

“Keepers” can be added to make circuit pseudo-static


Insensitive to Clock-Overlap

M 1

D Q M 4

M 2

0 0

V DD

X

M 5

M 8

M 6

V DD

(a) (0-0) overlap

M 3

M 1

D Q

M 2

1

V DD

X M 7 1

M 5

M 6

V DD

(b) (1-1) overlap


Pipelining

Reference Pipelined


Other Latches/Registers: TSPC

Negative latch (transparent when CLK= 0)

Positive latch (transparent when CLK= 1)


Including Logic in TSPC

AND latch Example: logic inside the latch


TSPC Register


μ π latches: Poor man’s TSPC Latch

  What is wrong with this TSPC Latch?

  Second attempt:


μ π latches Final solution


Pulse-Triggered Latches An Alternative Approach

Master-Slave Latches

D Clk

Q D Clk

Q

Clk

Data D Clk

Q Clk Data

Pulse-Triggered Latch

L1 L2 L

Ways to design an edge-triggered sequential cell:


Pulsed Latches


Pulsed Latches

Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :


Hybrid Latch-FF Timing


Latch-Based Pipeline


Non-Bistable Sequential Circuits─ Schmitt Trigger

• VTC with hysteresis

• Restores signal slopes


Noise Suppression using Schmitt Trigger


CMOS Schmitt Trigger


Schmitt Trigger Simulated VTC


CMOS Schmitt Trigger (2)


Multivibrator Circuits


Transition-Triggered Monostable


Monostable Trigger (RC-based)


Relaxation Oscillator


Astable Multivibrators (Oscillators)


Voltage Controller Oscillator (VCO)


Differential Delay Element and VCO

in 2

two stage VCO

v 1 v 2

v 3 v 4

V ctrl

V o 2 V o 1 in 1

delay cell

simulated waveforms of 2-stage VCO

0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0

2 0.5 1.5

V 1 V 2 V 3 V 4

time (ns) 2.5 3.5

topic 8 sequential circuits

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