topstar c46 - rev d - cce win t33b (1)
TRANSCRIPT
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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Title
TOPSTAR TECHNOLOGY
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C46
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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Title
TOPSTAR TECHNOLOGY
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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Title
TOPSTAR TECHNOLOGY
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C46
Manager Sign by:
Hardware drawing by: Hardware check by: EMI Check by:
Topstar Confidential
Power check by:
Topstar Digital technologies Co.,LTD
03. PWR Block & DescriptionVersion: VerA
60. Power On Sequence & Reset Map61. ACPI Mode Switch Timings
02. System block & Index
Power drawing by:
Project name: C46
60. Power on & off Sequence
05. Schematic Modify and History
Board name: MotherBoard Schematic
04. Notes & AnnotationsInitial Date: MAY.9, 2008
59. CLOCK Distribution
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A
Sys block
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Sys block
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C46
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Sys block
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C46
RJ45PCIE 1X
+V5S
SATA ODD
Card Reader+V3.3S,+V3.3ALITE 1337
SLG8SP585
BTM-203/CCOM
PCIE mini Card
TCM
RJ45RTL8102E+V3.3S,+V3.3AL
USB1.1/2.0
Camera1.3M/2.0MMODULE
LED/TouchPAD/Button/
1071 BGAIbex_peak
AZALIAPCIE 1X
+V3.3A,+V3.3S,+V1.5S,+V1.05S,+V1.8S,+V5A,+V5S
+V3.3AL
+VCC_CORE,+VccGFX +V1.5S, +V1.8S, +V1.1S_VTT
2.5" HDD
NEW CARD(Type II)
989rPGA
+V0.75S,+V1.5,+V3.3S
LPC
KB Matrix
+V3.3S+V3.3AL,+V3.3S,+V5AL
ENE 3926KB Controller/EC
Topstar Confidential
+V0.75S,+V1.5,+V3.3S
CK505MClocking
S-ATA
C46 SYSTEM BLOCK Ver:A
SD/MMC/MS CARD
DDR3 SODIMM0800/1066
+V3.3S
USB1.1/2.0
DMI*4 100MHz
BLUE TOOTH(V1.2)
Arrandule/clarsfield
DDR3 SODIMM1800/1066
ShenZhen Topstar Industry Co.,LTD
DAUGHTER BOARD
PCIE mini Half-Card
+V5S,+V3.3S
R
L
ALC662MiC
+V5S,+V3.3S
AZALIA
Q-key/LIDDAUGHTER BOARD
DDR3 800/1066
DDR3 800/1066
FDI
VGA
+V5STMDS
HDMI
PEGX16 /eDP+VGA_CORE,+V1.05GPU+V1.8GDDR,+V3.3GPU+V1.5GPU
Memoryinterface
Nvidia NB11
+V1.5GDDR64M*16Bit*4 GDDRIII
LVDS
R/G/B+V0.75S,+V1.5,+V3.3S
PCI-Express X16
LVDS
Only for PM
8MbitBIOS+V3.3AL
SPI
USB PORT1+V5AL
+VDC
+V3.3S
BacklightConnector
TFT LVDS switch
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B B
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
C46 A
PWR Block
TOPSTAR TECHNOLOG
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
C46 A
PWR Block
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Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
C46 A
PWR Block
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VR_TT#
PSI#
V_3
VIN
V_5
Platform Logic
Vcc_core
CLKCHIP
VID[6...0]
CPU_PWRGD
PSI#
PCH CPU-M
C
L
K
_
E
N
A
B
L
E
#
I
M
V
P
6
_
P
W
R
G
D
PROCHOT#
DPRSLPVR
IMVP-6.5
V
R
_
O
N
IMON
C46 POWER BLOCK Ver:A
VCC_SENCEVSS_SENCE
MOSFET
System Power +V_S
+VGFX
5A
5A/5A
+V1.05GPU
Adapter
+VCC_CORE
2.5A
ChargeISL6251
12A/2.5A
TPS51218
Always_On PowerTPS51125
+V5S+V3.3S
+V3.3AL+V5AL
51A
ISL62881
PowerSwitch
VCC_COREISL62882
14A
+VDC
DDR PowerTPS51218+APL5331
+V1.1S_VTT
Battery
18A+V1.5+V0.75S
65/90W
KIA1117
:
+V1.5GPU+V1.5S
MOSFET
3A+VGA_CORE
ISL62872
10A
MOSFET
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C C
B B
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Notes
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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Notes
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Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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Notes
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0.8--1.03V for GPU NB8M core voltage
+V1.5S 1.5S for PCIE Device
Primary DC system power supply(9V-19V)
+V0.75S
3.3V main power rail
+V5AL
0.75V DDR3 Termination voltage
1.1V for CPU
5V main power rail
+V3.3S
+V5S
+V1.05S
5V for USB Device
Voltage Rails
3.3V always on power rail
Core voltage for processor
1.05V for PCH core
+V1.5
+VDC
1.5V power rail for DDR3
+V3.3AL
+VCC_CORE
+V1.1S_VTT
+V1.8S 1.8V for display votage
+VGA_CORE
+V3.3GPU 3.3V for external GPU
+V1.05GPU 1.05V for external GPU
+V1.8GPU 1.8V for external GPU
+V1.5GPU 1.5V for external GPU
IN2
VCC
Bottom
Trace Impedence:50ohm +/-15%(Default)
IN3
TOP
PCB Layers
Board stack up description
IN1
GND
GND
reserved
camera
USB port1
Bluetooth
Reserved
CARD Reader
minicard2
8
9
Express Card
minicard1
Reserved
0
1
3
4
5
6
7
2
USB Table
USB Port# Function Description
10
11
USB port2
USB port3
PCHPCHPCHPCH
1101 001x
A41010 000xSO-DIMM01010 010x
Address
SMB_PCH
BusHexI2C SMB Address
Device
PCHA0D2
Master
Clock Generator
SO-DIMM1
VariableVariableNEW CARDVariableVariablePCIE Mini CARD
Smart Battery 0001 011x 16 I2C ENE3926
SMB_PCHSMB_PCHSMB_PCHSMB_PCH
ENE3926Variable Variable SMB1_PCHPCH
S3(STM)
Power States/AC mode
ON
ON ON
SLP_S5#
ON
SLP_S4#
ON
LOW
+V*S
ON
LOW
LOW OFF
Signal
S5(SoftOff)
OFF
OFFLOW
HIGH
SLP_S3#
OFF
OFF
S0(Full On)
+V*
LOWS4(STD)
HIGH
+V*AL
OFF
LOW
HIGH
Clock
OFF
HIGH
HIGH ON OFF
HIGH
ON
Wake up Events
LID switch from EC
Power switch from EC
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C C
B B
A A
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history
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
C46 A
history
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Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
C46 A
history
TOPSTAR TECHNOLOG
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VerA to VerB Changelist1.VBIOS ROM srrap 15K2. 27M clock0ohm33ohm3.PCH 100MCLK-REQ#4. PCH GPIO16 follow CHECK LIST5.Switch ICfootprint6. RGBESD 7. HDMIEC detect 8. SYS_RST#0hm9.SIM //connecterfootprint10.GPU_RST#11.HD connecter TP12.BT connect ECN
VerB to VerC Changelist1. N11M2.USBP/N3.ECIMVP_ON1K0ohm
VerC to VerD Changelist1.N11MHDMID2+/-D1+/-2. 3.3AL/5ALcolay 220uf poscap
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3
3
2
2
1
1
D D
C C
B B
A A
CLK_BUF_REF14
XTAL_IN
+VDDIO_CLK
BCLK_FS
BCLK#BCLK
DOT96DOT96#
+V3.3S_CK_VDD
+VDDIO_CLK
+V3.3S_CK_VDD
CLK_PWRGD
CPU_STOP#
BCLK_FS
CPU_STOP#
CLK_PWRGD
XTAL_OUT+V3.3S
+V3.3S
+V3.3S
+V3.3S
+V3.3S+V3.3AL
CLK_BUF_REF14 {23}
CLK_BUF_DOT96_N {23}
CLK_BUF_BCLK_N {23}CLK_BUF_BCLK_P {23}
CLK_BUF_SATA_N {23}
CLK_BUF_DOT96_P {23}
CLK_BUF_SATA_P {23}
CLK_BUF_EXP_P {23}CLK_BUF_EXP_N {23}
+V3.3S {8,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57}
27M_nonSSC {20}27M_SSC {20}
CK505_CLK_EN#{55}
+V3.3AL {23,24,26,27,29,32,33,36,38,39,40,41,42,43,44,45,46,47,48,49,50,52,53,56}
SMB_DATA_S {15,16,23,40,41}SMB_CLK_S {15,16,23,40,41}
Page Name
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
M21 B
CK505M
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
M21 B
CK505M
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Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
M21 B
CK505M
TOPSTAR TECHNOLOG
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No more than 500 mil
SMBUS ADD:1101 001X
Layout Note:Cap Close to CK505 PWR pin
Integrated resistors on differentail clk
Frequence SelectHigh:100MhzLow:133Mhz(Default)
update Y1 footprint
FB9 100ohm@100MHz,3A
FB0805
FB9 100ohm@100MHz,3A
FB0805
1 2
R317 1KR0402
R317 1KR0402
C227
0.1UF/25V,Y5V
C0402
C227
0.1UF/25V,Y5V
C0402
C249
0.1UF/25V,Y5VC0402ns
C249
0.1UF/25V,Y5VC0402ns
R27710KR0402ns
R27710KR0402ns
C217
0.1UF/25V,Y5V
C0402
C217
0.1UF/25V,Y5V
C0402
Y1
14.318MHzXS4_5032_0D8
Y1
14.318MHzXS4_5032_0D8
43
2 1
C244
0.1UF/25V,Y5VC0402
C244
0.1UF/25V,Y5VC0402
FB10 100ohm@100MHz,3AFB0805
FB10 100ohm@100MHz,3AFB0805
12
R306 0nsR306 0ns
R240 0 R0402R240 0 R0402
VCC
GND
U15SN74AHC1G08DBVSOT23_5
VCC
GND
U15SN74AHC1G08DBVSOT23_5
1
24
5
3
R30710KR0402
R30710KR0402
R276 0 R0402R276 0 R0402
C231 27pF/50V,NPOC0402
C231 27pF/50V,NPOC0402
R260 0 R0402R260 0 R0402
C232 10PF/50V,NPOns
C0402C232 10PF/50V,NPOns
C0402
R242 0 R0402R242 0 R0402
C222
0.1UF/25V,Y5V
C0402
C222
0.1UF/25V,Y5V
C0402
C2360.1UF/10V,X7RC2360.1UF/10V,X7R
C216
10UF/6.3V,X5RC0805
C216
10UF/6.3V,X5RC0805
R243 0 R0402R243 0 R0402
R262 0 R0402R262 0 R0402
R31410KR0402
nsR31410KR0402
ns
C220
0.1UF/25V,Y5VC0402
C220
0.1UF/25V,Y5VC0402
R275 0 R0402R275 0 R0402
U12
CK505QFN32
U12
CK505QFN32
VSS_DOT2
VSS_SATA9
VDD_SRC17
VSS_SRC12
VDD_CPU_IO18
SRC0/SATA 10XTAL_OUT27
XTAL_IN28 DOT96# 4
VDD_275
27M_NSS 6
DOT96 3
27M_SS 7
VDD_DOT1SMB_CLK 32
SMB_DATA 31
VSS_278
SRC0#/SATA 11
VDD_SRC_IO15
REF/FS 30
CPU0# 22CPU0 23
CPU1# 19CPU1 20
CPU_STOP# 16
SRC1 13SRC1# 14
CK_PWRGD/PWRDWN# 25VSS_CPU21
VDD_CPU24
VSS_REF26
VDD_REF29
GND1G1GND2G2GND3G3GND4G4
GND5G5
R24710KR0402
R24710KR0402
R241 0 R0402R241 0 R0402
R261 0 R0402R261 0 R0402
PQ322N7002SOT23
PQ322N7002SOT23
3
1
2
C229
0.1UF/25V,Y5VC0402
C229
0.1UF/25V,Y5VC0402
C226
10UF/6.3V,X5R
C0805
C226
10UF/6.3V,X5R
C0805
C230
10UF/6.3V,X5R
C0805
C230
10UF/6.3V,X5R
C0805
C223
0.1UF/25V,Y5VC0402
C223
0.1UF/25V,Y5VC0402
R278 33 R0402R278 33 R0402
C233 27pF/50V,NPOC0402
C233 27pF/50V,NPOC0402
R264 0 R0402R264 0 R0402
C234
0.1UF/25V,Y5V
C0402
C234
0.1UF/25V,Y5V
C0402
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55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_TXN0
DMI_RXP2
DMI_TXN3
DMI_TXP3
DMI_RXP0
DMI_TXP2DMI_TXP1
DMI_RXN3
DMI_TXN1
DMI_RXN2
DMI_TXN2
DMI_TXP0
DMI_RXN1
DMI_RXP1
DMI_RXP3
DMI_RXN0
FDI_TXN0FDI_TXN1FDI_TXN2FDI_TXN3FDI_TXN4FDI_TXN5FDI_TXN6FDI_TXN7
FDI_TXP0FDI_TXP1FDI_TXP2FDI_TXP3FDI_TXP4FDI_TXP5FDI_TXP6FDI_TXP7
PEG_IRCOMP_R
EXP_RBIAS
PEG_TXN1
PEG_TXN4PEG_TXN5
PEG_TXN3
PEG_TXN7PEG_TXN8
PEG_TXN6
PEG_TXN10PEG_TXN11
PEG_TXN9
PEG_TXN13PEG_TXN14
PEG_TXN12
PEG_TXN15
PEG_TXP1PEG_TXP2
PEG_TXP4PEG_TXP5
PEG_TXP3
PEG_TXP7PEG_TXP8
PEG_TXP6
PEG_TXP10PEG_TXP11
PEG_TXP9
PEG_TXP13PEG_TXP14
PEG_TXP12
PEG_TXP15
PEG_TXP0
PEG_TXN0
PEG_RXN1PEG_RXN2
PEG_RXN4PEG_RXN5
PEG_RXN3
PEG_RXN7PEG_RXN8
PEG_RXN6
PEG_RXN10PEG_RXN11
PEG_RXN9
PEG_RXN13PEG_RXN14
PEG_RXN12
PEG_RXN15
PEG_RXN0
PEG_RXP1PEG_RXP2
PEG_RXP4PEG_RXP5
PEG_RXP3
PEG_RXP7PEG_RXP8
PEG_RXP6
PEG_RXP10PEG_RXP11
PEG_RXP9
PEG_RXP13PEG_RXP14
PEG_RXP12
PEG_RXP15
PEG_RXP0
PEG_NV_RXN2
PEG_NV_RXN0PEG_NV_RXN1
PEG_NV_RXN3PEG_NV_RXN4PEG_NV_RXN5PEG_NV_RXN6PEG_NV_RXN7PEG_NV_RXN8PEG_NV_RXN9PEG_NV_RXN10PEG_NV_RXN11PEG_NV_RXN12PEG_NV_RXN13PEG_NV_RXN14PEG_NV_RXN15
PEG_NV_RXP0PEG_NV_RXP1PEG_NV_RXP2PEG_NV_RXP3PEG_NV_RXP4PEG_NV_RXP5PEG_NV_RXP6PEG_NV_RXP7PEG_NV_RXP8PEG_NV_RXP9PEG_NV_RXP10PEG_NV_RXP11PEG_NV_RXP12PEG_NV_RXP13PEG_NV_RXP14PEG_NV_RXP15
PEG_TXN2
DMI_TXP0{24}
DMI_RXN2{24}
DMI_TXN2{24}
DMI_RXP2{24}
DMI_TXP1{24}
DMI_TXN0{24}
DMI_TXN3{24}
DMI_TXP3{24}
DMI_TXN1{24}
DMI_TXP2{24}
DMI_RXN3{24}
DMI_RXN1{24}
DMI_RXP1{24}
DMI_RXN0{24}
DMI_RXP0{24}
DMI_RXP3{24}
FDI_TXN[7:0]{24}
FDI_TXP[7:0]{24}
FDI_FSYNC0{24}FDI_FSYNC1{24}
FDI_INT{24}
FDI_LSYNC0{24}FDI_LSYNC1{24}
PEG_RXN[15:0] {17}
PEG_RXP[15:0] {17}
PEG_NV_RXN[15:0] {17}
PEG_NV_RXP[15:0] {17}
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
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C46
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
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C46
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Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
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C46
GC1690.1UF/10V,X7RGC1690.1UF/10V,X7R
GC1230.1UF/10V,X7R GC1230.1UF/10V,X7R
GC130 0.1UF/10V,X7RGC130 0.1UF/10V,X7R
GC1070.1UF/10V,X7R GC1070.1UF/10V,X7R
GC1550.1UF/10V,X7R GC1550.1UF/10V,X7R
GC1320.1UF/10V,X7RGC1320.1UF/10V,X7R
GC1640.1UF/10V,X7RGC1640.1UF/10V,X7R
GC1180.1UF/10V,X7RGC1180.1UF/10V,X7R
GC121 0.1UF/10V,X7RGC121 0.1UF/10V,X7R
GC117 0.1UF/10V,X7RGC117 0.1UF/10V,X7R
GC184 0.1UF/10V,X7RGC184 0.1UF/10V,X7R
GC181 0.1UF/10V,X7RGC181 0.1UF/10V,X7RGC126 0.1UF/10V,X7RGC126 0.1UF/10V,X7R
GC177 0.1UF/10V,X7RGC177 0.1UF/10V,X7R
P
C
I
E
X
P
R
E
S
S
-
-
G
R
A
P
H
I
C
S
DMIIntel(R) FDI
U2A
IC,AUB_CFD_rPGA,R1P0
P
C
I
E
X
P
R
E
S
S
-
-
G
R
A
P
H
I
C
S
DMIIntel(R) FDI
U2A
IC,AUB_CFD_rPGA,R1P0
DMI_RX#[0]A24DMI_RX#[1]C23DMI_RX#[2]B22DMI_RX#[3]A21
DMI_RX[0]B24DMI_RX[1]D23DMI_RX[2]B23DMI_RX[3]A22
DMI_TX#[0]D24DMI_TX#[1]G24DMI_TX#[2]F23DMI_TX#[3]H23
DMI_TX[0]D25DMI_TX[1]F24
DMI_TX[3]G23DMI_TX[2]E23
FDI_TX#[0]E22FDI_TX#[1]D21FDI_TX#[2]D19FDI_TX#[3]D18FDI_TX#[4]G21FDI_TX#[5]E19FDI_TX#[6]F21FDI_TX#[7]G18
FDI_TX[0]D22FDI_TX[1]C21FDI_TX[2]D20FDI_TX[3]C18FDI_TX[4]G22FDI_TX[5]E20FDI_TX[6]F20FDI_TX[7]G19
FDI_FSYNC[0]F17FDI_FSYNC[1]E17
FDI_INTC17
FDI_LSYNC[0]F18FDI_LSYNC[1]D17
PEG_ICOMPI B26PEG_ICOMPO A26
PEG_RBIAS A25PEG_RCOMPO B27
PEG_RX#[0] K35PEG_RX#[1] J34PEG_RX#[2] J33PEG_RX#[3] G35PEG_RX#[4] G32PEG_RX#[5] F34PEG_RX#[6] F31PEG_RX#[7] D35PEG_RX#[8] E33PEG_RX#[9] C33
PEG_RX#[10] D32PEG_RX#[11] B32PEG_RX#[12] C31PEG_RX#[13] B28PEG_RX#[14] B30PEG_RX#[15] A31
PEG_RX[0] J35PEG_RX[1] H34PEG_RX[2] H33PEG_RX[3] F35PEG_RX[4] G33PEG_RX[5] E34PEG_RX[6] F32PEG_RX[7] D34PEG_RX[8] F33PEG_RX[9] B33
PEG_RX[10] D31PEG_RX[11] A32PEG_RX[12] C30PEG_RX[13] A28PEG_RX[14] B29PEG_RX[15] A30
PEG_TX#[0] L33PEG_TX#[1] M35PEG_TX#[2] M33PEG_TX#[3] M30PEG_TX#[4] L31PEG_TX#[5] K32PEG_TX#[6] M29PEG_TX#[7] J31PEG_TX#[8] K29PEG_TX#[9] H30
PEG_TX#[10] H29PEG_TX#[11] F29PEG_TX#[12] E28PEG_TX#[13] D29PEG_TX#[14] D27PEG_TX#[15] C26
PEG_TX[0] L34PEG_TX[1] M34PEG_TX[2] M32PEG_TX[3] L30PEG_TX[4] M31PEG_TX[5] K31PEG_TX[6] M28PEG_TX[7] H31PEG_TX[8] K28PEG_TX[9] G30
PEG_TX[10] G29PEG_TX[11] F28PEG_TX[12] E27PEG_TX[13] D28PEG_TX[14] C27PEG_TX[15] C25
GC172 0.1UF/10V,X7RGC172 0.1UF/10V,X7R
GC1030.1UF/10V,X7RGC1030.1UF/10V,X7R
R560 49.9,1%R0402
R560 49.9,1%R0402
GC1110.1UF/10V,X7RGC1110.1UF/10V,X7R
GC960.1UF/10V,X7R GC960.1UF/10V,X7R
GC1270.1UF/10V,X7R GC1270.1UF/10V,X7RGC1830.1UF/10V,X7R GC1830.1UF/10V,X7R
GC158 0.1UF/10V,X7RGC158 0.1UF/10V,X7R
GC1060.1UF/10V,X7RGC1060.1UF/10V,X7R
GC1780.1UF/10V,X7RGC1780.1UF/10V,X7R
GC1540.1UF/10V,X7RGC1540.1UF/10V,X7R
GC167 0.1UF/10V,X7RGC167 0.1UF/10V,X7R
R552 750 OHMR0402
R552 750 OHMR0402
GC1730.1UF/10V,X7RGC1730.1UF/10V,X7R
GC1850.1UF/10V,X7R GC1850.1UF/10V,X7R
GC101 0.1UF/10V,X7RGC101 0.1UF/10V,X7RGC1620.1UF/10V,X7RGC1620.1UF/10V,X7R
GC94 0.1UF/10V,X7RGC94 0.1UF/10V,X7R
GC1120.1UF/10V,X7R GC1120.1UF/10V,X7R
GC1590.1UF/10V,X7RGC1590.1UF/10V,X7R
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_COMP1
H_COMP0
H_COMP3
H_COMP2
BCLK_CPU_P_R
BCLK_ITP_P
BCLK_CPU_N_R
CLK_EXP_P_RCLK_EXP_N_R
BCLK_ITP_N
CLK_DP_P_RCLK_DP_N_R
SM_RCOMP_0
H_COMP3
SM_RCOMP_1SM_RCOMP_2
H_COMP2
H_COMP1
H_COMP0
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
PM_EXT_TS#0
PM_EXT_TS#1
PM_EXT_TS#0PM_EXT_TS#1
H_PECI_R
H_CATERR#
VR_PROCHOT#
VR_PROCHOT#
H_CPURST#_R
H_PM_SYNC_R
VCCPWRGOOD_1_R
PM_DRAM_PWRGD
PLT_RST#_R
VCCPWRGD_0_R
H_PWRGD_XDP_R
PM_DRAM_PWRGD
TDO
TCK
TDI
TMSTRST#
TDI_MTDO_M
XDP_REQ
TDO
TMS
TCK
TDI
XDP_REQ
TDO_M
TDI_M
CPU_VTT_PWG
+V1.1S_VTT
+V1.1S_VTT
+V3.3S
+V1.1S_VTT+V1.1S_VTT
+V1.1S_VTT
+V1.1S_VTT
+V1.1S_VTT
+V1.1S_VTT
+V1.1S_VTT
+V1.1S_VTT
+V3.3S
+V3.3S
+V1.1S_VTT
+V1.5
+V1.1S_VTT
BCLK_CPU_P {27}BCLK_CPU_N {27}
CLK_EXP_P {23}CLK_EXP_N {23}
DDR3_DRAMRST# {15,16}
DIM_EXTTS#0 {16}
DIM_EXTTS#1 {15}
H_PECI{27}
EC_PROCHOT# {43}
THERMTRIP#{27,38}
H_PM_SYNC{24}
VCCPWRGD_0{27}
PM_DRAM_PWRGD{24}
BUF_PLT_RST#{17,26,38,39,40,41,43,44}
+V1.1S_VTT {10,11,27,28,29,38,50,51,55}
+V3.3S {6,15,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58}
VR_PROCHOT# {55}
+V1.5 {11,15,16,49,56,57}
CPU_VTT_PWG{43}
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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Processor CompensationSignals
Layout Note:Place close to CPU
DDR3 Compensation Signals
Voltage Level?
Voltage Level?
T22 nsT22 ns
T23 nsT23 ns
R54320,1%r0402
R54320,1%r0402
T18 nsT18 ns
R11810K
R0402ns
R11810K
R0402ns
R522 0 R0402R522 0 R0402
R1051.21K,1%R1051.21K,1%
R439100,1%R0402
R439100,1%R0402
R6351KR0402
R6351KR0402
T21 nsT21 ns
R213
0 R0402
R213
0 R0402
Q30MMBT3904-FSOT23
Q30MMBT3904-FSOT23
1
2
3
R1811.5K,1%
R0402
R1811.5K,1%
R0402
T24 nsT24 ns
T25 nsT25 ns
R13310K
R0402
R13310K
R0402
R21449.9,1%
R0402 nsR21449.9,1%
R0402 ns
R539 0 R0402
ns
R539 0 R0402
ns
R549 68 R0402ns
R549 68 R0402ns
T26 nsT26 ns
750 OHMR344
R0402750 OHMR344
R0402
R54449.9,1%R0402
R54449.9,1%R0402
R2170R0402
ns
R2170R0402
ns
R218
49.9,1%R0402
nsR218
49.9,1%R0402
ns
T19 nsT19 ns
R531 0 R0402
ns
R531 0 R0402
ns
Q8
MMBT3904-FSOT23ns
Q8
MMBT3904-FSOT23ns
1
23
R524 0 R0402R524 0 R0402
R1291K,1%R0402ns
R1291K,1%R0402ns
T58 nsT58 ns
R19849.9,1%R0402
R19849.9,1%R0402
Q31MMBT3904-FSOT23
Q31MMBT3904-FSOT23
1
2
3
T59 nsT59 ns
R12310K
R0402
R12310K
R0402
R1391K,1%R0402ns
R1391K,1%R0402ns
R6341KR0402
R6341KR0402
R13010K
R0402ns
R13010K
R0402ns
750 OHMR185
R0402750 OHMR185
R0402
R6361KR0402
R6361KR0402
Q9
MMBT3904-FSOT23ns
Q9
MMBT3904-FSOT23ns
1
23
C
L
O
C
K
S
MISCTHERMAL
PWR MANAGEMENT
D
D
R
3
M
I
S
C
J
T
A
G
&
B
P
M
U2B
IC,AUB_CFD_rPGA,R1P0
C
L
O
C
K
S
MISCTHERMAL
PWR MANAGEMENT
D
D
R
3
M
I
S
C
J
T
A
G
&
B
P
M
U2B
IC,AUB_CFD_rPGA,R1P0
SM_RCOMP[1] AM1SM_RCOMP[2] AN1
SM_DRAMRST# F6
SM_RCOMP[0] AL1
BCLK# B16BCLK A16
BCLK_ITP# AT30BCLK_ITP AR30
PEG_CLK# D16PEG_CLK E16
DPLL_REF_SSCLK# A17DPLL_REF_SSCLK A18
CATERR#AK14
COMP3AT23
PECIAT15
PROCHOT#AN26
THERMTRIP#AK15
RESET_OBS#AP26
VCCPWRGOOD_1AN14
VCCPWRGOOD_0AN27
SM_DRAMPWROKAK13
VTTPWRGOODAM15
RSTIN#AL14
PM_EXT_TS#[0] AN15PM_EXT_TS#[1] AP15
PRDY# AT28PREQ# AP27
TCK AN28TMS AP28
TRST# AT27
TDI AT29TDO AR27
TDI_M AR29TDO_M AP29
DBR# AN25
BPM#[0] AJ22BPM#[1] AK22BPM#[2] AK24BPM#[3] AJ24BPM#[4] AJ25BPM#[5] AH22BPM#[6] AK23BPM#[7] AH23
COMP2AT24
PM_SYNCAL15
TAPPWRGOODAM26
COMP1G16
COMP0AT26
SKTOCC#AH24
R2121K,1%R0402
nsR2121K,1%R0402
ns
R56849.9,1%
R0402 nsR56849.9,1%
R0402 ns
R528 0 R0402R528 0 R0402
R182 0 R0402R182 0 R0402
R21649.9,1%R0402 ns
R21649.9,1%R0402 ns
R433 0 R0402R433 0 R0402
R54220,1%r0402
R54220,1%r0402
R437130,1%R0402
R437130,1%R0402
T20 nsT20 ns
R180 0 R0402R180 0 R0402
R548 68 R0402ns
R548 68 R0402ns
R520 0 R0402R520 0 R0402
R1013.3KR1013.3K
R566
49.9,1%R0402
nsR566
49.9,1%R0402
ns
R55949.9,1%R0402
R55949.9,1%R0402
R43824.9,1%R0402
R43824.9,1%R0402
10KR632
R040210KR632
R0402
R18749.9,1%R0402
R18749.9,1%R0402
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MA_A_A14
MA_DATA14
MA_DATA4
MA_DATA56
MA_DATA40
MA_DATA11
MA_DATA17
MA_DATA1
MA_DATA42
MA_DATA27
MA_DATA44
MA_DATA2
MA_DATA26
MA_DATA19
MA_DATA15
MA_DATA22
MA_DATA12
MA_DATA32
MA_DATA59MA_DATA58
MA_DATA41
MA_DATA45
MA_DATA63
MA_DATA50
MA_DATA33
MA_DATA51
MA_DATA5
MA_DATA60
MA_DATA20
MA_DATA49
MA_DATA38
MA_DATA3
MA_DATA47
MA_DATA61
MA_DATA28
MA_DATA18
MA_DATA43
MA_DATA48
MA_DATA37
MA_DATA13
MA_DATA29
MA_DATA10
MA_DATA62
MA_DATA53
MA_DATA55
MA_DATA23
MA_DATA52
MA_DATA54
MA_DATA35
MA_DATA31
MA_DATA46
MA_DATA30
MA_DATA16
MA_DATA39
MA_DATA8
MA_DATA34
MA_DATA25
MA_DATA57
MA_DATA36
MA_DATA6
MA_DATA0
MA_DATA21
MA_DATA9
MA_DATA24
MA_DATA7
MA_DQS#5
MA_DQS#7MA_DQS#6
MA_DQS#0MA_DQS#1MA_DQS#2MA_DQS#3MA_DQS#4
MA_DQS1MA_DQS0
MA_DQS2MA_DQS3MA_DQS4MA_DQS5MA_DQS6MA_DQS7
MA_DM1MA_DM0
MA_DM2MA_DM3
MA_DM5MA_DM4
MA_DM6MA_DM7
MA_A_A1MA_A_A2MA_A_A3MA_A_A4MA_A_A5MA_A_A6MA_A_A7MA_A_A8
MA_A_A0
MA_A_A9MA_A_A10MA_A_A11MA_A_A12MA_A_A13
MB_DATA58
MB_DATA55
MB_DATA61
MB_DATA54
MB_DATA59
MB_DATA62
MB_DATA60
MB_DATA57
MB_DATA63
MB_DATA52MB_DATA53
MB_DATA56
MB_DATA51
MB_DATA35
MB_DATA30
MB_DATA7
MB_DATA33
MB_DATA22
MB_DATA6
MB_DATA29
MB_DATA31
MB_DATA17
MB_DATA36
MB_DATA18
MB_DATA13
MB_DATA9
MB_DATA48
MB_DATA34
MB_DATA43
MB_DATA19
MB_DATA11
MB_DATA8
MB_DATA28
MB_DATA45MB_DATA46
MB_DATA16
MB_DATA0MB_DATA1
MB_DATA23
MB_DATA15
MB_DATA2
MB_DATA25
MB_DATA42
MB_DATA27
MB_DATA47
MB_DATA21MB_DATA20
MB_DATA5
MB_DATA44
MB_DATA37
MB_DATA50
MB_DATA10
MB_DATA49
MB_DATA14
MB_DATA40
MB_DATA38
MB_DATA32
MB_DATA24
MB_DATA41
MB_DATA3
MB_DATA12
MB_DATA26
MB_DATA39
MB_DATA4
MB_DM1
MB_DM4
MB_DM0
MB_DM7
MB_DM3
MB_DM6MB_DM5
MB_DM2
MB_DQS#1MB_DQS#0
MB_DQS#3
MB_DQS#7
MB_DQS#4MB_DQS#5
MB_DQS#2
MB_DQS#6
MB_DQS5
MB_DQS7MB_DQS6
MB_DQS3
MB_DQS1
MB_DQS4
MB_DQS0
MB_DQS2
MB_B_A9
MB_B_A11
MB_B_A4MB_B_A5
MB_B_A7
MB_B_A3
MB_B_A8
MB_B_A1
MB_B_A10
MB_B_A6
MB_B_A12
MB_B_A2
MB_B_A13
MB_B_A0
MA_A_A15 MB_B_A14MB_B_A15
MB_DATA[63:0]{15}
MA_A_WE#{16}
MA_A_BS0{16}MA_A_BS1{16}MA_A_BS2{16}
M_ODT2 {15}M_ODT3 {15}
M_CLK_DDR2 {15}M_CLK_DDR#2 {15}
M_CLK_DDR#1 {16}
M_CKE2 {15}
M_CS#2 {15}M_CS#3 {15}
M_CLK_DDR0 {16}
M_CLK_DDR1 {16}
M_CLK_DDR#0 {16}
M_CKE1 {16}
M_CKE0 {16}
M_ODT1 {16}M_ODT0 {16}
M_CS#0 {16}M_CS#1 {16}
M_CLK_DDR#3 {15}M_CLK_DDR3 {15}
M_CKE3 {15}
MB_B_WE#{15}
MB_B_CAS#{15}
MB_B_BS0{15}MB_B_BS1{15}
MB_B_RAS#{15}
MB_B_BS2{15}
MA_DQS#[7:0] {16}
MA_DQS[7:0] {16}
MB_DQS#[7:0] {15}
MB_DQS[7:0] {15}
MB_DM[7:0] {15}
MA_A_A[15:0] {16}MB_B_A[15:0] {15}
MA_DATA[63:0]{16}
MA_DM[7:0] {16}
MA_A_CAS#{16}MA_A_RAS#{16}
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Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
-
B
U2D
IC,AUB_CFD_rPGA,R1P0S_Bot
D
D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
-
B
U2D
IC,AUB_CFD_rPGA,R1P0S_Bot
SB_BS[0]AB1SB_BS[1]W5SB_BS[2]R7
SB_CAS#AC5SB_RAS#Y7SB_WE#AC6
SB_CK[0] W8
SB_CK[1] V7
SB_CK#[0] W9
SB_CK#[1] V6
SB_CKE[0] M3
SB_CKE[1] M2
SB_CS#[0] AB8SB_CS#[1] AD6
SB_ODT[0] AC7SB_ODT[1] AD1
SB_DM[0] D4SB_DM[1] E1SB_DM[2] H3SB_DM[3] K1SB_DM[4] AH1SB_DM[5] AL2SB_DM[6] AR4SB_DM[7] AT8
SB_DQS[4] AG2
SB_DQS#[4] AH2
SB_DQS[5] AL5
SB_DQS#[5] AL4
SB_DQS[6] AP5
SB_DQS#[6] AR5
SB_DQS[7] AR7
SB_DQS#[7] AR8
SB_DQS[0] C5
SB_DQS#[0] D5
SB_DQS[1] E3
SB_DQS#[1] F4
SB_DQS[2] H4
SB_DQS#[2] J4
SB_DQS[3] M5
SB_DQS#[3] L4
SB_MA[0] U5SB_MA[1] V2SB_MA[2] T5SB_MA[3] V3SB_MA[4] R1SB_MA[5] T8SB_MA[6] R2SB_MA[7] R6SB_MA[8] R4SB_MA[9] R5
SB_MA[10] AB5SB_MA[11] P3SB_MA[12] R3SB_MA[13] AF7SB_MA[14] P5SB_MA[15] N1
SB_DQ[0]B5SB_DQ[1]A5SB_DQ[2]C3SB_DQ[3]B3SB_DQ[4]E4SB_DQ[5]A6SB_DQ[6]A4SB_DQ[7]C4SB_DQ[8]D1SB_DQ[9]D2SB_DQ[10]F2SB_DQ[11]F1SB_DQ[12]C2SB_DQ[13]F5SB_DQ[14]F3SB_DQ[15]G4SB_DQ[16]H6SB_DQ[17]G2SB_DQ[18]J6SB_DQ[19]J3SB_DQ[20]G1SB_DQ[21]G5SB_DQ[22]J2SB_DQ[23]J1SB_DQ[24]J5SB_DQ[25]K2SB_DQ[26]L3SB_DQ[27]M1SB_DQ[28]K5SB_DQ[29]K4SB_DQ[30]M4SB_DQ[31]N5SB_DQ[32]AF3SB_DQ[33]AG1SB_DQ[34]AJ3SB_DQ[35]AK1SB_DQ[36]AG4SB_DQ[37]AG3SB_DQ[38]AJ4SB_DQ[39]AH4SB_DQ[40]AK3SB_DQ[41]AK4SB_DQ[42]AM6SB_DQ[43]AN2SB_DQ[44]AK5SB_DQ[45]AK2SB_DQ[46]AM4SB_DQ[47]AM3SB_DQ[48]AP3SB_DQ[49]AN5SB_DQ[50]AT4SB_DQ[51]AN6SB_DQ[52]AN4SB_DQ[53]AN3SB_DQ[54]AT5SB_DQ[55]AT6SB_DQ[56]AN7SB_DQ[57]AP6SB_DQ[58]AP8SB_DQ[59]AT9SB_DQ[60]AT7SB_DQ[61]AP9SB_DQ[62]AR10SB_DQ[63]AT10
D
D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
A
U2C
IC,AUB_CFD_rPGA,R1P0S_Bot
D
D
R
S
Y
S
T
E
M
M
E
M
O
R
Y
A
U2C
IC,AUB_CFD_rPGA,R1P0S_Bot
SA_BS[0]AC3SA_BS[1]AB2SA_BS[2]U7
SA_CAS#AE1SA_RAS#AB3SA_WE#AE9
SA_CK[0] AA6
SA_CK[1] Y6
SA_CK#[0] AA7
SA_CK#[1] Y5
SA_CKE[0] P7
SA_CKE[1] P6
SA_CS#[0] AE2SA_CS#[1] AE8
SA_ODT[0] AD8SA_ODT[1] AF9
SA_DM[0] B9SA_DM[1] D7SA_DM[2] H7SA_DM[3] M7SA_DM[4] AG6SA_DM[5] AM7SA_DM[6] AN10SA_DM[7] AN13
SA_DQS[0] C8
SA_DQS#[0] C9
SA_DQS[1] F9
SA_DQS#[1] F8
SA_DQS[2] H9
SA_DQS#[2] J9
SA_DQS[3] M9
SA_DQS#[3] N9
SA_DQS[4] AH8
SA_DQS#[4] AH7
SA_DQS[5] AK10
SA_DQS#[5] AK9
SA_DQS[6] AN11
SA_DQS#[6] AP11
SA_DQS[7] AR13
SA_DQS#[7] AT13
SA_MA[0] Y3SA_MA[1] W1SA_MA[2] AA8SA_MA[3] AA3SA_MA[4] V1SA_MA[5] AA9SA_MA[6] V8SA_MA[7] T1SA_MA[8] Y9SA_MA[9] U6
SA_MA[10] AD4SA_MA[11] T2SA_MA[12] U3SA_MA[13] AG8SA_MA[14] T3SA_MA[15] V9
SA_DQ[0]A10SA_DQ[1]C10SA_DQ[2]C7SA_DQ[3]A7SA_DQ[4]B10SA_DQ[5]D10SA_DQ[6]E10SA_DQ[7]A8SA_DQ[8]D8SA_DQ[9]F10SA_DQ[10]E6SA_DQ[11]F7SA_DQ[12]E9SA_DQ[13]B7SA_DQ[14]E7SA_DQ[15]C6SA_DQ[16]H10SA_DQ[17]G8SA_DQ[18]K7SA_DQ[19]J8SA_DQ[20]G7SA_DQ[21]G10SA_DQ[22]J7SA_DQ[23]J10SA_DQ[24]L7SA_DQ[25]M6SA_DQ[26]M8SA_DQ[27]L9SA_DQ[28]L6SA_DQ[29]K8SA_DQ[30]N8SA_DQ[31]P9SA_DQ[32]AH5SA_DQ[33]AF5SA_DQ[34]AK6SA_DQ[35]AK7SA_DQ[36]AF6SA_DQ[37]AG5SA_DQ[38]AJ7SA_DQ[39]AJ6SA_DQ[40]AJ10SA_DQ[41]AJ9SA_DQ[42]AL10SA_DQ[43]AK12SA_DQ[44]AK8SA_DQ[45]AL7SA_DQ[46]AK11SA_DQ[47]AL8SA_DQ[48]AN8SA_DQ[49]AM10SA_DQ[50]AR11SA_DQ[51]AL11SA_DQ[52]AM9SA_DQ[53]AN9SA_DQ[54]AT11SA_DQ[55]AP12SA_DQ[56]AM12SA_DQ[57]AN12SA_DQ[58]AM13SA_DQ[59]AT14SA_DQ[60]AT12SA_DQ[61]AL13SA_DQ[62]AR14SA_DQ[63]AP14
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VTT_SELECT_R
Vcore_IMON_R
VCCSENSE_RVSSSENSE_R
TP_VSS_SENSE_VTTTP_VTT_SENSE
PM_PSI# PM_DPRSLPVR
+VCC_CORE +V1.1S_VTT
+VCC_CORE
+V1.1S_VTT
+VCC_CORE
+V1.1S_VTT +V1.1S_VTT
H_VID0 {55}H_VID1 {55}H_VID2 {55}
H_VID4 {55}H_VID3 {55}
H_VID5 {55}H_VID6 {55}
Vcore_IMON {55}
VCCSENSE {55}VSSSENSE {55}
+VCC_CORE {55}
+V1.1S_VTT {8,11,27,28,29,38,50,51,55}
PM_PSI# {55}
PM_DPRSLPVR {55}
VTT_SELECT {50}
Page Name
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
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10 59Friday, November 27, 2009
bent
C46
Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
C
10 59Friday, November 27, 2009
bent
C46
Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
C
10 59Friday, November 27, 2009
bent
C46
Clarksfield 1.1vArrandale 1.05v
C1470.22uF/10V,X7RC1470.22uF/10V,X7R
C36310uF/6.3V,X5RC36310uF/6.3V,X5R
R2211KR0402
R2211KR0402
C38310uF/6.3V,X5RC38310uF/6.3V,X5R
C37910uF/6.3V,X5RC37910uF/6.3V,X5R
C38710uF/6.3V,X5RC38710uF/6.3V,X5R
C38810uF/6.3V,X5RC38810uF/6.3V,X5R
C18910uF/6.3V,X5RC18910uF/6.3V,X5R
C14510uF/6.3V,X5RC14510uF/6.3V,X5R
R2201KR0402
nsR2201KR0402
ns
R590100,1%R0402
R590100,1%R0402
R5761KR0402
R5761KR0402
R5810R5810
C18610uF/6.3V,X5RC18610uF/6.3V,X5R
C36510uF/6.3V,X5RC36510uF/6.3V,X5R
C36110uF/6.3V,X5RC36110uF/6.3V,X5R
C38010uF/6.3V,X5RC38010uF/6.3V,X5R
C1960.22uF/10V,X7RC1960.22uF/10V,X7R
C17210uF/6.3V,X5RC17210uF/6.3V,X5R
C2100.01uF/25V,X7RC2100.01uF/25V,X7R
C37310uF/6.3V,X5RC37310uF/6.3V,X5R
C17010uF/6.3V,X5RC17010uF/6.3V,X5R
R589100,1%R0402
R589100,1%R0402
C14610uF/6.3V,X5RC14610uF/6.3V,X5R
C1970.22uF/10V,X7RC1970.22uF/10V,X7R
R1930R1930
C17510uF/6.3V,X5RC17510uF/6.3V,X5R
R5820R5820
C38610uF/6.3V,X5RC38610uF/6.3V,X5R
C38410uF/6.3V,X5RC38410uF/6.3V,X5R
C37710uF/6.3V,X5RC37710uF/6.3V,X5R
C37510uF/6.3V,X5RC37510uF/6.3V,X5R
C1991uF/10V,X7RC1991uF/10V,X7R
C17610uF/6.3V,X5RC17610uF/6.3V,X5R
C18810uF/6.3V,X5RC18810uF/6.3V,X5R
C2120.01uF/25V,X7RC2120.01uF/25V,X7R
C21110uF/6.3V,X5RC21110uF/6.3V,X5R
C36210uF/6.3V,X5RC36210uF/6.3V,X5R
C20910uF/6.3V,X5RC20910uF/6.3V,X5R
C19110uF/6.3V,X5RC19110uF/6.3V,X5R
C37410uF/6.3V,X5RC37410uF/6.3V,X5R
C17110uF/6.3V,X5RC17110uF/6.3V,X5R
C16910uF/6.3V,X5RC16910uF/6.3V,X5R
C37610uF/6.3V,X5RC37610uF/6.3V,X5R
R5751KR0402
nsR5751KR0402
ns
C17410uF/6.3V,X5RC17410uF/6.3V,X5R
C18710uF/6.3V,X5RC18710uF/6.3V,X5R
R5800R5800
C36410uF/6.3V,X5RC36410uF/6.3V,X5R
C19010uF/6.3V,X5RC19010uF/6.3V,X5R
P
O
W
E
R
CPU CORE SUPPLY
1
.
1
V
R
A
I
L
P
O
W
E
R
S
E
N
S
E
L
I
N
E
S
C
P
U
V
I
D
S
U2F
IC,AUB_CFD_rPGA,R1P0
P
O
W
E
R
CPU CORE SUPPLY
1
.
1
V
R
A
I
L
P
O
W
E
R
S
E
N
S
E
L
I
N
E
S
C
P
U
V
I
D
S
U2F
IC,AUB_CFD_rPGA,R1P0
ISENSE AN35
VTT_SENSE B15
PSI# AN33
VID[0] AK35VID[1] AK33VID[2] AK34VID[3] AL35VID[4] AL33VID[5] AM33VID[6] AM35
PROC_DPRSLPVR AM34
VTT_SELECT G15
VCC_SENSE AJ34
VSS_SENSE_VTT A15
VCC1AG35VCC2AG34VCC3AG33VCC4AG32VCC5AG31VCC6AG30VCC7AG29VCC8AG28VCC9AG27VCC10AG26VCC11AF35VCC12AF34VCC13AF33VCC14AF32VCC15AF31VCC16AF30VCC17AF29VCC18AF28VCC19AF27VCC20AF26VCC21AD35VCC22AD34VCC23AD33VCC24AD32VCC25AD31VCC26AD30VCC27AD29VCC28AD28VCC29AD27VCC30AD26VCC31AC35VCC32AC34VCC33AC33VCC34AC32VCC35AC31VCC36AC30VCC37AC29VCC38AC28VCC39AC27VCC40AC26VCC41AA35VCC42AA34VCC43AA33VCC44AA32VCC45AA31VCC46AA30VCC47AA29VCC48AA28VCC49AA27VCC50AA26VCC51Y35VCC52Y34VCC53Y33VCC54Y32VCC55Y31VCC56Y30VCC57Y29VCC58Y28VCC59Y27VCC60Y26VCC61V35VCC62V34VCC63V33VCC64V32VCC65V31VCC66V30VCC67V29VCC68V28VCC69V27VCC70V26VCC71U35VCC72U34VCC73U33VCC74U32VCC75U31VCC76U30VCC77U29VCC78U28VCC79U27VCC80U26VCC81R35VCC82R34VCC83R33VCC84R32VCC85R31VCC86R30VCC87R29VCC88R28VCC89R27VCC90R26VCC91P35VCC92P34VCC93P33VCC94P32VCC95P31VCC96P30VCC97P29VCC98P28VCC99P27VCC100P26
VTT0_33 AF10VTT0_34 AE10VTT0_35 AC10VTT0_36 AB10VTT0_37 Y10VTT0_38 W10VTT0_39 U10VTT0_40 T10VTT0_41 J12VTT0_42 J11
VTT0_1 AH14VTT0_2 AH12VTT0_3 AH11VTT0_4 AH10VTT0_5 J14VTT0_6 J13VTT0_7 H14VTT0_8 H12VTT0_9 G14
VTT0_10 G13VTT0_11 G12VTT0_12 G11VTT0_13 F14VTT0_14 F13VTT0_15 F12VTT0_16 F11VTT0_17 E14VTT0_18 E12VTT0_19 D14VTT0_20 D13VTT0_21 D12VTT0_22 D11VTT0_23 C14VTT0_24 C13VTT0_25 C12VTT0_26 C11VTT0_27 B14VTT0_28 B12VTT0_29 A14VTT0_30 A13VTT0_31 A12VTT0_32 A11
VSS_SENSE AJ35
VTT0_43 J16VTT0_44 J15
C3680.01uF/25V,X7RC3680.01uF/25V,X7R
C38210uF/6.3V,X5RC38210uF/6.3V,X5R
C37810uF/6.3V,X5RC37810uF/6.3V,X5R
T15 ICTPns T15 ICTPns
T14 ICTPns T14ICTP
ns
C38110uF/6.3V,X5RC38110uF/6.3V,X5R
C17310uF/6.3V,X5RC17310uF/6.3V,X5R
C1981uF/10V,X7RC1981uF/10V,X7R
C19210uF/6.3V,X5RC19210uF/6.3V,X5R
C38510uF/6.3V,X5RC38510uF/6.3V,X5R
C36010uF/6.3V,X5RC36010uF/6.3V,X5R
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCPLL
VCCPLL
+V1.1S_VTT
+V1.1S_VTT
+V1.5
+V1.1S_VTT
+V1.1S_VTT
+V1.8S
+VGFX
VGFXVCCSEN {51}VGFXVSSSEN {51}
GFXVR_EN {51}
VGFX_IMON {51}
+VGFX {51}
+V1.1S_VTT {8,10,27,28,29,38,50,51,55}
+V1.5 {8,15,16,49,56,57}
+V1.8S {26,28,29,31,49,56,57}
GFXVR_VID_0 {51}GFXVR_VID_1 {51}GFXVR_VID_2 {51}GFXVR_VID_3 {51}GFXVR_VID_4 {51}GFXVR_VID_5 {51}GFXVR_VID_6 {51}
GFXVR_DPRSLPVR {51}
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
C
11 59Friday, November 27, 2009
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C46
Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
C
11 59Friday, November 27, 2009
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C46
Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
C
11 59Friday, November 27, 2009
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C46
C1600.22uF/10V,X7RC1600.22uF/10V,X7R
FB8300ohm@100MHz,1.5A
FB0805FB8300ohm@100MHz,1.5A
FB08051 2
C3710.01uF/25V,X7RC3710.01uF/25V,X7R
P
O
W
E
R
G
R
A
P
H
I
C
S
V
I
D
s
GRAPHICS
D
D
R
3
-
1
.
5
V
R
A
I
L
S
FDIPEG & DMI
S
E
N
S
E
L
I
N
E
S
1
.
1
V
1
.
8
V
U2G
IC,AUB_CFD_rPGA,R1P0
P
O
W
E
R
G
R
A
P
H
I
C
S
V
I
D
s
GRAPHICS
D
D
R
3
-
1
.
5
V
R
A
I
L
S
FDIPEG & DMI
S
E
N
S
E
L
I
N
E
S
1
.
1
V
1
.
8
V
U2G
IC,AUB_CFD_rPGA,R1P0
GFX_VID[0] AM22GFX_VID[1] AP22GFX_VID[2] AN22GFX_VID[3] AP23GFX_VID[4] AM23GFX_VID[5] AP24GFX_VID[6] AN24
GFX_VR_EN AR25GFX_DPRSLPVR AT25
GFX_IMON AM24
VAXG_SENSE AR22VSSAXG_SENSE AT22
VAXG1AT21VAXG2AT19VAXG3AT18VAXG4AT16VAXG5AR21VAXG6AR19VAXG7AR18VAXG8AR16VAXG9AP21VAXG10AP19VAXG11AP18VAXG12AP16VAXG13AN21VAXG14AN19VAXG15AN18VAXG16AN16VAXG17AM21VAXG18AM19VAXG19AM18VAXG20AM16VAXG21AL21VAXG22AL19VAXG23AL18VAXG24AL16VAXG25AK21VAXG26AK19VAXG27AK18VAXG28AK16VAXG29AJ21VAXG30AJ19VAXG31AJ18VAXG32AJ16VAXG33AH21VAXG34AH19VAXG35AH18VAXG36AH16
VTT1_45J24VTT1_46J23VTT1_47H25
VTT1_48K26VTT1_49J27VTT1_50J26VTT1_51J25VTT1_52H27VTT1_53G28VTT1_54G27VTT1_55G26VTT1_56F26VTT1_57E26VTT1_58E25
VDDQ1 AJ1VDDQ2 AF1VDDQ3 AE7VDDQ4 AE4VDDQ5 AC1VDDQ6 AB7VDDQ7 AB4VDDQ8 Y1VDDQ9 W7
VDDQ10 W4VDDQ11 U1VDDQ12 T7VDDQ13 T4VDDQ14 P1VDDQ15 N7VDDQ16 N4VDDQ17 L1VDDQ18 H1
VTT0_59 P10VTT0_60 N10VTT0_61 L10VTT0_62 K10
VCCPLL1 L26VCCPLL2 L27VCCPLL3 M26
VTT1_63 J22VTT1_64 J20VTT1_65 J18VTT1_66 H21VTT1_67 H20VTT1_68 H19
C15410uF/6.3V,X5RC15410uF/6.3V,X5R
C10610uF/6.3V,X5RC10610uF/6.3V,X5R
C14810uF/6.3V,X5RC14810uF/6.3V,X5R
C1091uF/10V,X7RC1091uF/10V,X7R
C1071uF/10V,X7RC1071uF/10V,X7R
R5454.7KR0402
R5454.7KR0402
C14910uF/6.3V,X5RC14910uF/6.3V,X5R
C1951uF/10V,X7RC1951uF/10V,X7R
C18510uF/6.3V,X5RC18510uF/6.3V,X5R
C18410uF/6.3V,X5RC18410uF/6.3V,X5R
C11010uF/6.3V,X5RC11010uF/6.3V,X5R
C35910uF/6.3V,X5RC35910uF/6.3V,X5R
C19310uF/6.3V,X5RC19310uF/6.3V,X5R
C16110uF/6.3V,X5RC16110uF/6.3V,X5R
C15310uF/6.3V,X5RC15310uF/6.3V,X5R
C37210uF/6.3V,X5RC37210uF/6.3V,X5R
C35810uF/6.3V,X5RC35810uF/6.3V,X5R
C2001uF/10V,X7RC2001uF/10V,X7R
C15210uF/6.3V,X5RC15210uF/6.3V,X5R
C16210uF/6.3V,X5RC16210uF/6.3V,X5R
C2011uF/10V,X7RC2011uF/10V,X7R
C15110uF/6.3V,X5RC15110uF/6.3V,X5R
C18310uF/6.3V,X5RC18310uF/6.3V,X5R C111
1uF/10V,X7RC1111uF/10V,X7R
C18110uF/6.3V,X5RC18110uF/6.3V,X5R
C15010uF/6.3V,X5RC15010uF/6.3V,X5R
C1081uF/10V,X7RC1081uF/10V,X7R
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
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C46
Page Name
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
B
12 59Friday, November 27, 2009
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C46
Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
TOPSTAR TECHNOLOGY
B
12 59Friday, November 27, 2009
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C46
VSS
U2H
IC,AUB_CFD_rPGA,R1P0S_Bot
VSS
U2H
IC,AUB_CFD_rPGA,R1P0S_Bot
VSS1AT20VSS2AT17VSS3AR31VSS4AR28VSS5AR26VSS6AR24VSS7AR23VSS8AR20VSS9AR17VSS10AR15VSS11AR12VSS12AR9VSS13AR6VSS14AR3VSS15AP20VSS16AP17VSS17AP13VSS18AP10VSS19AP7VSS20AP4VSS21AP2VSS22AN34VSS23AN31VSS24AN23VSS25AN20VSS26AN17VSS27AM29VSS28AM27VSS29AM25VSS30AM20VSS31AM17VSS32AM14VSS33AM11VSS34AM8VSS35AM5VSS36AM2VSS37AL34VSS38AL31VSS39AL23VSS40AL20VSS41AL17VSS42AL12VSS43AL9VSS44AL6VSS45AL3VSS46AK29VSS47AK27VSS48AK25VSS49AK20VSS50AK17VSS51AJ31VSS52AJ23VSS53AJ20VSS54AJ17VSS55AJ14VSS56AJ11VSS57AJ8VSS58AJ5VSS59AJ2VSS60AH35VSS61AH34VSS62AH33VSS63AH32VSS64AH31VSS65AH30VSS66AH29VSS67AH28VSS68AH27VSS69AH26VSS70AH20VSS71AH17VSS72AH13VSS73AH9VSS74AH6VSS75AH3VSS76AG10VSS77AF8VSS78AF4VSS79AF2VSS80AE35
VSS81 AE34VSS82 AE33VSS83 AE32VSS84 AE31VSS85 AE30VSS86 AE29VSS87 AE28VSS88 AE27VSS89 AE26VSS90 AE6VSS91 AD10VSS92 AC8VSS93 AC4VSS94 AC2VSS95 AB35VSS96 AB34VSS97 AB33VSS98 AB32VSS99 AB31
VSS100 AB30VSS101 AB29VSS102 AB28VSS103 AB27VSS104 AB26VSS105 AB6VSS106 AA10VSS107 Y8VSS108 Y4VSS109 Y2VSS110 W35VSS111 W34VSS112 W33VSS113 W32VSS114 W31VSS115 W30VSS116 W29VSS117 W28VSS118 W27VSS119 W26VSS120 W6VSS121 V10VSS122 U8VSS123 U4VSS124 U2VSS125 T35VSS126 T34VSS127 T33VSS128 T32VSS129 T31VSS130 T30VSS131 T29VSS132 T28VSS133 T27VSS134 T26VSS135 T6VSS136 R10VSS137 P8VSS138 P4VSS139 P2VSS140 N35VSS141 N34VSS142 N33VSS143 N32VSS144 N31VSS145 N30VSS146 N29VSS147 N28VSS148 N27VSS149 N26VSS150 N6VSS151 M10VSS152 L35VSS153 L32VSS154 L29VSS155 L8VSS156 L5VSS157 L2VSS158 K34VSS159 K33VSS160 K30
VSS
N
C
T
F
U2I
IC,AUB_CFD_rPGA,R1P0S_Bot
VSS
N
C
T
F
U2I
IC,AUB_CFD_rPGA,R1P0S_Bot
VSS161K27VSS162K9VSS163K6VSS164K3VSS165J32VSS166J30VSS167J21VSS168J19VSS169H35VSS170H32VSS171H28VSS172H26VSS173H24VSS174H22VSS175H18VSS176H15VSS177H13VSS178H11VSS179H8VSS180H5VSS181H2VSS182G34VSS183G31VSS184G20VSS185G9VSS186G6VSS187G3VSS188F30VSS189F27VSS190F25VSS191F22VSS192F19VSS193F16VSS194E35VSS195E32VSS196E29VSS197E24VSS198E21VSS199E18VSS200E13VSS201E11VSS202E8VSS203E5VSS204E2VSS205D33VSS206D30VSS207D26VSS208D9VSS209D6VSS210D3VSS211C34VSS212C32VSS213C29VSS214C28VSS215C24VSS216C22VSS217C20VSS218C19VSS219C16VSS220B31VSS221B25VSS222B21VSS223B18VSS224B17VSS225B13VSS226B11VSS227B8VSS228B6VSS229B4VSS230A29
VSS_NCTF1 AT35VSS_NCTF2 AT1VSS_NCTF3 AR34VSS_NCTF4 B34VSS_NCTF5 B2VSS_NCTF6 B1VSS_NCTF7 A35
VSS231A27VSS232A23VSS233A9
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VREF_CH_A_DIMMVREF_CH_B_DIMM
CFG0
CFG3CFG4
VREFA_DDR3{16}VREFB_DDR3{15}
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
Arrandule
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never pull down for switchable graphic
R570
3.01K,1%R0402
ns
R570
3.01K,1%R0402
ns
H12
CPU_HOLEns
H12
CPU_HOLEns
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
R209 0ns
R209 0ns
R5733.01K,1%R0402
R5733.01K,1%R0402
R204 0ns
R204 0ns
R579 0 R0402R579 0 R0402
R572
3.01K,1%R0402
ns
R572
3.01K,1%R0402
ns
H13
CPU_HOLEns
H13
CPU_HOLEns
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
BRACKET1_Mylar
Mylar
BRACKET1_Mylar
Mylar
BRACKET
CPU_BRACKET
BRACKET
CPU_BRACKET
H11
CPU_HOLEns
H11
CPU_HOLEns
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
R
E
S
E
R
V
E
D
U2E
IC,AUB_CFD_rPGA,R1P0
R
E
S
E
R
V
E
D
U2E
IC,AUB_CFD_rPGA,R1P0
CFG[0]AM30CFG[1]AM28CFG[2]AP31CFG[3]AL32CFG[4]AL30CFG[5]AM31CFG[6]AN29CFG[7]AM32CFG[8]AK32CFG[9]AK31CFG[10]AK28CFG[11]AJ28CFG[12]AN30CFG[13]AN32CFG[14]AJ32CFG[15]AJ29CFG[16]AJ30CFG[17]AK30
RSVD34 AH25RSVD35 AK26
RSVD38 AJ26
RSVD_NCTF_42 AT3
RSVD39 AJ27
RSVD_NCTF_40 AP1RSVD_NCTF_41 AT2
RSVD_NCTF_43 AR1
RSVD_TP_86H16
RSVD45 AL28RSVD46 AL29RSVD47 AP30RSVD48 AP32RSVD49 AL27RSVD50 AT31RSVD51 AT32RSVD52 AP33RSVD53 AR33
RSVD_NCTF_54 AT33RSVD_NCTF_55 AT34RSVD_NCTF_56 AP35RSVD_NCTF_57 AR35
RSVD58 AR32
RSVD_NCTF_30C35RSVD_NCTF_31B35
RSVD_NCTF_28A34RSVD_NCTF_29A33
RSVD27J28RSVD26J29
RSVD16A19RSVD15B19
RSVD17A20RSVD18B20
RSVD20T9RSVD19U9
RSVD22AB9RSVD21AC9
RSVD_NCTF_23C1RSVD_NCTF_24A3
RSVD_TP_66 AA5RSVD_TP_67 AA4RSVD_TP_68 R8
RSVD_TP_71 AA2RSVD_TP_72 AA1RSVD_TP_73 R9
RSVD_TP_69 AD3
RSVD_TP_74 AG7
RSVD_TP_70 AD2
RSVD_TP_75 AE3
RSVD_TP_76 V4RSVD_TP_77 V5RSVD_TP_78 N2
RSVD_TP_81 W3RSVD_TP_82 W2RSVD_TP_83 N3
RSVD_TP_79 AD5
RSVD_TP_84 AE5
RSVD_TP_80 AD7
RSVD_TP_85 AD9
RSVD36 AL26RSVD_NCTF_37 AR2
RSVD1AP25RSVD2AL25RSVD3AL24RSVD4AL22RSVD5AJ33RSVD6AG9RSVD7M27RSVD8L28SA_DIMM_VREFJ17SB_DIMM_VREFH17RSVD11G25RSVD12G17RSVD13E31RSVD14E30
RSVD32 AJ13RSVD33 AJ12
RSVD_TP_59 E15RSVD_TP_60 F15
KEY A2RSVD62 D15RSVD63 C15RSVD64 AJ15RSVD65 AH15
VSS AP34
H14
CPU_HOLEns
H14
CPU_HOLEns
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Page Name
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
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TOPSTAR TECHNOLOGY
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Page Name
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
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0 1Description
Internal pull-up.Leave as "No Connect"
Top Block SwapMode
Default Mode
Integrated VRM Mode EnabledDisabledDefault(SPI): Leave both GNT0#and GNT1# floating. Boot:From PCI: Connect GNT1# to ground with 1k resistor,leave GNT0# FloatingFrom LPC:Connect both GNT0# and GNT1#to ground with 1k resistor
Default: floating Disables theinternal VccVRMEnables theinternal VccVRM
Weak internalpull-up
Intel ME CryptoTLS cipher suite With No confidentiality Confidentiality
Weak internal pull-up
HDA_SDO Weak internal pull-down /
1.Security measureOverridden2.Sampled on the risingedge of PWROK,disablesIntel ME& its freatures
Security measureenabled
Flash DescriptorSecurity
DMI termination voltage
/
/ Weak internal pull-up
Intel Anti-TheftTechnology
EnabledDisabledIntel Anti-TheftTechnology
Disabled Enabled
Configures DMIfor ESI
Reboot optionat power-up Default Mode No Reboot Modewith TCO Disabled
Default Mode
Weak internalpull-down
Weak internal pull-down /Weak internalpull-down
PCH StrappingName
INIT3_3V#
SPKR
GNT3#/GPIO55
INTVRMEN
GNT0#GNT1#
GNT2#/GPIO53
SPI_MOSI
NV_ALE
NV_CLE
HDA_DOCK_EN#/GPIO33
HDA_SYNC
GPIO15
GPIO8
GPIO27
10Kohm pull up to V3.3AL and 10K to GNDAs SML1DATA and 2.2K to V3.3AL
As SML1CLK and 2.2K to V3.3AL
As LVDS_DDC_SEL for DDC select
As ALW_ACK link to EC and 10K to V3.3AL
EXTSMI# Reserve for EC,10k to V3.3S
10Kohm pull up to V3.3S
As CLK_CR_48M for IT1337E output 48M clock
1Kohm pull up to V3.3ALAs TPAs TP
10Kohm pull up to V3.3S
Reserve 1K pull down to GND
minicard_CLKREQ# Reserve,10k to V3.3S
Reserve 10Kohm pull down to GND for debug
10Kohm pull up to V3.3SGPIO1 +V3.3S I/OGPIO2GPIO3GPIO4GPIO5GPIO6GPIO7GPIO8GPIO9GPIO10GPIO11GPIO12GPIO13GPIO14GPIO15GPIO16GPIO17GPIO18GPIO19GPIO20GPIO21GPIO22GPIO23GPIO24GPIO25GPIO26GPIO27GPIO28GPIO29GPIO30GPIO31GPIO32GPIO33GPIO34GPIO35GPIO36GPIO37GPIO38GPIO39GPIO40GPIO41GPIO42GPIO43GPIO44GPIO45
+V3.3S I/OD+V3.3S I/OD+V3.3S I/OD+V3.3S I/OD+V3.3S I/O+V3.3S I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O
10Kohm pull up to V3.3AL
As EC_RUNTIME_SCI# link to EC,10K to V3.3S
10Kohm pull down to GND for BIOS ver
8.2Kohm pull up to V3.3S
10K to GND,reserve 10K to V3.3S for debugAs PM_SUS_STAT# link to EC and 1k to V3.3AL
As USB_OC#2 for USB board
10Kohm pull up to V3.3AL
NC
4.7Kohm pull down to GND
10Kohm pull up to V3.3S
10Kohm pull up to V3.3S
EXPCARD_CLKREQ# Reserve,100k to V3.3AL
As LVDS_BLT_SEL for BLT select
10Kohm pull up to V3.3AL
10Kohm pull down to GND
10Kohm pull up to V3.3AL
10Kohm pull up to V3.3AL
10Kohm pull down to GND for BIOS ver10Kohm pull down to GND for BIOS ver
8.2Kohm pull up to V3.3S
As PCIE_CLKREQ for N10,10K to GND and 10K to V3.3GPU
10Kohm pull up to V3.3S
10Kohm pull up to V3.3S
As USB_OC#5 for USB board
Reserve 10Kohm pull up to V3.3S for debug
8.2Kohm pull up to V3.3S
10Kohm pull up to V3.3S
10Kohm pull up to V3.3AL10Kohm pull up to V3.3AL
10Kohm pull up to V3.3AL
10Kohm pull up to V3.3S
As AC_IN_PCH link to EC
As TP(test point)
As TP(test point)
8.2Kohm pull up to V3.3S
10Kohm pull up to V3.3S
Name Pin Attr DescriptionGPIO0 +V3.3S I/O
10Kohm pull up to V3.3AL
8.2Kohm pull up to V3.3S8.2Kohm pull up to V3.3S
Name Pin Attr DescriptionGPIO46GPIO47GPIO48GPIO49GPIO50
8.2Kohm pull up to V3.3AL
8.2Kohm pull up to V3.3AL
GPIO51GPIO52GPIO53GPIO54GPIO55GPIO56GPIO57GPIO58GPIO59GPIO60GPIO61GPIO62GPIO63GPIO64GPIO65GPIO66GPIO67GPIO72GPIO73GPIO74GPIO75
+V3.3A I/O+V3.3A I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O
8.2Kohm pull up to V3.3AL
NCNCNC
+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3S I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O+V3.3A I/O
10Kohm pull down to GND
10Kohm pull up to V3.3AL
10Kohm pull up to V3.3AL
10Kohm pull up to V3.3AL
MiniPCIE_REQ# Reserve,10k to V3.3S
10Kohm pull up to V3.3AL
As BAT_LOW# link to EC and 10K to V3.3AL
NC
10Kohm pull up to V3.3S
Reserve 1K pull down to GND
10No Physical DisplayPort attached toEmbedded Displayport
An external DisplayPort device isconnected to theEmbedded Display Port
DescriptionEmbeddedDisplayPortPresence
PCI-E StaticLane Reversal Normal Operation
Lane NumbersResersed 15->0.14->1,...
PIC-Express Configuration Select
Bifurcation enable Single PCIE Graphics
Note: Default value for each bit is 1 unless specified otherless
CFG[4]
CFG[3]
CFG[0]
Processor StrappingPin
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MB_B_A9
MB_B_A11
MB_B_A4MB_B_A5
MB_B_A7
MB_B_A3
MB_B_A8
MB_B_A1
MB_B_A10
MB_B_A6
MB_B_A12
MB_B_A2
MB_B_A13
MB_B_A0
MB_B_A14MB_B_A15
MB_DM1
MB_DM4
MB_DM0
MB_DM7
MB_DM3
MB_DM6MB_DM5
MB_DM2
MB_DQS5MB_DQS6MB_DQS7
MB_DQS3
MB_DQS1
MB_DQS4
MB_DQS0
MB_DQS2
MB_DATA58
MB_DATA55
MB_DATA61
MB_DATA54
MB_DATA59
MB_DATA62
MB_DATA60
MB_DATA57
MB_DATA63
MB_DATA52MB_DATA53
MB_DATA56
MB_DATA51
MB_DATA35
MB_DATA30
MB_DATA7
MB_DATA33
MB_DATA22
MB_DATA6
MB_DATA29
MB_DATA31
MB_DATA17
MB_DATA36
MB_DATA18
MB_DATA13
MB_DATA9
MB_DATA48
MB_DATA34
MB_DATA43
MB_DATA19
MB_DATA11
MB_DATA8
MB_DATA28
MB_DATA45MB_DATA46
MB_DATA16
MB_DATA0MB_DATA1
MB_DATA23
MB_DATA15
MB_DATA2
MB_DATA25
MB_DATA42
MB_DATA27
MB_DATA47
MB_DATA21MB_DATA20
MB_DATA5
MB_DATA44
MB_DATA37
MB_DATA50
MB_DATA10
MB_DATA49
MB_DATA14
MB_DATA40
MB_DATA38
MB_DATA32
MB_DATA24
MB_DATA41
MB_DATA3
MB_DATA12
MB_DATA26
MB_DATA39
MB_DATA4
MB_DQS#1MB_DQS#0
MB_DQS#3
MB_DQS#7
MB_DQS#4MB_DQS#5
MB_DQS#2
MB_DQS#6
VREFB_DDR3
VREFB_DDR3
VREFB_CA
VREFB_CA
+V1.5
+V1.5
+V1.5
+V3.3S
+V1.5+V0.75S
+V1.5 +V1.5
+V1.5 {8,11,16,49,56,57}+V3.3S {6,8,16,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58}
MB_B_A[15:0]{9}
MB_B_BS0{9}MB_B_BS1{9}MB_B_BS2{9}
M_CS#3{9}M_CS#2{9}
MB_DM[7:0]{9}
MB_B_WE#{9}MB_B_CAS#{9}MB_B_RAS#{9}
M_CKE2{9}M_CKE3{9}
M_CLK_DDR3{9}M_CLK_DDR#3{9}
M_CLK_DDR#2{9}M_CLK_DDR2{9}
M_ODT2{9}M_ODT3{9}
MB_DQS[7:0]{9}
SMB_DATA_S{6,16,23,40,41}SMB_CLK_S{6,16,23,40,41}
DIM_EXTTS#1{8}
MB_DATA[63:0] {9}
MB_DQS#[7:0] {9}
+V0.75S {16,49,56}
DDR3_DRAMRST#{8,16}
VREFB_DDR3 {13}
Page Name
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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DDR3 SODIMM1
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Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
DDR3 SODIMM1
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Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
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DDR3 SODIMM1
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Layout note:DDR slot VDD PIN
close to DDR pin1close to DDRpin199
Note:SO-DIMM1 SPD Address is 0xA4
C27
0.1UF/25V,Y5V
C0402ns
C27
0.1UF/25V,Y5V
C0402ns
C4610uF/6.3V,X5RC0805
C4610uF/6.3V,X5RC0805
C38
0.1UF/25V,Y5VC0402
nsC38
0.1UF/25V,Y5VC0402
ns
C34
2.2UF/10V,X7RC0805
C34
2.2UF/10V,X7RC0805
R471K,1%R0402
R471K,1%R0402
C300.1UF/25V,Y5V
C0402
C300.1UF/25V,Y5V
C0402
C35
2.2UF/10V,X7R
C0805ns
C35
2.2UF/10V,X7R
C0805ns
C44
0.1UF/25V,Y5VC0402
nsC44
0.1UF/25V,Y5VC0402
ns
C21
2.2UF/10V,X7RC0805
ns
C21
2.2UF/10V,X7RC0805
ns
C530.1UF/25V,Y5V
C0402
C530.1UF/25V,Y5V
C0402
C45
0.1UF/25V,Y5V
C0402
C45
0.1UF/25V,Y5V
C0402
C43
2.2UF/10V,X7RC0805
C43
2.2UF/10V,X7RC0805
C76
2.2UF/10V,X7R
C0805
C76
2.2UF/10V,X7R
C0805
C19
2.2UF/10V,X7R
C0805ns
C19
2.2UF/10V,X7R
C0805ns
C4810uF/6.3V,X5RC0805
C4810uF/6.3V,X5RC0805
C78
2.2UF/10V,X7RC0805
C78
2.2UF/10V,X7RC0805
C20
2.2UF/10V,X7RC0805
C20
2.2UF/10V,X7RC0805
R49 10K R0402R49 10K R0402
C47
10UF/6.3V,X5R
C0805
C47
10UF/6.3V,X5R
C0805
C280.1UF/25V,Y5V
C0402
C280.1UF/25V,Y5V
C0402
C31
2.2UF/10V,X7RC0805
C31
2.2UF/10V,X7RC0805
DIMM2
DDR3_SODIMM204_0
DIMM2
DDR3_SODIMM204_0
A098A197A296A395A492A591A690A786A889A985A10/AP107
D0 5D1 7D2 15D3 17D4 4D5 6D6 16D7 18D8 21D9 23
D10 33D11 35D12 22D13 24D14 34D15 36D16 39D17 41D18 51D19 53D20 40D21 42D22 50D23 52D24 57D25 59D26 67D27 69D28 56D29 58D30 68D31 70D32 129D33 131D34 141D35 143D36 130D37 132D38 140D39 142D40 147D41 149D42 157D43 159D44 146D45 148D46 158D47 160D48 163D49 165D50 175D51 177D52 164D53 166D54 174D55 176D56 181D57 183D58 191D59 193D60 180D61 182D62 192D63 194
DQS#0 10DQS#1 27DQS#2 45DQS#3 62DQS#4 135DQS#5 152DQS#6 169DQS#7 186
WE113
A1184A12/BC#83A13119
BA0109BA1108
CAS115RAS110
V
S
S
3
6
1
5
1
V
D
D
1
7
5
V
D
D
2
7
6
V
D
D
3
8
1
V
D
D
4
8
2
V
D
D
5
8
7
V
D
D
6
8
8
V
D
D
7
9
3
V
D
D
8
9
4
V
D
D
9
9
9
V
D
D
1
0
1
0
0
V
D
D
1
1
1
0
5
V
D
D
1
2
1
0
6
V
S
S
3
4
1
4
5
V
S
S
3
5
1
5
0
V
S
S
3
7
1
5
5
V
S
S
3
8
1
5
6
V
S
S
3
9
1
6
1
V
S
S
4
0
1
6
2
V
S
S
4
1
1
6
7
V
S
S
4
2
1
6
8
V
S
S
4
3
1
7
2
V
S
S
4
4
1
7
3
V
S
S
4
5
1
7
8
A1578
CS0114CS1121
DQM011DQM128DQM246DQM363DQM4136DQM5153DQM6170DQM7187
CKE073CKE174
CK0101CK0103CK1102CK1104
ODT1120ODT0116
DQS012DQS129DQS247DQS364DQS4137DQS5154DQS6171DQS7188
SDA200SCL202
SA0197SA1201
A1480
VDDSPD199
BA279
VREF_DQ1
RESET#30
NC177NC2122NCTEST125
V
S
S
2
3
V
S
S
3
8
V
S
S
4
9
V
S
S
5
1
3
V
S
S
6
1
4
V
S
S
7
1
9
V
S
S
8
2
0
V
S
S
9
2
5
V
S
S
1
0
2
6
V
S
S
1
1
3
1
V
S
S
1
2
3
2
V
S
S
1
3
3
7
V
S
S
1
4
3
8
V
S
S
1
5
4
3
V
S
S
1
6
4
4
V
S
S
1
7
4
8
V
S
S
1
8
4
9
V
S
S
1
9
5
4
V
S
S
2
0
5
5
V
S
S
2
1
6
0
V
S
S
2
2
6
1
V
S
S
2
3
6
5
V
S
S
2
4
6
6
V
S
S
2
5
7
1
V
S
S
2
6
7
2
V
S
S
2
7
1
2
7
V
S
S
2
9
1
3
3
V
S
S
3
0
1
3
4
V
S
S
3
1
1
3
8
V
S
S
3
2
1
3
9
V
S
S
1
2
V
S
S
2
8
1
2
8
V
S
S
3
3
1
4
4
V
S
S
4
6
1
7
9
V
S
S
4
7
1
8
4
V
S
S
4
8
1
8
5
V
S
S
4
9
1
8
9
V
S
S
5
0
1
9
0
V
S
S
5
1
1
9
5
V
S
S
5
2
1
9
6
G
N
D
1
2
0
5
G
N
D
2
2
0
6
VREF_CA126
EVENT#198V
T
T
1
2
0
3
V
T
T
2
2
0
4
V
D
D
1
3
1
1
1
V
D
D
1
4
1
1
2
V
D
D
1
5
1
1
7
V
D
D
1
6
1
1
8
V
D
D
1
7
1
2
3
V
D
D
1
8
1
2
4
C40
0.1UF/25V,Y5V
C0402
C40
0.1UF/25V,Y5V
C0402
R501K,1%R0402
R501K,1%R0402
C77
2.2UF/10V,X7RC0805
C77
2.2UF/10V,X7RC0805
R46 10K R0402R46 10K R0402
C39
2.2UF/10V,X7RC0805
C39
2.2UF/10V,X7RC0805
C25
0.1UF/25V,Y5VC0402
C25
0.1UF/25V,Y5VC0402
R511K,1%R0402
R511K,1%R0402
C29
2.2UF/10V,X7RC0805
C29
2.2UF/10V,X7RC0805
C75
2.2UF/10V,X7R
C0805
C75
2.2UF/10V,X7R
C0805
R481K,1%R0402
R481K,1%R0402
-
55
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MA_A_A1MA_A_A2MA_A_A3MA_A_A4MA_A_A5MA_A_A6MA_A_A7MA_A_A8
MA_A_A0
MA_A_A9MA_A_A10MA_A_A11MA_A_A12MA_A_A13MA_A_A14MA_A_A15
MA_DM1MA_DM0
MA_DM2MA_DM3
MA_DM5MA_DM4
MA_DM6MA_DM7
MA_DQS1MA_DQS0
MA_DQS2MA_DQS3MA_DQS4MA_DQS5MA_DQS6MA_DQS7
VREFA_DDR3
MA_DATA14
MA_DATA4
MA_DATA56
MA_DATA40
MA_DATA11
MA_DATA17
MA_DATA1
MA_DATA42
MA_DATA27
MA_DATA44
MA_DATA2
MA_DATA26
MA_DATA19
MA_DATA15
MA_DATA22
MA_DATA12
MA_DATA32
MA_DATA59MA_DATA58
MA_DATA41
MA_DATA45
MA_DATA63
MA_DATA50
MA_DATA33
MA_DATA51
MA_DATA5
MA_DATA60
MA_DATA20
MA_DATA49
MA_DATA38
MA_DATA3
MA_DATA47
MA_DATA61
MA_DATA28
MA_DATA18
MA_DATA43
MA_DATA48
MA_DATA37
MA_DATA13
MA_DATA29
MA_DATA10
MA_DATA62
MA_DATA53
MA_DATA55
MA_DATA23
MA_DATA52
MA_DATA54
MA_DATA35
MA_DATA31
MA_DATA46
MA_DATA30
MA_DATA16
MA_DATA39
MA_DATA8
MA_DATA34
MA_DATA25
MA_DATA57
MA_DATA36
MA_DATA6
MA_DATA0
MA_DATA21
MA_DATA9
MA_DATA24
MA_DATA7
MA_DQS#5
MA_DQS#7MA_DQS#6
MA_DQS#0
MA_DQS#2MA_DQS#3MA_DQS#4
MA_DQS#1
VREFA_DDR3
VREFA_CA
VREFA_CAVREFA_CA
+V3.3S
+V1.5+V0.75S
+V1.5
+V1.5
+V1.5
+V0.75S
+V1.5
+V1.5 {8,11,15,49,56,57}+V3.3S {6,8,15,22,23,24,25,26,27,28,29,31,32,33,34,35,37,38,39,40,41,42,43,44,45,49,50,51,52,53,55,56,57,58}
MA_A_A[15:0]{9}
MA_A_BS2{9}
MA_A_BS0{9}MA_A_BS1{9}
M_CS#1{9}M_CS#0{9}
MA_DM[7:0]{9}
MA_A_RAS#{9}MA_A_CAS#{9}MA_A_WE#{9}
M_CKE0{9}M_CKE1{9}
M_CLK_DDR0{9}M_CLK_DDR#0{9}
M_CLK_DDR#1{9}M_CLK_DDR1{9}
M_ODT1{9}M_ODT0{9}
MA_DQS[7:0]{9}
SMB_DATA_S{6,15,23,40,41}SMB_CLK_S{6,15,23,40,41}
MA_DQS#[7:0] {9}
DIM_EXTTS#0{8}
DDR3_DRAMRST#{8,15}
VREFA_DDR3 {13}
+V0.75S {15,49,56}
MA_DATA[63:0] {9}
Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
DDR3 SODIMM0
TOPSTAR TECHNOLOGY
C
16 59Friday, November 27, 2009
bent
C46
Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
DDR3 SODIMM0
TOPSTAR TECHNOLOGY
C
16 59Friday, November 27, 2009
bent
C46
Page Name
Size Project Name Rev
Date: Sheet ofPROPERTY NOTE: this document contains information confidential and property toTOPSTAR and shall not be reproduced or transferred to other documents or disclosedto others or used for any purpose other than that for which it was obtained withoutthe expressed written consent of TOPSTAR
A
DDR3 SODIMM0
TOPSTAR TECHNOLOGY
C
16 59Friday, November 27, 2009
bent
C46
close to DDR pin
Layout note:DDR slot VDD PIN
1, A minimum of 9 high frequencycapacitors are recommended to beplaced near each SO-DIMM of DDR2. 2, 2.2F*5 per DIMM,0.1F*4 perDIMM,330F*1 per DIMM
C23
0.1UF/25V,Y5V
C0402
C23
0.1UF/25V,Y5V
C0402
C3280.1UF/25V,Y5V
C0402
C3280.1UF/25V,Y5V
C0402
C721uF/10V,X7RC721uF/10V,X7R
C213
2.2UF/10V,X7RC0805
C213
2.2UF/10V,X7RC0805
C3272.2UF/10V,X7R
C0805
C3272.2UF/10V,X7R
C0805
C22
2.2UF/10V,X7RC0805
C22
2.2UF/10V,X7RC0805
C20810uF/6.3V,X5RC20810uF/6.3V,X5R
C36
0.1UF/25V,Y5V
C0402ns
C36
0.1UF/25V,Y5V
C0402ns
C24
0.1UF/25V,Y5V
C0402
C24
0.1UF/25V,Y5V
C0402
C49
2.2UF/10V,X7RC0805
nsC49
2.2UF/10V,X7RC0805
ns
C181uF/10V,X7RC181uF/10V,X7R
R4351K,1%R0402
R4351K,1%R0402
C33
2.2UF/10V,X7R
C0805
C33
2.2UF/10V,X7R
C0805
R531K,1%R0402
R531K,1%R0402
C26
0.1UF/25V,Y5V
C0402
C26
0.1UF/25V,Y5V
C0402
R54 0R54 0
C419
2.2UF/10V,X7RC0805
C419
2.2UF/10V,X7RC0805
C420.1UF/25V,Y5V
C0402
C420.1UF/25V,Y5V
C0402
R521K,1%R0402
R521K,1%R0402
C41810uF/6.3V,X5RC41810uF/6.3V,X5R
R4361K,1%R0402
R4361K,1%R0402
C520.1UF/25V,Y5V
C0402
C520.1UF/25V,Y5V
C0402
+1
C96
220uF/2.5V,POSCAP
CT7343_19ns
+1
C96
220uF/2.5V,POSCAP
CT7343_19ns
1
2
C41
2.2UF/10V,X7RC0805
C41
2.2UF/10V,X7RC0805
DIMM1
DDR3_SODIMM204_0
DIMM1
DDR3_SODIMM204_0
A098A197A296A395A492A591A690A786A889A985A10/AP107
D0 5D1 7D2 15D3 17D4 4D5 6D6 16D7 18D8 21D9 23
D10 33D11 35D12 22D13 24D14 34D15 36D16 39D17 41D18 51D19 53D20 40D21 42D22 50D23 52D24 57D25 59D26 67D27 69D28 56D29 58D30 68D31 70D32 129D33 131D34 141D35 143D36 130D37 132D38 140D39 142D40 147D41 149D42 157D43 159D44 146D45 148D46 158D47 160D48 163D49 165D50 175D51 177D52 164D53 166D54 174D55 176D56 181D57 183D58 191D59 193D60 180D61 182D62 192D63 194
DQS#0 10DQS#1 27DQS#2 45DQS#3 62DQS#4 135DQS#5 152DQS#6 169DQS#7 186
WE113
A1184A12/BC#83A13119
BA0109BA1108
CAS115RAS110
V
S
S
3
6
1
5
1
V
D
D
1
7
5
V
D
D
2
7
6
V
D
D
3
8
1
V
D
D
4
8
2
V
D
D
5
8
7
V
D
D
6
8
8
V
D
D
7
9
3
V
D
D
8
9
4
V
D
D
9
9
9
V
D
D
1
0
1
0
0
V
D
D
1
1
1
0
5
V
D
D
1
2
1
0
6
V
S
S
3
4
1
4
5
V
S
S
3
5
1
5
0
V
S
S
3
7
1
5
5
V
S
S
3
8
1
5
6
V
S
S
3
9
1
6
1
V
S
S
4
0
1
6
2
V
S
S
4
1
1
6
7
V
S
S
4
2
1
6
8
V
S
S
4
3
1
7
2
V
S
S
4
4
1
7
3
V
S
S
4
5
1
7
8
A1578
CS0114CS1121
DQM011DQM128DQM246DQM363DQM4136DQM5153DQM6170DQM7187
CKE073CKE174
CK0101CK0103CK1102CK1104
ODT1120ODT0116
DQS012DQS129DQS247DQS364DQS4137DQS5154DQS6171DQS7188
SDA200SCL202
SA0197SA1201
A1480
VDDSPD199
BA279
VREF_DQ1
RESET#30
NC177NC2122NCTEST125
V
S
S
2
3
V
S
S
3
8
V
S
S
4
9
V
S
S
5
1
3
V
S
S
6
1
4
V
S
S
7
1
9
V
S
S
8
2
0
V
S
S
9
2
5
V
S
S
1
0
2
6
V
S
S
1
1
3
1
V
S
S
1
2
3
2
V
S
S
1
3
3
7
V
S
S
1
4
3
8
V
S
S
1
5
4
3
V
S
S
1
6
4
4
V
S
S
1
7
4
8
V
S
S
1
8
4
9
V
S
S
1
9
5
4
V
S
S
2
0
5
5
V
S
S
2
1
6
0
V
S
S
2
2
6
1
V
S
S
2
3
6
5
V
S
S
2
4
6
6
V
S
S
2
5
7
1
V
S
S
2
6
7
2
V
S
S
2
7
1
2
7
V