toshiba t1100 plus - maintenance manual · toshiba tiioo plus is a portable personal computer which...

1.1 General

Toshiba TIIOO PLUS is a portable personal computer which is compatible with IBM PC and is situated at higher rank of portable computer than Toshiba TllOO. It provides many powerful functions in spite of its compact size. Hardware of the TllOO PLUS, most. of IC chips are,-f-MOS type so that the power consumption is very little :;'0 V W) and Gate Array IC chips are applied so that it is very mpact and light weight ( (:)

). J. 0 -rr t;- 151/ The TllOO PLUS System has following two types. 1. F type - Only one Floppy Disk Drive. 2. F/F type - Two Floppy Disk Drives.

The TllOO PLUS is composed of System PCB, Keyboard, LCD, 3.5" FDD (Floppy Disk Drive), Power Supply Unit and case. LCD can display 640 X 200 pixels in graphic mode and 2000 characters in character mode. The 3.5" FDD have capacity of 720KB. The standerd memory size of the TllOO PLUS is 256.KS and it is able to extend up to 640 KB with optional Memory Card. Option unit to the TllOO PLUS System are one Memory Card (384 KB), Modem Card and Interface Card are capable to be installed in the TllOO PLUS System Unit. The optional external unit attached to the system unit are 5.25" External PDD 2D (Storage capacity of 360 KB) and I/O Expansion Box are prepared. The TllOO PLUS has connectors of Color/Monochrome CRT Display port and RS232C port and Print r/FDD on the rear panel of the TllOO PLUS.

Figure 1-1 TllOO PLUS System To be continued.

1-2

System Configuration

~'-

TllOO PLUS System Unit (F Type , F/F Type)

~---------System PCB

t-----------LCD

~----------Keyboard

~----------Floppy Disk Drive (F Type - One FDD) (F/F Type - Two FDD)

~----------Power Supply

~----------Option Unit

To be continued.

,1) Memory Card ,2) Modem Card ·3) I/O Expansion Box and Interface Card .4) External Floppy Disk Drive (2D 5.25")

1-3

Configuration Matrix

Modules/Units *Subsystem

System Unit * System Board

CPU 256KB RAM Color/Graphics Controller & Interface Floppy Drive Controller & Interface Parallel Printer Port Keyboard Interface

* LCD (640 x 200 pixels) * Keyboard (81 keys) * Floppy Disk Drive (FDD)

F Typ~ ••• One FDD (3.5 II )

F /F Type .•• Two FDD (3. 5 " ) * Power Supply Unit (Battery and PCB) * Upper Cover * Lower Cover

Memory Expansion Card (384 KB)

Modem Expansion Card

I/O Expansion Box (and Interface Card)

Ext-erna1 Floppy Disk Drive (5.25") 2D

1-4

Standard Options

1

1 1

1 1 2 1

1 1

1

1

1

1

1.2 System UDit

The T11aa PLUS System Unit is composed of subunits. All subunits of T11aa PLUS system are built in one compact System Unit case. They are System PCB (Printed Circuit Board), 3.5" FDD (Floppy Disk Drive), LCD (Liquid Crystal Display), Keyboard, Power Supply Unit, Speaker and harnesses. In a maintenance service, the faulty subunit will be replaced with good spare subunits easily. Followings are showing locations of subunits of the T110a PLUS System Unit.

(1) Locations of subunits

LCD --------J.'fir-"i--

Upper Cover ________ ~~

Power Supply 'Unit

Speaker ~~~:?JI"""""'"

Lower

Indicator Plate

Keyboard Unit

FDD 1

Memory, Card (Option)

Figure 1-2 System Unit(F/F Type)

To be continued.

1-5

The System unit contains the following subunits.

System PCB 3.5" FDD (Floppy Disk Drive) LCD Keyboard Power Supply Unit Harnesses Covers

Ac Adaptor is used for rechargment of the Battery and/or power source to the TllOO PLUS System indoors by plug in the DC Jack on the back of the System.

AC Adaptor Input

output

I~o /07 /).J-~v (~-~V) For U.S.A. version 230v (207-253V) For Europe version 9V DC

(2) Locations of connectors and switches

Figure 1-3 Rear View of the TllOO PLUS

RS-232C Connector External FDD and Printer Connector Monochrome CRT Display Connector (Composit) Color CRT Display port (RGB) DC jack Power Switch PRT/FDD Select Switch LCD CONTRAST Dial

1-6

1.2.1 System PCB

System PCB is composed of processor (i80C86-2), RAM Memory (256KB for Main Memory, 32KB for Video RAM), ROM Memory· (32KB for BIOS, 32KB for Character Generater of CRTC), FDD Controller, Keyboard Controller, Display and Printer controller and Printer Adaptor. As the advanced technology, this PCB introduces four liGate Array" packages .

The System PCB houses:

- Central Processor Unit (CPU: i80C86-2 compatible l6-bit Processor. ) Clock speed is 4.77 MHz (Slow mode) or 7.16 MHz (Fast mode) . switching the clock speeds can be done by depressing some keys of keyboard. When the system power turns on, the processor runs at 7.16 MHz.

- Main Memory 256KB dynamic RAM (as standard configuration)

- PCB connector for additional Main Memory (from 256KB to 640KB) Internal 384 KB memory expansion cards.(Option)

3Z KBy ±>~*c; - BIOS ROM (256K-~j bes MASK ROM) including Initial

Reliability Test and Initial Program Loader.

Programmable Interrupt Controller (PIC: i8~C59A compatible) providing eight-level Interrupt Register/priority Logic, Interrupt Mask and Vector Address

- Programmable Interval Timer (PIT: i82C53 compatible)

- Direct Memory Access Controller (DMAC; i82C37 compatible) for Floppy Disk Controller, Hard Disk controller and serial Input/Output operation. .

- Floppy Disk Controller (FDC : TC 8565F compatible)

To be continued.

1-7

The System PCB houses (Continued):

- Calender Clock (Clock: TC82S0 compatible)

Calender Clock power are supplyed from unit. Battery (Ni-Cd) life lasts for ( dealer rep lac able ). When the power of on, this battery is charged. (NOTE)

the Ni-Cd battery about five years the system turns

If you haven r t used the system unit for tow months since battery has been charged, the stored data disappears.

- Universal Asynchronous Receiver Transmitter (UART for RS232C port : 82CSO compatible)

- Keyboard controller (80C49A compatible)

- DIP switch (Configuration information for Software)

- Parallel 8-bit Interface)

Printer

- BUS Controller Gate Array

Interface

(Bus control, Keyboard control, etc.)

- BUS Driver Gate Array

- I/O Decorder Gate Arrey

- Display Controller Gate Array

port (Centronics

(LCD, RGB-CRT, Monochrome-CRT, Composit signal control)

To be continued.

1-8

DMAC(82C37) PIT(82C53)

PJ15 PJ14 Ni-Cd Battery

CPU(80C86-2) (BIOS)

PJ6

9 PJ8 I/O DEC ORDER

(GA) BUS CONT

(GA)

Memory Chips ~~~'- (256KB)

EX03 16.000M PJ1

PRT/FDD Select Swi LCD CONTRAS BUS DRIVER(GA)

8586FCFDD CONT) TC8250

PJ1 DIP S

U8250 EX03 14.745M

DISPLAY CONT(GA) EX03 14.318M

PJ4 80C49CKB CONT)

Figure 1-4 System PCB

Connectors

PJ1 PJ2 PJ4 PJ6 PJ7 PJ8 PJ9 PJ10 PJ12 PJ13 PJ14 PJ15 PJ16

- Keyboard Connector - LCD Connector - Speaker Connector - FDD 1 Connector - FDD 2 Connector - LED Connector - Expansion Memory Card Connector - Power Supply Connector - Composit Video Connecto~ - Color CRT Display Connector - External FDD and Printer Connector - RS-232C Connector - Expansion BUS Connector

To be continued.

1-9

Configuration switches The TllOO PLUS System Unit configuration Swicth is 6 pin Dual-In Line Package (DIP) switches.

Figure 1-5 DIP switch

The meanings of all Configuration DIP Switch's settings are described in the following table.

SW DESCRIPTION

1 Should be always OFF

Amount of Memory System Board SW2,SW3

2,3 ON ON ... 256 KB OFF ON ... 384 KB ON OFF ... 512 KB OFF OFF ... 640 KB

Number of 3.5" drives 4 ON ...... One Floppy Disk Drive

OFF ...... Two Floppy Disk Drive

This is the switch to set port address of RS232C on the system board and I/O port address of modem card (option) of I/O expansion slot.

5 ON ....... I/O address of RS232C port -- COM-l I/O address of modem port ~COM-2

OFF ....... I/O address of RS23~C port -- COM-2 I/O address of modem port -COM-l

Enable/Disable Display Controller ON ....... En-abIes the Display Controller on

6 the System Board. OFF ....... Disables the Display Controller

on the System Board.

1-10

1.2.2 3.5- Floppy Disk Drive (POD)

The SMD-280L of 3.5" FDD is a high performance, high reliable, slim sized Floppy Disk Drive (FDD) for 3.5" floppy disks. The drive is able to read and write single or double density 3.5" floppy disk with 1M-bytes of recording capacity (unformatted) in double side, double density and 135 TPI.

Figure 1-6 3.5"FDD

1-11

Storage Capacity Unformatted Formatted

Performance Specification

(K-bytes) 1,000

720

Number of Heads/Drive 2

Track/Surface (tracks) 80

Data Transfer Rate (K-bits/Second) 250

Access Time" (ms) Per Track Average (Including Settling Time) Settling Time Head Load Time

Average Latency Time

Recording Density (Max.) Bit Density Track Density

Motor Start Time

Rotational Speed

(ms )

(BPI) (TPI)

(ms )

(RPM)

6 100

15 o * (I)

100

8,717 135

500

300

Recording Method MFM

Recording disk 3.5" ANSI Standard disk

Weight

Size

Note * (1)

(g)

(nun)

460

101.6(W) X l49.5{D) X 25.4{H)

Heads have been always loaded in operation mode.

1-12

1.2.3 Keyboard

The keyboard consists of 81 key tops crresponding number of Keyswitches (81) and matrix circuit, and it is connected to the System PCB through signal cable. The keyboard controller (80C49A) is built in on the System PCB. It is applied by chang ing the key tops with option key tops for character differences due to the Nations where the TIIOO PLUS is used

Figure 1-7 Keyboard

1-13

1.2.4 Liquid Crystal Display

LQ. The LCD Module (TeL-365-121) is flat panel 640 x 200 pixels Liquid Crystal Display unit with aspect ratio of the active area of four to three. The LCD can display graphic patterns, numerals, alphabets and symbols up to 2,000 charactors (8 x 8 dots charactor).

Figure 1-8 LCD

Clock

Supply Voltage (volts)

Number of Dot (pixel)

Number of Characters (Dot)

Dot Size (nun)

Dot pitch (mm)

+5V DC + 0.5V -15V DC ± 0.5V

640 (Horizontal) 200 (Vertical)

80 X 25 (2000 characters> (8 X 8 dot format>

0.46 H X 0.32 W

0.35 (Horizontal) 0.49 (Vertical>

Power Consumption (mW) 400

Size (mm) 275.0 X 126.0 X 15.8

Weight (g) 500

1-14

1.2.5 Power Supply Unit

The Power Supply Unit of the TllOO PLUS System Unit is housed Power Supply PCB and it furnishes DC power, +5, +9, -9 and -15 volts for all components in the TllOO PLUS System Unit. These power are supplyed from the Ni-Cd battery Unit or AC Adaptor.

This Power Supply Unit is Housed in System Unit and is designed to support the following:

Input (DC)

Output (DC)

1) System PCB 2) 3.5" FDD 3) LCD 4) Expansion PCB's

Figure 1-9 Power Supply Unit

+ 5V (from Battery Package) ::t /~ /,0 :! /sX

- 9V + 9V -15V + 5V

1-15

30mA lOrnA !lulA

c...; /. r-A

1.3 Option units

The TllOO PLUS has a variation of option units to be attached to the system. Following Units are possible to attached to the TllOO PLUS system.

1) Memory Expansion Card (384KB)

2) Modem Expansion Card

3) I/O Expansion Box and Interface Card

4) External Floppy Disk Drive (5.25") 20

1-16

1.3.1 Memory Expansion Card

The Expansion Memory unit is an option memory board to be installed on the System PCB. It is installed to the TllOa PLUS System Unit just by plugging in the connector on the System PCB and expands the memory size of the TllOO PLUS system till 640KB with the basic 384KB memory. When the Expansion Memory Unit is installed, the Configuration DIP Switch must be changed properly. (Refer to page 1-10)

WARNING

The Memory chip is very weak in a static electricity shock. When you handle the Expansion Memory board itself, it is recomended to protect the Expansion Memory Unit with anti static electricity materials.

Figure 1-10 Expansion Memory Unit

1-17

1.3.2 M.odem Expansion Card

The Expansion Modem Card is an option card which communicates wi th an external asynchronous communications device through an appropriate cable having modulatar jacks on both end. one end of the cable is connected to the External Modem Card and other end is to a wall jack of the telephone line.

It supports CCITT V. 22 asynchronous mode and BELL 2l2A. The specifications of this card are as follows.

Figure 1-11 Modem Expansion Card

Performasce Specification of Modem Card

Data Format Low Speed(O-300 BPS)

High Speed(1200BPS)

Dialing Capability

Audio Monitor

Receive Sensitivity

7 or 8 bits, 1 or 2 stop bits odd, even or noparity.

7 bits, no parity, 2 stop bits 7 bits, e/o parity, 1 stop bits 8 bits, no parity, 1 stop bits

Tone Dial/Pulse Dial

Speaker

-45dBm

1-18

1.3.3 I/O Expansion Box and Interface Card

Expansion Box is an option unit to provide the I/O channel to the TllOO PLUS System. This unit is composed of the Expansion I/O Cable, Interface Card, Expansion Box and AC Power Cord. The Expans ion Card, Backpanel Card and Power Supply are in the Expansion Box. Adding an Expansion Box provides five expansion slots.

An option adaptor in the Expansion Box and. the System Unit communicates through the Interface and Expansion Cards. The Interface Card is plugged into the EXP sockets at the rear of System Unit. This card is connected to the Receiver Card in the Expansion Box via a cable having 62-pin D-shell connectors at the both ends. The Expansion Card is mounted one of six Expansion Slots in the Expansion Box.

Figure 1-12 Expansion Box

Figure 1-13 Interface Card

1-19

1.3.4 5.25- External POD (SD-521)

The 50-521 is a high performance, high reliable, slim sized Floppy Oisk Orive (FOO) for 5.25" floppy disks. The drive is able to read and write single or double· density 5.25" floppy disk with 500KB of recording capacity (unformatted) in double side, double density and 48 TPI. TllOO PLUS System uses the 50-521 as external 5.25" FOO unit (option) .

Front View Rear View

Figure 1-14 5.25" External FOO (50-521)

1-20

Explanations on components

CD 5.25" External FDD 5.25" External FDD (Floppy Disk Drive) is composed of Disk Drive and Control PCB.

CD Connector Cable This cable is a signal cable between the FDD and the T1100 PLUS System Unit.

~ Disk Eject Button This button is used to remove a Floppy Disk from the FDD •

Cardboard Protector This cardboard is used for head protection shock during a transportation of the FDD.

against a

Dsub-Connector The Dsub-Connector Connector Cable.

Jack

is a 25-pin connector

The DC Jack is for connecting the AC Adaptor. The required specification of AC Adaptor is

Input 220-24DV ac Output 18V dc, 60DmA

for

(2) Power Switch Push the rear portion of the switch to Power ON. Push the front portion of the switch to Power OFF.

the

C!) Drive Unit Select Indicator It is lit while the FDD is selected to use by The TllDD PLUS system. Do not eject a disk while it is lit.

1-21

Performance Specification of SO-521

Storage Capacity (K-bytes) Unformatted 500 Formatted (9 Sectors/Track) 360

Number of Heads /Dr i ve 2

Track/Surface (tracks) 40

Data Transfer Rate (K-bits/Second) 250 ---------------------------------------~----------------------Access Time (ms)

Per Track 6 Average 97 Settling Time 15 Head Load Time 0

Recording Density (Max.) Bit Density Track Density

Motor Start Time

Rotational Speed

(BPI) (TPI)

(s)

(RPM)

5,876 48

0.5

300

Recording Method MFM

1-22

1.4 CRT Display Interface Connector

The TllOO PLUS system has CRT Display Interface connector on the back of TllOO PLUS System Unit. You can connect the following types of CRT Display to the TllOO PLUS System Unit.

1) Medium Resolution Color Display Unit

320 x 200 pixel's Color CRT Display. It can display 80 column x 25 line or 40 column x 25 line characters in character mode on one frame. It can be connected to the TllOO PLUS System through D-sub 9-pin connector.

2) Low Resolution Monochrome Display Unit

640 x 200 pixel's Monochrome CRT Display. It can display 640 x 200 pixel graphic pattern. It can display 80 column x 25 line or 40 column x 25 line characters in character mode. It connected through phone jack.

Medium resolution color CRT display

Low resolution monochrome CRT display

Figure 1-18 Rear View of TllOO PLUS System Unit

1-23

Specification

Unit type I Signal I Description

1.Medium Resolution Color Display unit

Connector 9-pin D-sub

Video signal 14.3 MHz (Max) Red video : positive level

TTL compatible Green video: Positive level

TTL compatible Blue video : positive level

TTL compatible

Vertical drive 60 Hz refresh rate 200 scan lines displayed

(non-interlace) positive level, TTL compatibel

------------------r---------------------------------------Horizontal drive 15.75 KHz scan rate

320/640 pixels displayed positive level, TTL compatible

2. Low Resolution Monochrome Display

Connector Phone Jack type ------------------r---------------------------------------Video signal 14.3 MHz (Max.)

positive level (1.5v peak to peak) ------------------ ------------------~--------------------Vertical sync 60 Hz refresh rate

200 scan lines displayed (non-interlace)

524 scan lines interlaced total

Horizontal sync 15.750 KHz scan rate 320/640 pixels displayed

1-24

This PART is a Trouble Isolation Procedures (TIP's) for the TIIOO PLUS system . It is based on the FRU (Field Replaceable Unit) which is defined in PART 7. The target of this Trouble Isolation Procedures is to isolate the faulty unit from the system and replace it in the field.

The required tools for this trouble-shooting are as follows.

1). MS-DOS System Disk (including T&D program)

2). Work Disk (for FDD test)

3) . AVO meter

4). Cleaning Disk

5). Screwdrivers (Blade screwdriver and Phillips screwdriver)

6). Printer port LED

7). Printer Wraparound Connector

8). RS-232C Wraparound Connector

For the trouble-shooting, you are required to read the T&D operation procedure of PART 8 of this manual.

You will follow the Trouble Isolation Procedures (TIP's) to isolate the failing Field Replaceable Unit (FRU) in case you met a failure on the FRU of the TOSHIBA Personal Computer TIIOO PLUS. The TIP's are composed of the following groups, and the TIP's in these groups will lead you to failing FRU.

The [ENTRY] is the isolation procedure of which TIP should be taken for the trouble. Another TIP's are of the units which will be given by [ENTRY], or the suspected units. Start from next page, for any trouble shooting.

4-2

Pault component (PRO) is identified already ?

1. If fault component (FRU) is identified already, or obvious problem such as unusual noise or damaged part on a component, go to the appropriate TIP (Trouble Isolation Procedure).

TIP

Power On Diagnostic

Power Supply Unit

System PCB

FDD (3.5" Int. FDD)

Keyboard

LCD

External FDD

Pa e

4-14

4-12

4-24

4-31

4-54

4-62

4-80

2. If fault component (FRU) is not identified, go to next page.

4-3

ENTRY

Before the Trouble Isolation Procedure

Set up the system to standard for checking.

1. Turn OFF the power switch of the System Unit.

2. Discnnect the all connectors from rear panel.

3. Check that the PRT/FDD select switch at the left side (from the view point where you are facing the LCD) of the System Unit is set to PRT side.

4. Rotate the LCD CONTRAST Dial fully to the direction of nHigh".

5. Release the latches by sliding them forward, hold the latches and pull up the display, then open the' LCD. And go to Enter-I.

"''''" ....... I"!I ,Eae to!

J 1

Figure 4-1 Before the Trouble Isolation Procedure

4-4

ENTER-l

LED check

1. Turn ON the power of System Unit.

2. Check that the LED (Power/Speed) of indicator lighting.

Figure 4-2 LED Check

Is the LED lighting ?

Yes: Go to ENTRY-2.

No: Go to POWER.

~ Power/Speed

If you have disassembled the System Unit before, confirm that the Indicator cable is connected correctly to the System PCB (PJa). (refer to PART 5)

4-5

ENTRY-2

check

1. Check that the isplay indicats all dots momentarily after\ turning the power ON .

.. \.

Figure 4-3 Display indicats all d

Are the above all dots displayed ?

Yes: Go to ENTRY-3.

No: The LCD may be faulty. Go to LCD.

4-6

second

ENTRY-3

Screen check at the start up time

1. Confirm that the following message appears on the display screen.

MEMORY TEST XXX KB

Does the above message appear ?

Yes: Go to ENTRY-4.

No: The System PCB may be faulty. Go to SYSTEM PCB.

4-7

ENTRY-4

Speaker check

1. After MEMORY TEST XXX KB message appears on the display screen, check that Beep sound from speaker.

Figure 4-4 Check the beep sound

Is the speaker Beep sound ?

Yes: Go to ENTRY-S.

No: Turn OFF the power switch of the System Unit. Confirm that the Speaker cable is connected to the System PCB. (refer to PART 5) If the Speaker cable is connected to System PCB, replace the Speaker Unit with a good spare Speaker Unit. (Refer to PART 5) If the failure remains, the System PCB may be faulty. Go to SYSTEM PCB.

4-8

ENTRY-S

Message check

1. Confirm that the following message appears on the display screen, about 15 seconds after the Beep sound from the speaker:

Place s~stem disk in d~ive. P~ess an~ ke~ when ready.


Yes: Go to ENTRY-6.

No: System PCB may be faulty. Go to FDD. Rate: If the MS-DOS system disk has been inserted in

the FDD before the power ON, the above massage is bypassed. (Go to ENTRY-6 )

4-9

ENTRY-6

MS-DOS loading cheak

1. Insert the MS-DOS system Disk into the internal disk drive and press the any key.

2. After the MS-DOS loading, press the "ENTER" key twice.

3. Confirm that the following message appears on the display screen.

ToshJba Personal Computer (R2100EN)

Copyright 1984,86 Toshiba Corporation

MS-DOS Ver 2.11 Copyright 1983,84 Microsoft Corp.

Command Ver 2.11V Current date is Wed 1-01-1986 Enter nelll date : Current time is 0:36:46.00 Enter nelll time:

A)

Prel iminary version


Yes: Go to ENTRY-7.

No: You may use a damaged MS-DOS System Disk. Replace the good MS-DOS System Disk, then repeat the operation to verify it. If failure remains, the Floppy Disk Drive may be faulty. Go to !'DO.

4-10

ENTRY-7

Input check

1. Input file name of CE DIAGNOSTIC as testce to load the diagnostic program. The underlined position on the follow screen are to input testce message.

2. Confirm that the testce message is inputed on the screen.

Toshiba Personal Computer (R2100EN)

Copyright 1964,66 Toshiba Corporation

MS-DOS Ver 2.11 Copyright 1963,64 Microsoft Corp.

Command Ver 2.11V Current date is Wed 1-01-1966 Enter new date : Current time is 0=36=46.00 En-ter new time :

A>testce


Is the message inputed ?

Yes: Press the "ENTER" key. Execute the T&D operation. (Refer to PART 8)

No: Go to KEYBOARD.

4-11

POWER-ON DIAGNOSTICS

This section describes how to execute the POWER-ON DIAGNOSTIC TEST .

You need to prepare the Printer Port LED (maintenance tool).

POWER ON DIAGNOSTIC TEST is for executing System PCB test.

Go to POWER-ON DIAGNOSTIC-l •

4-12

POWER-ON DIAGNOSTIC-l

Set the Printer Port LED


2. Disconnect the all cables from the System Unit of rear panel.

3. Connect the Printer Port LED (A) (Maintenance tool) to PRT/FDD connector (B)· of the System Unit (rear panel) as shown below.

4. Confirm that the PRT/FDD select switch (C) is set to PRT side.

POWER

OFF~ON

Figure 4-5 Printer Port LED Setting

4-13

POWER-ON DIAGNOSTIC-2

Run the Power-On Diagnostic

1. Turn ON the power switch of the System Unit to run the Power-On Diagnostics.

2. Confirm that the LED of Printer Port LEO is lighted.

Figure 4-6 Printer Port LED

Is the Printer Port LED lighted ?

Yes: Go to POWER-ON DIAGNOSTIC-3.

No: Go to POWER.

4-14


Read error status and isolate the failre component.

You may have an error condition in the Power-On Diagnostics, and the status has been indicated on the Printer Port LED. (NOTE) The status D5(8) means no error.

1. Read the error status on the Printer Port LED.

2. Isolate the failure component in accordance with the following chart of Power-On Diagnostics.

ex. : Brror status =

Printer Port LED

Figure 4-7 Indicat on the Printer Port LED

<order number :

3. In the following flow chart of the Power-On Diagnostics, sequence of the subtest executions is shown by arrow marks. In each subtest, all possible error status and information corresponding the error are described as below.

To be continued.

4-15


Read error status and isolate the failure component (continued)

Test Name Status

OK No good

T BIOS ROM Test

1 TimelC82C53) Test

DMACt82C37) Test

RAM !/W Test for First 16KB

PIC(82Cs9) Test

VIDE! RAM Test

DISPLAY §A Test

AA (H)

Ds (H)

12 (H)

14 (H)

16 (H)

18 (H)

FE (H)

Is the Brror Status disappear ?

Yes: Go to SYSTEM PCB-I.

No: Go to SYSTEM PCB-4.

4-16

01 (H)

02 (H) 03 (H)

04 (H) 05 (H)

06 (H) 07 (H)

08 (H) 09 (H) OA (H) OB (H)

OC (H)

OD (H) OE (H)

POWER (Power Supply Unit)

You have reached this TIP since the Power Supply Unit is suspected of the cause of failure.

You need to prepare the good Power Supply Parts and Power Supply Unit for maintenance.

The symptom may be one of follows.

1) No character is on the LCD Display.

2) No LED is on the Printer Port LED.

3) power/Speed indicator could not be OFF.

4) Error status is disappeared on the Printer port LED.

Go to POWER-l for the symptom 1, 2, 3 or 4 of the above.

4-17

POWER-l

LED (Low Batt.) check

1. Turn ON the power switch of the System unit.

2. Confirm that the LED (Low Batt.> of indicator lighting.

Figure 4-8 LED (Low Batt.) Check

Is the LED (Law Batt.) lighting?

Yes: You need to charge the batteries, then repeat the operation. If failure remains, go to POWER-4.

No: Go to POWER-2.

4-18

POWER-2

Connector Check


2. Disassemble the Upper Cover of the System Unit. <Refer to PART 5)

3. Check that the three cables <PJl, PJ3, PJ4) are connected correctly & securely.

Figure 4-9 Connector Check

Are the connectors and cables connected correctly 6 securely ?

Yes: Go to POWER-3.

No: Correct them and repeat the operation to verify it. If failure remains, go to POWER-3.

4-19

POWER-3

Output voltage check

1. Turn ON the power switch of the System Unit.

2. Check all output voltage of +9V, -9V, -lSV and +SV DC with AVO meter. (Refer to next page)

Figure 4-10 Output Voltage Check

To be continued.

4-20

POWER-3

OUtput voltage check (Continued)

Output voltage torerance

Connector Pin Voltaqe +lead -lead Normal Vdc Min Vdc Max Vdc

1 4 + 9 f7tJO 7'/°6 PJ 1

2 4 - 9 -/°'0 -J'n 3 4 - 15 -1r.O -/;40

I~ .:l... ~ -tr- t'l-O 7'<';0 ~ ~ tr

PJ# o/':. "'" -, '7 ,--' ~

Are all output voltages in tolerance ?

Yes: Power Supply PCB and Battery Package is good.

No: In the case of the PJ 3 output voltage in tolerance, go to POWER-4. In the case of the PJ land PJ 4 output voltage in tolerance, go to POWER-S.

4-21

POWER-4

Replacement Battery Package

1. Turn OFF the power switch of the Power Supply Unit.

2. Replace the suspected Battery Package with a good spare Battery Package.


4. Repeat the operation to verify it.

Does the failure remain ?

Yes: Battery Package is good. Go to POWER-S.

No: Battery Package is faulty.

4-22

POWER-S

Replacement Power Supply PCB


2. Replace the suspected Power Supply PCB with a good spare Power Supply PCB.




Yes: Power Supply PCB is good. Another Unit may be suspected.

No: Power Supply PCB is faulty.

4-23

SYSTEM PCB

You have reached this TIP since the System PCB is suspected of the cause of failure. You need to prepare the Printer Port LED for maintenance and good spare System PCB for replacement.


1) The Power-On Diagnostics could not run at all. No error status is indicated on the Printer Port LED.

2) An error status has been indicated on the Printer Port LED during the Power-On Diagnostics.

Go to SYSTEM-l for the trouble shooting of above symptoms.

4-24

•

SYSTEM PCB-l

Set the Printer Port LED

1. Turn OFF the power switch of the System unit.

2. Disconnect the all connectors from rear panel.

3. Connect the Pr inter Port LED (A) to the PRT/FDD connector (B) of the System Unit.

4. Confirm that PRT/FDD select switch (C) is set to PRT side.


6. Check whether the symptom disappears or not to Printer Port LED.

(Refer to POWER-ON DIAGNOSTIC )

( A)

\ .~

Figure 4-11 Set the Printer Port LED

Does the symptom disappear?

Yes: Failure is the one of separated units. Connect each separated unit one by one to the System Unit and run Power-On Diagnostics for the failure unit isolation. Turn OFF the power switch of the all units before making disconnection.


4-25

SYSTEM PCB-2

Remove all option PCB(s)


2. Remove all option PCB(s) (Expansion Memory Card (A) and Modem Card or Interface Card (B) ). Note : If the mamory size of the System Unit have been

changed you must change the setting of configuration DIP switch (C).

3. Turn ON the power switch of the System Unit then check the error status on the Printer Port LED.

(Refer to POWER-ON DIAGNOSTIC-3

(B)

'10

Figure 4-12 Option PCB Removal


Yes: Failure is the one of option PCB(s). Reinstall each option PCB one by one to the System Unit and run Power-On Diagnostics for the failure PCB isolation. Turn OFF the power switch of the System Unit before making removal and reinstallation of each option PCB.


4-26

SYSTEM PCB-4

Disconnect all signal cables


2. Disconnect all signal cable connectors of Int. FDD (A), Indicator (B), LCD (C) and Keyboard Unit (D).

3. Turn ON the power switch of the System Unit, then check the error status on the Printer Port LED.

Figure 4-13 Disconnect


Yes: Falure is one of Int. FDD, Indicator, LCD Display or Keyboard. Connect each unit of them one by one to the System Unit and run Power-On Diagnostics for failure unit. Turn OFF the power switch of the System Unit before each disconnection and connection of unit.

No: Go to SYSTEM PCB-S.

4-27

SYSTEM PCB-S

Voltage check

1. Check the voltages at connector pin with AVO meter. (Refer to next page.) Note: When you check the voltage at LCD connector (PJ2),

connect the LCD connector to System PCB. GND point is (A).

~,Z " , '.'

I

Z

Figure 4-14 Voltage Check

To be continued.

4-28

STSTEM PCB-S

Voltaqe check (Continued)

Voltage Tolerance

r /

I

Connector

PJ 2

PJ 6

PJ 7

PJ 8

\ ~J 2-L

Pin +Lead

12

1,3,5 7,9

1,3,5, 7,9

2

I /tj ( I I

-Lead Normal Vdc

GND + 5 (LC-£»)

GND + 5

GND + 5

GND + 5

<t-N P ( -IS-

Voltage Min Vdc

0 +-~. 7_ ,

+~

'1. t

+ t. 75 jL/~

'f~ ~

-/>; ~

Is the voltage in tolerance?

Yes: Go to SYSTEM PCB-6.

No: Go to POWER-I.

4-29

Max Vdc

+.t:P +~

~?

+ 5 ;-38

1-'7

C-:J I - Iff·3 I I I

I l .\ --1

SYSTEM PCB-6

System PCB replacement

1. Replace the suspected System PCB with a good spare System PCB. Note: You need to set the DIP switch. (Refer to page 1-10.>




Yes: The System PCB is good. Another Unit may be suspected.

No: The System PCB is faulty.

4-30

POD (3~5· Intarnal Ploppy Disk Drive)

You have reached this TIP since FDD is suspected of the cause of the failure. For the trouble shooting, you need to prepare one good spare 3.5" Int. FDD for the replacement. You need to prepare one work disk for Test program and Cleaning disk for head cleaning. Work disk must be formated. (Refer to PART 8)

Before the trouble-shooting, confirm that PRT/FDD select switch of the TIIOO PLUS System Unit is set to PRT position and rotate the LCD CONTRA~T Dial fully to the direction of "High".

DD 2

Figure 4-15 TIIOO PLUS System Unit (F/F type)

4-31

PDD-I

LED of PDD Check

1. Confirm that the Floppy Disk is inserted into the FDD. If the Floppy Disk is inserted into the FDD, remove the Floppy Disk from the FDD.

2. Turn ON the power switch of the System unit.

3. Confirme that both Disk in Use (Upper/Lower) light sequentialy, ~ indicator (Upper) light then ~ indicator(Lower) light.

{ _ J or .hfk Y','" }..

Figuren 4-16 LED Check

Is the LED lighting ?

Yes: Go to PDD-2.

No: System PCB may be faulty. Go to SYSTEM-PCB

4-32

indicators at first,

FDD-2

The MS-DOS loading


2. Insert the MS-DOS system disk to the internai disk drive, then turn ON the power of the System Unit.

3. The MS-DOS is loaded after Power On Diagnostic execution.

4. After the MS-DOS loading, confirm that the following message appears on the display screen.

5. Press the "ENTER" key twice, then input file name of CE Diagnostic as testce to load the diagnostic program.


Copyright 1984J8b Toshiba Corporation

MS-DOS Ver 2.11 Copyright 1983J84 Microsott Corp.

Command Ver 2.11V Current date is Wed 1-01-198b Enter new date : Current time is O:3b:4b.OO Enter new time:

A>testce


Is the above message displayed?

Yes: The underlined portion on the above screen are for the input testce message. Press the "ENTER" key. Go to FDD-S.

No: Go to the next page.

4-33

FDD-2

Loading the MS-DOS (Continued)

6. Confirm that the following message on the display screen.

Place s~stem disk in d~ive. P~ess an~ ke~ when ~ead~.


Yes: You may use a damaged system disk. Prepare the other good MS-DOS system disk, then repeat the turn ON the power switch of the System unit to verify it. Head of FDD may be dirty. Clean the head of FDD (Refer to PART 8 ). If the failure remains, go to FDD-IO (F type) or FDD-4 (F/F type).

No: Go to FDD-3.

4-34

PDD-3

Prepare the good MS-DOS system disk

1.

2.

3.

4.

Turn OFF the power switch of the System unit.

You may use a different system disk. Prepare the good MS-DOS system disk.

Turn ON the power switch of the System Unit.

Confirm that the MS-DOS is loarded. (Refer to PDD-2 )

Is the MS-DOS Ioarded ?

Yes: Go to PDD-S .

No: Head of FDD may be dirty. Clean the head of FDD (Refer to PART 8). Repeat the opration to verify it, then if the MS-DOS is loaded, go to FDD-IO ( F Type) or go to FDD-4 ( F IF Type) .

4-35

FDD-4.

Use the FDD 2


2. Insert the MS-DOS system disk to other FDD (FDD 2).


4. Confirm that the MS-DOS is 10arded. (Refer to FDD-2 )

Figure 4-17 Use the FDD 2

Is the lIS-DOS loaded ?

Yes: FDD 1 is faulty. Go to FDD-IO.

No: Though FDD 2 is on ready, it may be interfered by FDD 1. Remove the Upper Cover (Refer to PART 5), disconnect the FOD 1 cable from System PCB. Repeat the operation to verify, then the MS-DOS is loaded, go to FDD-5. If the failure remains, go to FDD-IO.

4-36

FDD-S

Diagnostic Menu Check

1. After the T&D program loading, confirm that the following Diagnostic Menu appears on the screen.

The TOSHIBA personal computer DIAGNOSTICS version 0.12 (c) copyright TOSHIBA Corp 1986

DIAGNOSTICS MENU :

1 - DIAGNOSTIC TEST 2 - HARD DISK FORMAT 3 - SEEK TO LANDING ZONE (HDD) 4 - HEAD CLEANING 5 - LOG UTILITIES b - RUNNING TEST 7 - FDD UTILITIES 8 - SYSTEM CONFIGURATION 9 - EXIT TO MS-DOS

PRESS C1J-C9J KEY

Is the above message displayed?

Yes: Go to FDD-6.

No: You may use a damaged disk. Prepare the other MS-DOS system disk, then repeat the operation to verify it. (press "Ctrl"+"Alt"+"Del" keys) If the failure remains, go to FDD-IO.

4-37

FDD-6

Diagnostic Test Menu Check

1. Press "1" then "Enter" keys to display the Diagnostic Test Menu.

2. Confirm that the following Diagnostic Test Menu appears on the screen.


DIAGNOSTIC TEST MENU

1 - SYSTEM TEST 2 - MEMORY TEST 3 - KEYBOARD TEST 4 - DISPLAY TEST 5 - FLOPPY DISK TEST o - PRINTER TEST 7 - ASYNC TEST 6 - HARD DISK TEST 9 - REAL TIMER TEST

10 - NDP TEST 88 - FDD & HOD ERROR RETRY COUNT SET 99 - EXIT TO DIAGNOSTICS MENU

PRESS (0]-(9] KEY

Does the above message displayed?

Yes: Go to FDD-7.

No: You may use a damaged disk. Prepare the other MS-DOS system disk, then repeat the operation to verify it. (press "Ctrl"+"Alt"+"Del a keys) If the failure remains, go to FDD-IO.

4-38

FDD-7

Test Number Select

1. Press "5" then "Enter" keys to select the Floppy Disk Test.

2. Confirm that the following message appears under the Diagnostic Test Menu.

Tha TOSHIBA personal computer DIAGNOSTICS version 0.12 (c) copyright TOSHIBA Corp 1986

, DIAGNOSTIC TEST MENU I

1 - SYSTEM TEST 2 - MEMORY TEST 3 - KEYBOARD TEST 4 - DISPLAY TEST 5 - FLOPPY DISK TEST b - PRINTER TEST 7 - ASYNC TEST 8 - HARD DISK TEST 9 - REAL TIMER TEST

10 - NDP TEST 88 - FDD ~ HOD ERROR RETRY COUNT SET 99 - EXIT TO DIAGNOSTICS MENU

Test drive number select (1:FDD1J2:FDD2JO:FDD1~2) ?

PRESS (0)-(9) KEY 5


Yes: Select the test drive number. For FDD 1 test, press "1" then "Enter" keys. For FDD 2 test, press "2" then "Enter" keys. For FDD 1 and FDD 2 test, press "0" then "Enter" keys. Go to FDD-8.

No: You may use a damaged disk. Prepare other MS-DOS system disk, then repeat the operation to verity it. (press "Ctrl"+"Alt"+"Del" keys) If the failure remains, go to FDD-IO.

4-39

FDD-8

Ploppy Disk Test Menu

1. Confirm that the floppy Disk Test Menu is displayed as shown below.

FLOPPY DISK XXXXXXX

SUB-TEST XX PASS COUNT: XXXXX WRITE DATA: XX

ERROR COUNT: XXXXX READ DATA XX

ADDRESS XXXXXX STATUS XXX

SUB-TEST MENU :

01 - Sequential read 02 - Sequential read/write 03 - Random address/data 04 - Write specified address 05 - Read specified address 99 - Exit to DIAGNOSTIC TEST MENU

SELECT SUB-TEST NUMBER ?

2. Execute each sub-test in accordance with T&D operation procedures in PART 8. Note: You need to prepare the good Work Disk for test

execution.

Is any error message display ?

Yes: Go to PDD-9.

No: FDD is good. Anoter Unit may be suspected.

4-40

P'DD-9

Connector Check


2. Disassemble the Upper Cover. (Refer to PART 5)

3. Check that the FDD cable (s ) (PJ 6, PJ 7) are connected correctly and securely.


Is the FDD cable connection with the connector & correctly?

Yes: Go to P'DD-IO.

No Conneect them, then repeat the T&D operation to verify it. If the failre remain, go to FDD-l0.

4-41

FDD-IO

POD connector check


2. Remove the FDD Unit. (Refer to PART 5)

3. Spread the four nai1es (A) with the blade screwdr iver to remove as shown below.

Figure 4-19 FDD Cover Removal

To be continued.

4-42

PDD-IO

POD conectors check (Continued)

4. Confirm that the five (J3, J4, J5, J6, J7 connected to FDD PCB.

J3 rh I I I I L.J

o

o 0 0

Figure 4-20 FDD PCB

Are the all cables connected ?

Yes: Go to PDD-IO.

cables are

No.: Connect them, then repeat the operation to ver ify it.

4-43

PDD-ll

PDD PCB Replacement

1. Remove the two screws (A), then spread two nailes (B) with the blade screwdriver and disconnect the soket (C).

Figure 4-21 FDD PCB Removal

To be continued.

4-44

FDD-II

PDD PCB Replacement (Continued)

2. Disconnect two cables (D) from FDD PCB with a pair of tweezers hooking in the hole as shown below.

3. Disconnect the two connector (E) from the FDD PCB to remove.

4. Replace the suspected FDD PCB with a good spare FDD PCB.

5. Turn on the Power switch of the System Unit.

6. Repeat the T&D operation to verify it.



Yes: FDD PCB is good. Go to FDD-12.

No: FDD PCB is faulty.

4-45

FDD-12

FDD mechanical parts replacement

1. Replace the suspected FDD mechanical parts with a good spare FDD Device.

2. Install the FDD Unit, then turn ON the power switch of the System Unit.


Does the Failure remain ?

Yes: The FDD mechanical parts is good. Go to FDD-13.

No: The FDD mechanical parts faulty.

4-46

FeD-13

PDD Replacement

1. Replace the suspected FDD with a good spare FDD.

2. Install the FDD Unit, then turn ON the power switch of the System Unit.

3. Repeat the T&D opration to verify it.


Yes: The FDD is good. Another Unit may be suspected.

No: The FDD is faulty.

4-47

POD-I 4

POD Adjustment

NOTE ••• Following items are not applzed to field maintenance.

This section provides adjustment procedure of FDD Unit and it includes the following.

1. Disk rotation period adjustment 2. Off track adjustment 3. Track 00 sensor position adjustment 4. Index timing adjustment

Note:Adjustment should be performed in the above order because the adjustments have an effect on the driver chracteristics.

Adjustment ~ools

Adjustment Disk Off track Track 00 Index Items rotation adjustment sensor timing

Required period position adjustment adjustment Tools adjustment

Exerciser 0 0 0 0 ------------------ r---------- r---------- 1----------- ----------OscillC!scope ___ 0 ___ - ___ D ____ ___ 0 ___ ------------------- ----------CE Disk 0 0 0 (Epson TC-301) ------------------

~~~Q~~~~ ----------

~~~Q~~~~ ----------

Normal Disk ------------------ ---------- ----------#1 Phillips 0 0 0 screwdriver ------------------ r---------- ---------- ---------- ----------#1 Flat 0 0 0 screwdriver ------------------ ---------- ---------- ---------- ----------Precision flat 0 0 screwdriver ------------------ ----------

~~~~O~~~~ ~~~Q~~~~ ~~~Q~~~~ Torque screwdriver ------------------ ----------Adhesive agent 0 (LOCTITE # 601)

4-48

Positions and Functions of Test Points

Eight test points are provided on the SMD-280 main board uni t for measuring the signal waveforms required for adjustment and inspection.

Figure 4-23 position of Test Points

The contents of Test Pin as Follows.

TP-l(TKO) .... Test point for measuring the track 00 sensor position, -the output level is Low and at track 1 or High at track 2.

TP-2(IDX)

TP-3(GND)

TP-4(AMP) TP-S(AMP)

Test point for measuring the index signal.

An OV (GND) analog signal line. A reference point for measur ing signal waveforms of TP-l, TP-2, TP-4, TP-S, TP-7, and TP-8.

Test point for measuring read amplifiertput output. Differential waveforms which are 180 out of phase appear at TP-4 and TP-S.

TP-6(GND) ...• OV (GND) analog signal line.

TP-7(DIF) TP-8(DIF)

A reference point for measuring the signal waveforms of TP-l, TP-2, TP-4, TP-S, TP-7, and TP-8.

Test point for measuring differential amplfier output. Differential waveforms which are 180 out of phase appear at TP-7 and TP-8.

4-49

Adjustment Procedures

1. Disk rotation Period Adjustment

Adjustment Procedure

a) Turn off the power. b) Connect the cable of an exerciser to the connecter PJ c) Turn on the power of spindle moter. d) Set the normal disk. e) Seek the head to track 40. f) Adjust VRl on the spindle motor unit and set the pulse

interval of the index output as follows: 200+0.6sec

4-50

Adjustment Procedures (Continued)

2. Off track Adjustment


a) Turn off the power. b) Connect the SMD-280 to the Exerciser and connect TP-l to

CH 1 of the oscilloscope, TP-2 to CH2, and the Exerciser index output terminal to the external trigger.

c) Set the measuring conditions of the oscilloscope as follows:

Channel CHl,CH2 AC-GND-DC AC VERT MODE ADD INVERT ON VOLTS/DIV 50 mV TIME/DIV 20 msec

d) Turn on the spindle motor and set the CE disk. e) Return the head to track 00. Next, move the head to track

40 using the STEP switch on the Exerciser. f) Observe the off track signal waveforms on the

oscilloscope. If the ratio between the right and left bUrst signal levels (small/large) is 0.8 or less, insert the Phillipes screwdriver into the screwdriver insertion holes on the main board unit and loosen the two stepping clamper mounting screws. 'Next, insert the stepping motor unit back and forth while turning the screwdriver. after adjusting the burst signal level ratio to 0.8 or more, tighten the stepping clamper mounting screws.

g) Apply the adhesive agent (LOCTITE *601) to the stepping clamper mounting screws.

4-51

Adjustment Procedure (Continued)

3. Index Timing Adjustment


a) Turn off the power. b) Connect the SMD-280 to the Exerciser. c) Turn on the spindle motor and set the CE disk. d) Return the head to track 00. Next move the head to track

40 using the STEP switch on the Exerciser. e) Using the Exerciser, check that the index burst timing in

the range 90-350 usec. If the timing in outside this range, adjust the index burst adjustment resistor (VRl).

4-52

Adjustment procedure (Continued)

4. Track 00 Sensor position Adjustment


a) Turn off the power. b) Connect the SMD-280 to the Exerciser. c) Check that the off track adjustment has been completed by

CE disk. d) Set the measuring conditions of the oscilloscope as

follows:

Channel CHI AC-GND-DC DC VERT-MODE CHI INVERT -VOLTS/DIV 1 V TIME/DIV 0.1 msec

e) Connect TP-l to CHI of the oscilloscope and short the terminal 1 and 4 of J4 by wire.

f) Turn on the power. g) Set the normal disk and turn on the Spindle motor.

Move the head carrige unit to the outermost track. h) Check whether the output at TP-l is 1 V or less at track

2 using the oscilloscope. i) Next, check whether the output at track 1. j) Whn the outputs are more than 1 V at track 2 and less

than 4 V at track 1, adjust them as follows. k) Insert the PhIlips screwdriver through the shield cover

or main board unit and loosen the track 00 sensor mounting screw.

1) Next, insert the flat screwdriver btween the main frame groove and track 00 sensor mounting board.

m) While observing the oscilloscope, rotate the flat screwdriver and adjust the output at TP-l until it is 1 V less at track 2 and 4 V or more at track 1.

n) Tighten the track 00 sensor mounting screw.

4-53

KEYBOARD

You have reached this TIP scince Keyboard is suspected of the cause of the failure. You need to prepare good key-switch and key cap remover for remove the key switch for maintenance. You need to prepare the good spare Keyboard Unit for replacement.


1. Character(s) are lost or changed incorrectly during key-in operation.

2. Excessive character(s) are transferred from the Keyboard to the System Unit.

Go to KEYBOARD-l for the symptom 1 and 2 of the above.

4-54

KEYBOARD-I

T&D Operation

1. Inser\. the MS-DOS system disk to the Int. FDD Unit of the System Unit.

2. Turn ON the power switch for the System Unit.

3. Execute the T&D program for keyboard in accordance with the T&D operation procedure of "PART 8".

KEyaOA~:J ~---I Co:: I IN i=ROGRt::SS 301000

ace cae cae ace c ~

ceo COO ~ cae 0 C = 0

a a c a 0 C ceo a ~ COO

= C 0 C cae C 0 C C C C C

c c c C c c C C C C cae c

c C C C ace c c C

IF TEST OK, PRESS CDELJ THEN CENTER) KEY

Does all input operation function correctly ?

Yes: Another unit is suspected.

No: Go to next page.

4-55

KEDOARD-l

T&D Operation (Continued)


1. All input operation do not function correctly:

Go to KEDOARD-2.

2. Specified input operation do not function correctly:

Refer to Key Matrix and key number (See next page ), then judge the Keyboard cable faulty or Key-switch faulty. If Keyboard cable faulty, go to KEYBOARD-3. If Key-switch faulty, go to KEYBOARD-4.

3. One or two input operation does not function correctly:

The Key-switch may be faulty. Go to KEYBORD-4.

4-56

KEYBORD-1

T&D Operation (Continued)

Table 4-1 Key Matrix

KBRTa 0 1 2 3 4 5 6 7

A 84 9 14 80 71 28 41 54 55 82 8 13 72 26 27 77 40 53 58 7 11 12 25 75 38 39 52 83 6 9 10 23 24 36 37 51 50

KBSCNb 5 7 8 21 22 35 48 49 57 4 5 6 19 20 33 34 47 46 3 3 4 17 18 31 32 44 45 2 1 2 15 16 30 29 42 43 1 60 70 62 73 64 66 68 56 0 59 69 61 81 63 65 67 79

IGJI~I~I@)I§)I@1I§JI§)I§)I@]I§)II§)I§)I§)I§)1 '------JJ G

57

Figure 4-24 Key Number

4-57

KEYBOARD-2

connector check


2. Disassemble the Upper Cover of the System upit. (Refer to PART 5)

3. Check that the keyboard cable (A) connect on the System PCB.

Figure 4-25 Connector check

Does the keyboard cable connect ?

Yes: Go to KEYBOARD-3.

No: Connect them, then repeat the operation to verify it. If the failure remains, go to KEYBOARD-3.

4-58

KEYBOARD-3

Connector check for damaqe

1. Check the Keyboard cable for damage with AVO meter.

o o .

Figure 4-26 Check for Damage

Is there any damage an the Keyboard cable ?

Yes: Replace the Keyboard cable, then repeat the T&D opresion to verify it. If the failure remains, go to KEYBOARD-5.

No: Go to KEYBOARD-S.

4-59

KBYBOARD-4

Key-switch replacement


2. Disassemble the Upper Cover of the System Unit. (Refer to PART 5)

3. Remove the Keyboard from the System Unit.

4. To replace a key cap, hold the cap with the attached key cap remover as in the bellow and pull it out right above. When fixing a key cap, push the key cap just a bit below.

5. Replace the Key-switch with good spare one.

Figure 4-27 Key Cap Remover


Yes: Go to KBYBORD-4.

No: Key-switch is faulty.

4-60

KEYBOARD-S

Keyboard replacement

1. Replace the Keyboard and Keyboard Cable with good spare ones. (Refer to PART 5)




Yes: The Keyboard is good. Another Unit may be suspected.

No: The Keyboard Unit is faulty.

4-61

LCD

You have reached this TIP since LCD Display is suspected of the cause of the failure.

The symptom may be one of the follows.

1. Neither of character nor graph appear on the LCD while the system is running.

2. Pictures on the LCD are distorted.

Go to LCD-l for the symptom 1 of the above.

Go to LCD-IS for the symptom 2 of the above.

4-62

LCD-I

Display check

1. Turn ON the power switch of the System Unit. /

2. Check that the disPla~ indicats all dots for' a second momentarily. ,

, /

, , , ,

--, ~ /

Figure 4-28 Display Check

Are the above all dots displayed ?

Yes: Go to LCD-4.

No: Go to LCD-2.

4-63

LCD-2

Opper/Lower half screen check

1. Check the LCD screen for whether a half of LCD screen is unable to display as shown in the figure 4-29.

Figure 4-29 Upper/Lower Hal Screen Check

Does above symptom appear ?

Yes: Go to LCD-IS.

No: Go to LCD-3.

4-64

LCD-3

Extra dots or missing dots check

1. Check the extra dots and missing dots on a cetain column.

Figure 4-30 Extra Dots or Missing Dots Check

Are there any extra or mdssing dots ?

Yes: Go to LCD-I7.

No: Go to LCD-IS.

4-65

LCD-4

Screen check at the start up time

1. After the display indicats all dot, confirm that the following message appeared on the screen.

MEMORY TEST XXX 1m

Does the above message appears ?

Yes: Go to LCD-S.

No: Go to LCD-IS.

4-66

LCD-S

Message check

1. After -MEMORY TEST XXX KB- message appears on the screen, confirm that the following message appears on the screen.

Place system disk in drive. Press any key when ready.


Yes: Go to LCD-6.

No: Go to LCD-IS.

4-67

LCD-6

Display Test Menu check

1. After the MS-DOS loading, run the Test & Diagnostic.

2. Press "4" then "Enter" keys for selecting the Display test of DIAGNOSTIC TEST MENU. (Refer to PART 8)

3. Confirm that the following Display Sub-test Menu appears on the screen.

DISPLAY TEST XXXXXXX




SUB-TEST MENU :

01 - VRAM readlwrite 02 - Character attributes D3 - Character set 04 - 80 * 25 Character display 05 - Graphics display (color set all) 06 - 640 * 200 Graphics display 07 - 640 * 400 Graphics display 08 - Display page 09 - UHU pattern display 99 - Exit to DIAGNOSTIC TEST MENU



Yes: Go to LCD-7.

No: Go to LCD-IS.

4-68

LCD-7

(01) VRAM read/write

1. Press 01 then keys on the Display test menu. The following message appears on the screen for very short time, then it returns to the Display Test Menu.

DISPLAY TEST

SUB-TEST XX PASS COUNT: XXXXX WRITE DATA: XX ADDRESS XXXXXX

XXXXXXX

ERROR COUNT: XXXXX READ DATA XX STATUS XXX

Does the error message appear ?

Yes: System PCB is faulty. Replace the System PCB (Refer to PART 5), then repeat the T&D operation to verify it.

No: Go to LCD-B.

4-69

LCD-8

(02) Character attributes

1. Press 02 then ENTER keys while the Display Test Menu appears. The following pattern appears on the screen. Note: The underline position of following screen display ,

·RRR ••••••• • to turn on and off.

2. Press ENTER key to return to the Display Test Menu.

NEXT LINE SHOWS REVERSE DISPLAY.

CHARACTER ATTRI8UTES

NEXT LINE SHOWS NORMAL DISPLAY. NNNNNNNNNNNNNNNNNNNNNNNNNNNNNN

NEXT LINE SHOWS INTENSIFIED DISPLAY. III 11111 I 11111 IlIIII II II I I II I I

NEXT LINE SHOWS REVERSE DISPLAY. RRRRRRRRRRRRRRRRRRRRRRRRRRRRRR

NEXT LINE SHOWS 9LINKING DISPLAY. 998898998888898988888888988888

PRESS CENTER] KEY

9LUE RED MAGENTA GREEN CYAN YELLOW WHITE

Is the above pattern displayed correctly

Yes: Go to LCD-9.

No: System PCB is faulty. Replace the System PCB (Refer to PART 5), then repeat the T&D operation to verify it.

4-70

LCD-9

(03) Character set

1. Press 03 then ENTER keys on the Display Test Menu, then the following pattern appears on the screen.


Is the above pattern displayed correctry ?

Yes: Go to LCD-IO.

No: System PCB is faulty. Replace the System PCB <Refer to PART 5), then repeat the T&D operation to verify it.

4-71

LCD-l 0

(04) 80 * 25 Character display

1. Press 04 then ENTER keys while the Display Test Menu appears. The following pattern appears on the screen.


80*25 CHARACTER OISPLAY 012345678901234567690123~ 676901234567890123456769 !»#$1.~'()*+,-./01234567· JXYZ(¥]A_ 'abcdetghijklmnc

!»#$1.~'()*+,-./01234567f XYZ(¥JA 'abcdetghijklmncp »#$1.~'()*+,-./012345676' (YZ(¥]A ~abcdetghijklmncpq #$7.~'()*+,-./0123456769 YZ(¥JA ~abcdetghijklmncpq~ $1.~'()*+,-./0123456789 Z(¥]A_~abcdetghijklmncpqrs 7.l'()*+,-./0123456769: :C¥JA 'abcdetghijklmncpq~st l'()*+,-./0123456769:j, ¥JA ~abcdetghijklmncpq~stu 1()*+,-./0123456769:j<= JA ~abcdetghijklmncpqrstuv ()*+,-./0123456769: j(=> \_~abcdetghijklmncpqrs~uvw )*+,-./0123456769:j(=>?a 'abc~etghijklmncpqrstuvwx *+,-./0123456769:j(=>?@A 9bcdetghijklmncpq~stuvWxy +.-.10123456769: i(=>?@ABt cdetghijklmncpqrstuvwxy% .-./0123456769: i(=>?@ABCO detghijklmncpq~stuvwxy%( -./0123456789: i(=>?@ABCOEI ~tghijklmncpq~stuvwxY%(1 ./0123456789: j(=>?@ABCOEF~ ghijklmncpq~stuvwxY%(I} /0123456789: j(=>?@ABCOEFGH hijklmncpq~stuvwxY%(I)-0123456769: i(=>?@ABCOEFGHI ijklmncpq~stuvwxY%(I)-A 123456769:j<=>?@ABCOEFGHIJ jklmncpq~stuvwxY%(I)-~g 23456769:j(=>?@ABCOEFGHIJI jklmncpq~stuvwxy%(I)-A~Q

PRESS (ENTER] KEY

Is the above pattern displayed correctly ?

Yes: Go to LCD-II.


4-72

LCD-II

(05) Graphics display (color set 0/1)

1. Press 05 then ENTER keys while the Display Test Menu appears. The following pattern appears on the screen. Note: Right most block is the brightest.


320*200 GRAPHICS DISPLAY

PRESS CENTERJ KEY


Yes: Go to LCD-12.


4-73

LCD-I 2

(06) 640 * 200 Graphics display

1. Press 06 then ENTER keys while the Display Test Menu appears. The following pattern appears on the screen. Note: Right most block (ALL DOTS DRIVEN) is the brightest.


040*200 GRAPHICS DISPLAY

EVEN DOTS ODD DOTS DRIVEN DRIVEN

PRESS CENTERJ KEY

ALL DOTS DRIVEN


Yes: Go to LCD-13.


4-74

LCD-13

(08) Display paqe

1. Press 08 then ENTER keys while the Display Test Menu appears. The following patturn appears on the screen. Note: The following screen change a page number (0 - 7).


OISPLAY PAGE 0

0000000000000000000000000000000000000000 o a o a o a o a a 0 a a a a o 0 o a o 0 a a o 0 a 0 a 0 o 0 o 0 a 0 o 0 a a OOOOOOOOOOOOOOOOOOpOOOOOOOOOOOOOOOOOOOOO


Yes: Go to LCD-14.


4-75

LCD-It

(09) -8- pattern display

1. Press 09 then ENTER keys while the Display Test Menu appears. The following pattern appears on the screen.


HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH


Yes: Go to LCD-IS.


4-76

LCD-IS

Connector Check


2. Remove the LCD from the LCD rear cover <Refer to PART 5), but the LCD cable. And put it on the Keyboard Unit.

3. Check the LCD connectors and cables are connected correctly & securely.


Are the connectors and cables connected correctly • securely ?

Yes: Go to LCD-16.

No: Connect it and repeat the T&D operation to verify it.

4-77

LCD-16

voltage check

1. Check the Power voltage at the LCD connector for the appropriate voltage with AVO meter.


Voltage Tolerance

Connector Pin Vo1taqe + Lead - Lead Noma1 Vdc Min Vdc Max Vdc

12 6,11,15 + 5 (L~i» + :¢:;::!" +~ J 2 9-.7 s:6

14 6,11,15 - 15 -~ - l:4=.=!'"" -IS ff' _ ;:..t.;>

Are the voltages in tolerance ?

Yes: Go to LCD-17.

No: Go to POWER.

4-78

LCD-I 7

LCD Replacement


2. Replace the suspected LCD with a good spare LCD.




Yes: The LCD is good. Another Unit may be suspected.

No: The LCD is faulty.

4-79

Ext. !'DD (5.25- EXternal Floppy Disk Drive)

You have reached this TIP since Ext. FDD (External FDD) is suspected of the cause of the failure. For the trouble shooting, you will need one good spare 5.25" Ext. FDD for the replacement.

External FDD is composed of following components. You will isolate the faulty component from them in this TIP.

External FDD components

* FDD assembly * FDD PCB (FDD5Cl) * Ni-Cd Battery unit * AC Adaptor * Ext. FDD Cable

You need to prepair the following tools for this TIP.

Tools

* AVO meter * MS·-DOS System. Disk (including T&D program file) * Work Disk (formatted) * Spair Ext. FDD unit and Ext. FDD Cable * Cleaning Disk (5.25") * Screwdriver (phillips screwdriver)

Start from Ext. !'DD-l for any trouble-shooting of Ext. FDD.

4-80

Ext. FDD-l

Set up for the FDD test

1. Connect the Ext. FDD cable to the TllOO PLUS System and the Ext. FDD.

2. Connect the AC adaptor to the Ext. FDD, and plug in AC plug of the AC adaptor to a wall-outlet.

3. Set the PRT/FDD select switch of the TllOO PLUS System to PRT pos i tion .

4. Insert the MS-DOS disk (including T&D program file) to the Int. FDD of the TllOO PLUS System.

5. Turn ON the power switches of the TllOO PLUS System and the Ext. FDD, then run the FDD test program according to the operation procedure of T&D (PART 8: TEST & DIAGNOSTICS).

Figure 4-33 Set the External FDD

Go to Ext. FDD-2.

4-81

Ext. FDD-2

FDD test menu

1. Proceed the T&D program to FDD test menu (FDD test menu is as follow).

2. Set the PRT/FDD select switch of the System Unit to "A" position.

3. Insert the good 5-inch work disk (error free) into the Ext. FDD.

4. Run all subtests of the FDD test program according to the T&D program operation procrdure. (refer to PART 8: TEST & DIAGNOSTICS) Following figure is an example screen of FDD Test program.

FLOPPY DISK 501000

SUB-TEST 01 PASS COUNT: 00000 WRITE DATA: 00

ERROR COUNT: OOOOD READ DATA I 00

ADDRESS 000000 STATUS 000

SUB-TEST MENU :

01 - Sequential read 02 - Sequential read/write 03 - Random address/data 04 - Write specified address 05 - Read specifi~d address 99 - Exit to DIAGNOSTIC TEST MENU

SELECT SUB-TEST NUMBER ? 01 TEST LOOP (1:YES/2:NO) ? 2 ERROR STOP (1:YES/2:NO) ? 1

Does any error message apperar?

Yes: Clean the Read/Write head of the Ext. FDD with cleaning disk. For head cleaning, insert a cleaning disk to the Ext. FDD then select "HEAD CLEANING" on a DIAGNOSTIC MENU of T&D program. (refer to PART 8: TEST & DIAGNOSTICS) If it leads you here again, go to Ext. FDD-3 .

No: The Ext. FDD is good.

4-82

Ext. PDD-3

Voltage check

Check the voltages of the Ext. FDD as following.

1. Turn OFF the power switches of the TllDD PLUS System Unit and Ext. FDD.

2. Open the upper cover of the Ext.. FDD. (Refer to PART 5: REPLACEMENT/ADJUSTMENT)

3. Turn ON the power switch of the Ext. FDD, then check the voltages for the FDD assembly by a AVO meter. (All check points are shown in the Tables on next page.)


To be continued.

4-83

Ext. FDD-3

voltage check (continued)

Voltage Tolerances

connector Pin Volta~e +Lead -Lead Normal Vdc Min Vdc Max Vdc

1 +12 +11.5 +14.5 Jl ------- 2,3 ----------- ----------- -----------

4 5 + 4.5 + 5.3

Are the voltages within the torelance.

Yes: Go to Ext. FDD-5

No: Go to Ext. FDD-4.

4-84

Ext. PDD-4

voltage check

If the voltages to FDD assembly are not in tolerance, one of the AC adaptor, FDD PCB or Ni-Cd battery is suspected. Check all of them by a AVO meter as follows.

Rote: Ni-Cd batter must be charged at least for an hour before the check.

1. Turn OFF the power switch of the Ext. FDD then pullout the DC plug of the AC adaptor from the Ext. FDD.

2. Check the voltage at the battery connector on the FDD PCB. (All check points are shown in the tables on next page.)

3. Check the output voltage of the AC adaptor at DC plug.


~-------+ 0 Ci)

:~--------~ rr AC Adaptor Figure 4-36 AC Adaptor

To be continued.

4-85

Ext. PDD-4

voltage check (continued)

voltage Tolerances

Output 0 f d Nl-C Batter 1

Connector Pin Voltage +Lead -Lead

PJ4 1,2 3,4 More than 12 Vdc

ott f AC d t u :pu 0 a ap' or Pin Vo1taqe

+Lead -lead Normal Vdc Min Vdc Max Vdc Inner Outer +20 +18 +22 Contact Contact

If output voltage of Ni-Cd battery is out of tolerance: ===> Change the battery.

If output voltage of AC adaptor is out of tolerance: ===> Change the AC adaptor.

If both output voltages of the battery & the AC adaptor are in the tolerance:

===> Change the FDD PCB.

4-86

Ext. PDD-S

Connector & jumper strap check

1. Check all connectors of the suspected FDD assembly whether they are connected properly and securely.

2. Check the jumper strap settings on the FDD assembly PCB.

c::J

·0 PJ6

•

On ~DJ o PJ7~

[f l' 'J' PJ8 I ::

~ PJ2 .~ ~ foJ4 I .,?-J ~I -)1'

Figure 4-37 Jumper of FDD PCB

Are the connectors and jumper straps set properly?

Yes: Go to Ext. PDD-6.

No: Set the connector or the jumper strap properly then repeat to run FOD test program to verify it. If it leads you here again, go to Ext. PDD-6.

.,1

4-87

Ext. PDD-6

POD cbange

1. Turn OFF the power switches of the Ext. FDD & the TllDD PLUS System Unit.

2. Change the FDD assembly with a good one for checking.

3. Run FDD test program for the Ext. FDD. If an error occurs again, the FDD PCB (FFDSCl) or Ext. FDD cable are suspected.

Figure 4-38 FDD Change

Does any error occurs?

Yes: Go to Ext. PDD-7.

No: The FDD assembly is faulty. Change the FDD assembly with spare one.

4-88

Ext. POD-7

FDD cable change

The FDD PCB and EXT. FDD cable are still suspected. In this entry, you will isolate the faulty component from them.

1. Turn OFF the power switches of the Ext. FDD and the TllOO PLUS System Unit.

2. Change the Ext. FDD cable with good one for checking.

3. Turn ON the power switches of the Ext. FDD and the TllOa PLUS System Unit then run the FDD test program for Ext. FDD.

External FDD Unit

FDD cable

Figure 4-39 FDD Cable Change


Yes: Go to Ext. POD-8.

No: The Ext. FDD cable is faulty. Change the Ext. FDD cable with spare one.

4-89

Ext. FDD-8

PDD PCB change

The FDD PCB is suspected. Change the FDD PCB (FFD5CI) refering to PART 5: REPLACEMENT /ADJUSTMENT.

1. Turn OFF the power switches of the Ext. FDD and the TIIOO PLUS System Unit.

2. Replace the Ext. FDD PCB then run FDD test program for the Ext. FDD.

Figure 4-40 FDD PCB Change


Yes: Ext. FDD UNIT is good. The System board of the TIIOO PLUS System Unit is suspected. Go to the TIP of System PCB.

No: The FDD PCB of the Ext. FDD is faulty. Change the FDD PCB.

4-90

5.1 DISASSEMBLING THE OPPER COVER OF THE SYSTEM UNIT


2. Turn the System Unit upside down, then remove the five screws (A) on the Lower Cover.

3. Turn the System Unit to normal position, then remove the three screws (B) on the rear panel of the System Unit.

(A)

Figure 5-1 Five Scres Removal

Figure 5-2 Three Screws removal

To be continued.

5-3

5.1 DISASSEMBLING THE OPPER COVER OF THE SYSTEM UNIT (Continued)

REMOVAL

4. Stand the Upper Cover (C) to left side of the System Unit as shown in the figure 5-3.

Figure 5-3 Disassemble the Upper Cover

REPLACEMENT

Follow the reverse procedure.

5-4

5.2 OPPER COVER REMOVAL/REPLACEMENT

REMOVAL


2. Disassemble the Upper Cover of the System Unit. (see section 5.1)

3. Lift up the Keyboard Unit, then put it in front of the System PCB (A).

4. Lift up the Indicator plate (B), then put it on the System PCB (A).

5. Disconnected the LCD cable (C) from the System PCB (A), then remove the one screw (D) from the System PCB (A) for disconnected the GND cable (E) of LCD Display to remove the Upper Cover (F).

Figure 5-4 Upper Cover Removal

REPLACEMENT


5-5

" .l I ""'" P c:..e-rI"'\ (~94 ~ . t""" ,..L

(t ,:, 'u ')

5 .3 KEYBOARD UNIT REMOVAL/REPLACEMENT

REMOVAL



3. Lift up the Keyboard Unit (A), then put it in front of the System PCB (B).

4. Pull the pressure plate (C) of connector (PJ 1), then pullout the keyboard cable (D) from the System PCB (B) to remove the Keyboard Unit (A).

Figure 5-5 Keyboard Unit Removal

REPLACEMENT


The Keyboard cable (Flat cable) is fixed to the Keyboard connector with pressure plate. To connect the Keyboard connector insert the cable into the connector then press the pressure plate securely.

5-6

5.4 IRDICATOR REMOVAL/REPLACEMENT

REMOVAL



3. Lift up the Keyboard Unit, then put it in front of the System PCB (A). (refer to figure 5-5)

4. Lift up the Indicator ~late (B), then disconnect the LED cable (C) from the System PCB (A) to remove it.

5. Remove the one screw (D) on the rear panel of the Indicator Plate (B) to remove the Indicator (E).

Figure 5-6 Indicator Plate Removal i (D)

(E)

Figure 5-7 Indicator Removal

REPLACEMENT


5-7

5.5 BATTERY PACKAGE AND POWER SUPPLY -PCB REMOVAL / REPLACEMENT

REMOVAL



3. Disconnect the three cables (A) from the Power Supply PCB (B).

4. Remove the Battery Package (C) on the FDD base (D).

5. Remove the two screws (E) on the rear panel of the System Unit to remove the- filler panel (F).

6. Remove the three screws (G) on the Power Supply PCB (B), then remove the metal plate (I) to remove the Power Supply PCB.

( A)

(G)

L.---- (F)

~----(B)

2L~_-~(C)

Figure 5-8 Battery Package and Power Supply PCB Removal

RPLACEMENT


5-8

5 .6 FLOPPY DISK DRIVE BASE REMOVAL/REPLACEMENT

REMOVAL



3. Remove the Keyboard Unit and Indicater Plate from the System PCB. (see section 5.3, 5.4)

4. Disconnected the FDD cable(s) (A) from the System PCB (B).

5. Remove the four screws (C)(O) on the FDD base (E) to remove the FDD baes (E).

Figure 5-9 FDD Base Removal

REPLACEMENT

Follow the reverse procedure. Screws (D) is short screw.

5-9

5.7 FLOPPY DISK DRIVE REMOVAL/REPLACEMENT

REMOVAL



3. Remove the Keyboard Unit, Indicator plate and FDD base from the System Unit. (see section 5.3, 5.4, 5.6)

In the case of the F type

4. Remove the four screws (A)(B) on the FDD base (C), then remove the metal plate (D) and Floppy Disk Drive (E).

5. Push the both side nales of the filler panel (F), then remove it.

Figure 5-10 Floppy Disk Drive Removal (F type)

REPLACEMENT

Follow the reverse procedure. Screws (A) is flat head screws.

To be continued.

5-10

5.7 FLOPPY DISK DRIVE REMOVAL/REPLACEMENT (Continued)

REMOVAL

In the case of the F/F type

4. Remove the eight screws (G)(H) on the FDD base, then remove the mo+- .. 1 r'l1 .. +-0 tT' .. n~ hn+-+-nm lO'1nr'lr'lu n;col,' n,..;uo t,,.,

5. Pass the FDD cable through a slit of the FDD base to remove the top Floppy Disk Drive (K).

_""""" ..... (G)

Figure 5-11 Floppy Disk Drive Removal (F/F type)

REPLACEMENT

Follow the reverse procedure. Screws (G) is flat head screw.

5-11

5.8 PDD BEZEL REMOVAL/REPLACEMENT

REMOVAL


2. Remove the Upper Cover, Keyboard Unit, Indica tor plate, FDD base and FDD. (see section 5.2, 5.3, 5.4 5.6, 5.7)

3. Spread the four nailes (A) with the blade scrwdriver to remove the FDD cover as shown in the figure 5-12.

4. Remove the two screws FDD bezel (D).

on the FDD device (C) to remove the

Figure 5-12 Spreading

Figure 5-13 FDD Bezel Removal

REPLACEMENT


5-12

5. 9 SYSTEM PCB REMOVAL/REPLACEMENT

REMOVAL


2. Remove the Upper Cover, Keyboard Unit, indicator plate and FDD base (see section 5.2, 5.3, 5.4, 5.6)

3. Remove the Expansion slot PCB (A) from the System PCB (B).

4. Disconnected the Speaker cable (C) from the System PCB (B).

5. Remove the three screws (D) on the System PCB (B) to remove the System PCB (B).

Figure 5-14 System PCB Rempval

REPLACEMENT


5-13

5 .10 SPEAKER AND INSULATER REMOVAL/REPLACEMENT

REMOVAL


2. Remove the Upper Cover, base and System PCB.

Keyboard Unit, Indicator plate, FDD (see section 5.2, 5.3, 5.4, 5.6, 5.9)

3. The speaker (A) is moun ted on the Lower Cover (B) with a locking lever (C). Push the locking lever (C) outward so that the speaker is free to move, then pullout the speaker (A) from the Lower Cover (B).

4. Peel the Insulater (D) to remove it.

Figure 5-15 Speaker and Insulater Removal

REPLACEMENT


5-14

5 .11 LCD MASK REMOVAL/REPLACEMENT

REMOVAL


2. Replace the latches (A) by sliding them forward hold the latches and pull up the display, then open the LCD as shown in the figure 5-16.

3. Peel the seal (B) from LCD (C) with a pear of tweezers and remove it.

Figure 5-16 Opening the LCD

(B)

Figure 5-17 Peeling the Seal

To be continued.

5-15

5.11 LCD MASK REMOVAL/REPLACEMENT (Continued)

REMOVAL

4. Remove the one screw (D) from the LCD Mask (E), then slide the LCD Mask (E) to the forward position a little to remove it.

Figure 5-18 LCD Mask Removal

REPLACEMENT


5-16

5 .12 LCD REMOVAL/REPLACEMENT

REMOVAL


2. Remove the LCD Mask from the System unit. (see section 5.11)

3. Remove the four screws (A) on the LCD (B).

4. Lift up the LCD (B), then put it on the Keyboard Unit.

5. Disconnect the LCD the LCD (B).

rear of the LCD to remove

Figure 5-19 Four Screws Removal

(B)

Figure 5-20 LCD Removal

REPLACEMENT


5-17

5 .13 LCD REAR COVER REMOVAL/REPLACEMENT

REMOVAL


2. Remove the LCD Mask and LCD. (see section 5.11, 5.12)

3 . Peel the seal (A) with a pair of twee zers from the hinge (B), then remove it.

4. Peel the LCD GND cable (C) from the LCD rear cover (D).

5. Remove the two screws (E) on the hinge (B).

Figure 5-21 Peeling the Seal

(D)

Figure 5-22 Two Mounting Screws Removal

To be continued.

5-18

5.13 LCD REAR COVER REMOVAL/REPLACEMENT (Continued)

REMOVAL

5. Turn the LCD rear cover down, then remove the hinge (E) from the Upper Cover (F).

6. Pullout the torsion bar (G) from hole of the Upper Cover (H).

7. Remove the LCD rear cover (I) to forward position.

Figure 5-23 LCD Rear Cover Removal

REPLACEMENT

FollOw the reverse procedure.

5-19

5.14 MEMORY CARD REMOVAL/REPLACEMENT (Option)

REMOVAL



3. Lift up the Keyboard Unit and Indicator plate, put it front of the System PCB (A) as shown in the figure 5-24.

4. Pullout the Memory Card (B) from the System PCB (A).

5. If the memory size of the TllOO PLUS System have been changed you must change the setting of configuration DIP switch (C).

(Refer to page 1-10)

Figure 5-24 Memory Card Removal

REPLACEMENT


5-20

5.15 MODEM CARD AND I/O EXPANSION CARD REMOVAL/REPLACEMENT (Option)

REMOVAL


2. Remove the two screws (A) fixing the Modem Card (B).

3. Hook the card puller (C) into the holes (D).

4. Hold the card puller (C) and gently slide out the card.

6--_--( A)

Figure 5-25 Two Screws Removal

(C)----~========~ (0 )

Figure 5-26 Modem Card or I/O Expansion Card Removal

REPLACEMENT


5-21

5.16 5.25- EXTERNAL PDD DISASSEMBLE/ASSEMBLE (option) Upper Cover Removal/Replaceme~t

REMOVAL

1. Turn OFF the power switch of the Ext. FDD (External FDD) and the System Unit then remove the Ext. FDD cable from the rear of the Ext. FDD Unit.

2. Remove four screws (A) from the Ext. FDD.

3. Slide the Upper Cover (B) backward to remove it.

(B)

Figure 5-27 Upper Cover Removal

REPLACEMENT


5-22

5.16 5.25- EXTERNAL POD DISASSEMBLE/ASSEMBLE (Continued) FDD Assembly ( and Front Panel) Removal/Replacement

REMOVAL

1. Remove three screws (A) of the FDD assembly.

2. Disconnect the signal cable connector J2 (B) and power cable connector Jl (C) on the FDD assembly.

3. Slide the FDD assembly forward to remove it.

4. The FDD assembly has a. front panel (D) which is mounted to the FDD assembly by two screws (E). Remove the two screws (E) to remove the front panel if need.

(e) (B)

Figure 5-28 FDD Assembly Removal

REPLACEMENT


5-23

5.16 5.25- EXTERNAL POD DISASSEMBLE/ASSEMBLE (Continued) FDD PCB (FFD5C1) Removal/Replacement

REMOVAL

1. Disconnect the battery connector PJ4 (A) on the FDD PCB.

2. The FDD PCB (B) is mounted on the lower cover with a nylon latch (C) and a slot (D). Nip head of the nylon latch on the PCB by a longnose plier to be free then lift the PCB up by getting it out of the slit.


REPLACEMENT


5-24

5.16 5.25- EXTERNAL FDD DISASSEMBLE/ASSEMBLE (Continued) Battery Removal/Replacement

REMOVAL

The battery stock room is there under the FOD assembly .. Before removing the battery, you have to remove the FOO assembly and disconnect the battery connector PJ4 on the FDD PCB.

1. Remove the battery cover screw (A).

2. Slide the battery cover (B) backward one inch to unhoock then lift up the battery cover. You can access the battery.

(B)

~(A)

i~

Figure 5-30 Battery Removal

REPLACEMENT


5-25

PART 6 LOCATION

CONTENTS

SYSTEM UNIT

Front View

Rear Panel

KEYBOARD

U.S.A. Version

U.K. Version

German Version

French Version

Spanish Version

Italian Version

Scandinavia Version

(GO=: TA.sa;de 'l'aMe

SYSTEM PCB ...... .

FLOPPY DISK DRIVE

Top View

Bottom View

FDD PCB

CORRECTOR

..........................................

System Unit Rear Panel

6-1

6-2

6-2

6-3

6-4

6-4

6-5

6-6

6-7

6-8

6-9

6-10

6-11

6-12

6-14

6-14

6-15

6-16

6-17

6-17

SYSTEM UNIT (Pront View)

(A) System PCB

(B) Memory Card (Option)

(C) 3.5" Floppy Disk Drive

(0 )

(E)

( F)

(G)

(H)

( I)

F type One Floppy Disk Drive F/F type ... Two Floppy Disk Drive

Keyboard

Power Supply Unit

Speaker

LCD Display

Upper Cover

Lower Cover

(C)

Figure 6-1 Front View of System Unit

6-2

SYSTEM UNIT (Rear Panel)

( A) Power Switch

(B) DC Jack

(C) Display Connector (for Color Display)

(D) Display Connector (for Monochrome Display)

(E) Printer or Expansion FDD Connector

(F) RS232C Cable Connector

(G) Modem Card or Interface Card Slot

(H) Printer / FDD Select Switch

(I) LCD Contrast Volume

Figure 6-2 Rear Panel of System Unit

6-3

KEYBOARD (U.S .A. Version)

jij] ,.. .. ."at lIJ UJ rIJ I!J OJ (B ct

OOJ o U I! ~j

l~" TIl j!J L!J It) m W ~

liJ til I

rn r~ liJ ill

G ~- l~ B l ..

rn UJ 8 .. c ""

l+:J '---

t:J m B ~:J l8 8 lD 8 1

t~r B A-

I~~ [:J 8 oJ"

B 8~ _en

Et ~-

8 ~ E~r *(1) 8-~. If%] B~ TrJ car--

EJ ~ [<3 EJ 8 Q j~:] ~ G B B EJ G '-

fXl t8 (:3 B 0 8 19 Till IB Au

G lJ!S

ill 'Q EJ ~ ~

Figure 6-3 U.S.A. Version

6-4

KEYBOARD (U .K. Version)

l1J lIJ W l!J to

j1J m LL

m on m l!J fEJ til m T~ 8 ill

G ~- G B 1

rn m .B I III

l+UJ ~

~ m B ~:J l8 8 LD 8 1 8-B A-

Ij:J" ~ 8 EJ B~ _en j~N lO-

G @ Er *(1) Gl ~. 'GJ 8~ T~ cD"'"

EJ ~ [<3 EJ 8 l~ j~3 EJ G 8 B ~ G GJ '---

8 B B 8 B B j_a) B AU

DD

G U-I

ill Q B [n liJ Figure 6-4 U.K. Version

6-5

KEYBOARD (German Version)

l~l

ffJ

·m j~

j21l-----I

T~ 1m ill

Figure 6-5 German Version

6-6

KEYBOARD (Prench Version)

jill .... 11111:

jIJ ... j!J

l!J r~ l!J ~

rn LL.

m :

j~

T~ l~ ill

Figure 6-6 French Version

6-7

KEYBOARD (Spanish Version)

lJJ 1ft

W iliJ LD fIl .5

jIJ r¥J

l!J on

r~ r!J r~ til j~ jF) l~ liJ

G ~- G 8 l

rn tTI [3 ~ c: III

'---

f+UJ [3 m n it] tB - E+ tD 8 1

~. 8 8 rtJ j~\O [j 8 8 to-n l~ 18 l~T ~. If%] jdS!j If%] 8 ~ rt9 8 8 l~ j~3 GJ G 8 GJ ~ -~

G l~ ~

18 B B 0 en.

G a Ifill l~ AU

G B~

ill t1 'GJ @ w Figure 6-7 Spanish Version

6-8

KEYBOARD (Italian Version)

19) ... .,. ,.... ilia::

jID r¥J

l!J on

rt]

l!l r~ m jr]

T~ 8 ill

Figure 6-8 Italian Version

6-9

LBOARD (Scandinavian Version)

ru ,.., m liJ LD fIl ~

CD

rIJ l¥J

C!J ~ 1/'1

@

W ~

reJ

m m T~ 8 ill

Q ~- G L=J l ..

rn UJ ~1 .. c 1&1

n '----t1 CD IS] - ~

rt:31 - If 1 IL O!~ ttJ I' 8 1 1~ -r --[J: ~---8

... " rtl jOJ~ n /-

B ,8 ~-

8 -It} a 8 @~ If%] 0: IjrJ

G ~ ~< Er 8 l~ jij 8 8 8 8 8 G '[Xl '---

fw;l B G 8 - 18 ff=:l~ Till G

.... a.u

G 00 U~ -

ill Q B ~ m 1!J ¢

Figure 6-9 Scandinavian Version

6-10

CODE TABLE (Display)

Table 6-1 Code Table

== 0 I 2 3 4 5 6 7 8 9 A B C D E F

0 ~ ~ 0 @ p , p y E , '" I ex ~ a -

I ~ ... I 1 A Q a q U , I {3 + Ee I T

2 • 1 II 2 B R b ,

A:: , r > r e 0 II -

3 • " # 3 C S " /\ , LL TT < C 5 a 0 U r-.. 4 + err $ 4 D T d t Ci 0

,.., - - b L r n 5 + S 0/0 5 E U e u

, a

, N = 0 - I-- F (J J 6 + -& 6 F V f Cl " a F ,......u · v U -1 · 7 • f

, 7 G W 9 w ~

, 0 T ---u ill ,..... ±;-r ( 8 H X h x " y .

F= 2 0 e (,

9 0 1 ) 9 I Y i Y e 6 r F= II e • -

A - * • J Z j z " U -, W1= n • e • -

{ B (j + • K [ k ¢ '12 n1 = 6 ....,-- , I

C 9 L < L " I I /\ £ 1.11 WJ 00 n , I I

D } M ] } " % . --.II cfJ 2 - - - m I I

E ~ • • > N /\ n 'V A Pt 9 d ~ E • F ¢ / ? 0

0 n I~ • 0 6- A f » h · -

6-11

SYSTEM PCB

(J) (K) ( L) ( M)

--'. aDD •

; o· 0; ~ -. ~

o (N)

RJ16i •

1;]- 0 ',., . 8 ... • • ... (U)(T) (S) ( R~'

Figure 6-10 System PCB

6-12

SYSTEM PCB (Continued)

(A) Keyboard Connector

(B) Configuration DIP Switch

(C) Expansion Bus Connector

(D) CPU

(E) LCD Contrast Volume

(F) Printer/FDD Select Switch

(G) Power Supply Connector 2

(H) Ni-Cd Battery

(I) Power Supply Connector 1

(J) Composit Video Connector

(K) Color CRT Display Connector

(L) External FDD and Printer Connector

(M) RS232C Connector

(N) FDD 1 Connector

(0) FDD 2 Connector

(P) Expansion Memory Connector

(Q) Indicator Connector

(R) Memory Chips (256 KB)

(S) ROM (BIOS)

(T) Speaker Connector

(U) LCD Connector

6-13

FLOPPY DISK DRIVE (FDD) (Top View of mechanical assembly)

(A) Head Assembly

(B) Stepping Motor

(C) Track 00 sensor

(A)

(B)

Figure 6-11 Top View of Mechanical Assembly

6-14

FLOPPY DISK DRIVE (FDD) (Bottom View)

(A) Drive Motor

( A)

Figure 6-12 Bottom View of FDD

6-15

PLOPPY DISK DRIVE (POD) (POD PCB)

( A) PJ 2

(B) PJ 3

(C) PJ 4

(0 ) PJ 5

(E) PJ 6

(F) PJ 7

Interface and power connector

Sensor connector

Sensor connector

Step motor

Read/Write

Read/Write

(0 )

(C)

connector

head 0 connector

head 1 connector

o

~-"-t.I!!I--(B)

\\11111

Figure 6-13 FOO PCB

6-16

CONNECTOR (System Unit Rear Panel)

"I 5 1 \

II \0 0 0 0 0 J ) \ 0 0 0 0

~~J 13

Figure 6-14 System Unit Rear Panel

Pin No. Signal Pin No. Signal Pin No. Signal

PJ 13 PJ 14 1 GNO 1 STROBO 21 GNO 2 GNO 2 POOl 22 GNO 3 CRVI 3 POll 23 GNO 4 CGVl 4 P02l 24 GNO 5 CBVI 5 P031 25 GNO 6 CIVI 6 P04l 7 NC 7 P05l 8 CHSYI 8 P061 9 CVSYI 9 P071

10 ACKO 11 BUSYI PJ 15 12 PEl 1 OSOI 13 SELECI 2 ROO 14 AUTFOO 3 SOO

PJ 12 15 ERROR 0 4 OTRI 1 P26CP 16 PINTO 5 GNO 2 GNO 17 SLINO 6 OSRI

18 GNO 7 RTSI 19 GNO 8 CTSI 20 GNO 9 RTI

6-17

PART 7 REPLACEMENT PARTS CATALOG

The followings are parts catalogs in accordance with a Field Replaceable unit (FRU) maintenance philosophy.

7.1 System Unit •.•.••••••••••••••..••.•.•..•......•..•.. 7-2

7.2 AC Adaptor •••.•....••••••••••••••...•....•...•...... 7-4

7.3 5.25 n External FDD •..••••••••.••••••...••.....•..... 7-5

7-1

Unit 7.1 System

TIIOOPLUS System

7-2

7.1 System unit (Continued)

INDEX PART NUMBER DESCRIPTION ROTE No.

1 47TlO8477Pl LCD Mask

2 VFOO14P03 LCD (Liquid Crystal Display)

3 ULOO65P03 LCD Harness

4 47M140393Gl LCD Cover Sub Assy

5 47P127400pl Hinge

6 47M140394Gl Upper Caver Sub Assy

7 47K154048p5 Seal 1

8 47K156063Pl Seal 2

9 34M741476GOI Power Supply PCB FPLPSI

10 XZOO75P02 Battery Package

11 ZA0652POI 3.5" FDD (Floppy Disk Drive)

_ 12 47M140552Gl FDD Bezel

13 47TlO8478Pl FDD Base

14 34M74l48lGOl Expansion Slot PCB FPLBPI

15 34M74l486GOl Indicator (LED) PCB FPLEDI

16 UE0182pll Keyboard (TEG, TIU) UE0182P12 Keyboard (TAl, TAP)

17 34T77996lGOl System Board

18 39K156042Gl Speaker with Harness

19 47M140395Gl Lower Cover Sub Assy

7-3

7.2 AC Adaptor

INDEX PART NUMBER DESCRIPTIQiI ROTE No.

I UA0266pOI AC Adaptor TAI Version UA0266p02 AC Adaptor TAP Version

~~-~--------~l

AC Adaptor

7-4

7.3 5.25- External POD

Figure 7-3 5.25" External FDD

7-5

7.3 5.25· External!'DD (COIltiuned)

INDEX PART NUMBER DESCRIPTION ROTE Ro.

I 47Pl27086PI Upper Cover

2 47Pl27085PI Lower Cover

3 34P71024lGOI PCB

4 47Ml37924PI Battery Cover

5 XZOO67POI Battery

6 47Pl27089PI Front Panel

7 ZAOl62POI 5.25 inch FDD

8 ULOO34P23 FDD PS Cable

9 ULOO46Pl3DDOO4 Cable

7-6

8.1 INTRODUCTION

8.1.1 General

The purpose of this TIIOO PLUS Test and Diagnostics is to check the functions of all hardware modules of the TIIOO PLUS Personal Computer.

This TIIOO PLUS Test and Diagnostics is structured under the MS-DOS, and consists of 17 programs covering all of the hardware modules supported in TIIOO PLUS Personal Computer system as described in STRUCTURE section.

The CE Diagnostic Test Program is provided as a file in the MS-DOS System Disk. You have to run the MS-DOS before you load the CE Diagnostic Test Program.

The service engineer utilize these programs to isolate the trouble by selecting the appropriate program by the operation procedure described in OPERATION section.

8-3

8.1.2 Components Required

The following devices are required to execute the test program system .

CPU

DSP/KB r---........ _--*

Device to be tested

Where:

CPU Central Processer Unit

RAM Random Access Memory ; 256KB

ROM Read Only Memory; 32KB

DSP LCD Unit

KB Keyboard

FDD Floppy Disk Drive ;720KB

* Devices to be tested

RAM Random Access Memory

ROM Read Only Memory

KB Keyboard

DSP LCD Unit

FDD Floppy Disk Drive (720KB/360KB)

PRT Printer Device or Wraparound connector

RSC Communications controller + Wraparound connector card, Modem

HDD Hard Disk Drive

RTM Real Timer

NDP High speed numeric processor

8-4

8.1.3 Structure

The TllOO PLUS test program system is composed of 17 program modules executed under the Test Monitor.

The 17 program modules can be divided into two groups, the Service Program modules (HDD format, Landing zone seek, Head cleaning, Log utility, Running test, FDD utili ties, and System configuration) and the Test Program modules (all other modules). Those are shown in the figure on next page.

Each of the Test Program modules contains some number of subtest programs which are shown in the ANNEX A: Test Program List.

Don't execute NDP Test. If you execute NDP Test, error status is displayed on the screen .

8-5

TEST PROGRAM STRUCTURE

SERVICE PROGRAM MODULES TEST PROGRAM MODULES

rl DIAGNOSTIC TEST J SYSTEM TEST I L

H HDD DISK FORMAT J MEMORY TEST I L MS-

I I DOS ~ SEEK TO LANDING I

KEYBOARD TEST ZONE (HDD)

J DISPLAY TEST I H 1 HEAD CLEANING

J FLOPPY DISK TEST I H L LOG UTILITIES TEST

J 1 MONITOR~

H I PRINTER TEST RUNNING TEST

J ASYNC TEST I H L FDD UTILITIES

J HARD DISK TEST I L ~ SYSTEM CONFIGURATION

J 1 I REAL TIME TEST

I EXIT TO MS-DOS I I L NDP TEST

8-6

8.2 OPERATION

This section describes how to operate the TllOO PLUS Test and Diagnostics such as CE Diagnostic Test Program These Diagnostic Test Programs are provided in the MS-DOS System Disk. You have to run the MS-DOS before you load the CE Diagnostic Test Program.

8.2.1 CE DIAGNOSTIC

(1) Test program loading

Insert the MS-DOS disk to the internal disk drive, then turn ON the power of the TllOO PLUS. The MS-DOS is loaded after Power On Self-test execution. After the loading, following messages appear on the screen. And press the "ENTER" Key twice, and then file name of CE Diagnostic as testce to load the diagnostic program. If Current date and Current time is mistake, input the Enter new date and Enter new time then file name of Diagnostic as testce to load the diagnostic program.


Cop~ri9ht 1984,86 Toshiba Corporation

MS-DOS Ver 2.11 Cop~ri9ht 1983,84 Microsoft Corp.

Command Ver 2.11V Current date is Wed 1-01-1986 Enter nelll date : Current time is 0:36:46.00 Enter nelll time:

A>testce

Prel iminar~ version

The underlined portion on the above screen is for the input message. After the above operation, the test program loading is complete.

8-7

(2)Module selection

The following screen (Diagnostic Menu) is displayed after the test program loading.

Tne TOSHIBA personal computer DIAGNOSTICS version 0.12 (c) cOpyri9ht TOSHIBA Corp 1986

DIAGNOSTICS MENU :

1 - DIAGNOSTIC TEST 2 - HARD DISK FORMAT 3 - SEEK TO LANDING ZONE (HOD) 4 - HEAD CLEANING 5 - LOG UTILITiES 6 - RUNNING TEST 7 - FDD UTILITIES 8 - SYSTEM CONFIGURATION 9 - EXIT TO MS-DOS

PRESS (1)-[9) KEY

Input a module number and then press the "ENTER" key to select the module on DIAGNOSTIC MENU. When you input;

1 Displays the Diagnostic Test Menu. See page 8-10. (includes pressing "ENTER" key only)

2 Executes the Hard Disk Format. See page 8-35.

3 Seeks the head of HDD to Landing Zone. See page 8-37.

4 Cleans the head of FDD. See page 8-38.

5 Displays the error logs. See page 8-39.

6 Executes the running test. See page 8-41.

7 Executes the format, copy and dump of FDD. See page 8-42.

8 Displays the system configuration. See page 8-43.

9 Returns to MS-DOS

If you input the except above module number, the screen return to the Diagnostic Menu. <above screen)

8-8

(3) Displaying of system configuration

After press "8" and "ENTER" keys of DIAGNOSTIC MENU, the following system configuration is displayed on the LCD Unit/CRT Display Unit.

SYSTEM CONFIGURATION

* - 640KB MEMORY

* - LCD DISPLAY

* - 2 FLOPPY DISK DRIVE(S)

* - 1 ASYNC ADAPTER

* - 0 HARD DISK DRIVE(S)

* - 1 PRINTER ADAPTER

* - 0 MATH CO-PROCESSOR

PRESS CENTER) KEY

Abo~e message is an example of F/F type System .

Compare your System Unit and System Configuration of above message, and then if it is good, press the "ENTER" key. If it is no good, turn OFF the power switch of the System Unit, and then check the configuration DIP switch. (Refer to page 1-10) Repeat the operation from step (1) after correcting them.

8-9

(4) Test selection

After press "1" and "ENTER" keys of DIAGNOSTIC MENU, the following screen appears on the LCD Unit/CRT Display Unit.


DIAGNOSTIC TEST MENU

1 - SYSTEM TEST 2 - MEMORY TEST 3 - KEYBOARD TEST 4 - DISPLAY TEST 5 - FLOPPY DISK TEST 6 - PRINTER TEST 7 - ASYNC TEST 8 - HARD DISK TEST 9 - REAL TIMER TEST

10 - NDP TEST 88 - FDD & HOD ERROR RETRY COUNT SET 99 - EXIT TO DIAGNOSTICS MENU

PRESS COJ-C9J KEY

Input the test number I and then press the "ENTER" key to execute the DIAGNOSTIC TEST MENU.

If you input the above test number (1 - 10), System Unit execute the each test.

If you input the above test number (88), You can set the error retry count of the FDD and HOD.

If you input the above test number (99), the Screen return to the DIAGNOSTIC MENU. (Refer to page 8-8.)

If you input except above test number, the screen return to the Diagnostic Test Menu. (above screen)

8-10

(5) Subtest and test mode selection

The subtest menu screen (the following sample is for FDD) is displayed after selecting any test (1-7) at test selection, so input two digit subtest number.

(Refer to ANNEX A: Test Program List)

FLOPPY DISK 501000 I'

SUB-TEST 01 PASS COUNT: 00000 WRITE DATA: 00

ERROR COUNT: 00000 READ DATA 00

ADDRESS 000000 STATUS 000

SUB-TEST MENU :

01 - Sequential read 02 - Sequential read/write 03 - Random address/data 04 - Write specitied address 05 - Read specified address 99 - Exit to DIAGNOSTIC TEST MENU

SELECT SUB-TEST NUMBER ? 01 TEST LOOP (1:YES/2:NQ) ? 2 ERROR STOP (1:YES/2:NO) ? 1

where,

TSSDSS

~ Status Device number Subtest number Test number

Note 1 Subtest number

(Refer

(Refer (Refer

to

to to

ANNEX C

ANNEX A )

ANNEX· A )

Select a subtest by typing two-digit number. The input number "99" make the control return to Diagnostic Test Menu.

8-11

Note 2 Test mode selection

The test program execution mode can be specified as follows after the test ends or when an error occurs.

TEST LOOP (1:YES/2:NO) ?

1 At each time a test cycle ends, it increments the pass counter by one and repeats the test cycle. (If you press "RETURN" key, it is assumed to be TEST LOOP l:YES.)

2 At the end of test cycle, it terminates the test execution and exits to the subtest selection menu.

ERROR STOP (1:YES/2:NO) ?

1

2

Note

When an error at column 7 execution of displays on follows .

occurs, it displays the error status (Refer to ANNEX C ) and stops the test program. The operation guide the right side of the screen as

«HALT OPERATION» 1 Test End 2 Continue 3 Retry

Input "I" key

Input "2" key Input "3" key

It terminates the test program execution and exits to the subtest selection menu. It ·continues the test. It retrys the test.

When an error occurs, it displays the error status, then it increments the error counter by one and goes to the next test step.

The Running test will neglect the "TEST LOOP (N)", and "ERROR STOP (Y)". If you stop the Running test, press "Ctrl" + "Break" keys. The screen return to the DIAGNOSTIC MENU.

(6) Termination

When it is needed to terminate the test program execution, press the -Ctrl- + -Break- keys. The screen return to the DIAGNOSTIC MENU.

8-12

8.3 SYSTEM TEST

Summary of the System Test

This program performs the checksum test of the ROM on the Systems PCB. (Test limits : F8000H - FFFFFH, 32KB)

Subtest and test mode selection

After pressing "1" and "ENTER" keys at test selection of DIAGNOSTIC TEST MENU, the following screen appears for subtest and test mode selection.

SYSTEM TEST


SUB-TEST MENU :

01 - ROM checksum

xxxxxxx


02 - Secound ROM check Sum -99 - Exit to DIAGNOSTIC TEST MENU


Select desired subtest by pressing two digits subtest number in SUBTEST MENU as shown above and "ENTER". Then select the test mode by pressing "l:YES" or "2:NO" and "ENTER" keys for TEST LOOP and ERROR STOP question respectively.

The selected subtest starts and test information such as SOBTEST Bo., PASS COUNT, ERROR COUNT, WRITE DATA, READ DATA, ADDRESS , and STATUS are displayed and updated during execution as shown above.

8-13

8.4 MEMORY TEST

Summary of the Memory Test

This test performs the memory read/write test with constant data (Five patterns) and address pattern data and also memory refresh test for RAM.


After pressing "2" and "ENTER" keys at test selection on the DIAGNOSTIC TEST MENU, the following screen appears for subtest and test mode selection.

MEMORY TEST XXXXXXX




SUB-TEST MENU :

01 - RAM constant data 02 - RAM address pattern data 03 - RAM refresh 99 - Exit to DIAGNOSTIC TEST MENU


Select desired subtest by pressing two digits subtest number in SUBTEST MENU as shown above and "ENTER" key. Then select the test mode by pressing "l:YES" or "2:NO" and "ENTER" for TEST LOOP and ERROR STOP question respectively.

The selected subtest starts and test information such as SUBTEST Ro., PASS COUNT, ERROR COUNT, WRITE DATA, READ DATA, ADDRESS, and STATUS are displayed and updated during execution as shown above.

Refer the following page for subtest description. Refer to the ANNEX C for error status code.

8-14

Subtest description

(Test limits : OH - Max size)

Subtest 01 Constant data read/write test

Writes constant data to Memory, and then reads and compares it with the original data. The constant data are "FFFFH", "AAAAH", "5555H", "OlOlH" and "OOOOH".

Subtest 02 Address pattern data read/write test

Makes the segment address and offset address by XORing, and then writes the address pattern data it and reads and compares them wi th a or ig inal data.

Subtest 03 Memory refresh test

Writes constant data in 256 byte length to Memory, and then reads and compares it with the original data. The constant data are "AAAAH" and "5555H".

A certain interval time will be taken between the write and the read operations.

8-15

8.5 KEYBOARD TEST

Summary of the Keyboard Test

This test performs the function test of keyboard by pressing all the keys according to the keyboard pattern on the screen.



KEYBOARD TEST


SUB-TEST MENU :

XXXXXXX

ERROR COUNT: XXXXX READ DATA XX STATUS r XXX

01 - Pressed key display 99 - Exit to DIAGNOSTIC TEST MENU


Select desired subtest by pressing two digits subtest number in SUBTEST MENU as shown above and "ENTER" key. Then select the test mode by pressing "l:YES" or "2:NO" and "ENTER" keys for TEST LOOP and ERROR STOP question respectively.

The selected subtest starts and test information such as SUBTEST Ro., PASS COUNT, ERROR COUNT, MUTE DATA, READ DATA, ADDRESS, and STATUS are displayed and updated during execution as shown above.


8-16

Subtest description

Keyboard layout is drawn on the Display, and when a certain key is pressed, the character "*" will be displayed at the corresponding location of the screen.

If the same key is pressed again, it becomes to be the original state so that it is able to confirm the self-repeat function.

If you stop the Keyboard test, press "ctr 1" + "Break" keys .

. , Note: If state of NUDl Lock is ON, you can not execute exact test.

8-17

8.6 DISPLAY TEST

Summary of the Display Test

This test performs the test of VIDEO RAM read/write, attribute character, character mode display, graphic mode display, and screen page for LCD and its controller function.



DISPLAY TEST XXXXXXX



ADDRESS XXXXXX STATUS : XXX

SUB-TEST MENU :

01 - VRAM readlwrite 02 - Character attributes 03 - Character set 04 - 80 * 25 Character display as - Graphics display (caler set all) 06 - 640 * 200 Graphics display 07 - 640 * 400 Graphics display 08 - Display page 09 - »H» pattern display 99 - Exit ta DIAGNOSTIC TEST MENU


Select desired sUbtest by pressing two digits subtest number in SOBTEST MENU as show above and "ENTER" key. Then select the test mode by pressing "l:YES" or "2:NO" and "ENTER" for TEST LOOP and ERROR STOP question respectively.

The selected subtest starts and test information such as SOBTEST Ro., PASS COUNT, ERROR COUNT, WRITE DATA, READ DATA,. ADDRESS, and STATUS are displayed and updated during execution as shown above.


8-18

Subtest description

Subtest 01 Read/write test of video RAM

In the display-off mode, it writes the constant data such as "FFH", "AAH" , "55H", "OOH" to the video RAM, then it reads and compares them with the original data.

Subtest 02 Character attribute display test

Normal Display Intensified Display Reverse Display Blinking Display

* Note If it is a color CRT display unit, you checks background color, foreground color, border color about each of seven colors of blue, green cyan, red magenta, yellow and white.

Subtest 03 Display of character set

Displays in 40 x 25 Test mode character codes "OOH" though "FFH".

Subtest 04 Display of 80 x 25 characters

Displays Shift-Characters.

Subtest as In the case of-Color Display:

Displays three painted blocks with color set a in 320 x 200 graphic mode.

Blocks color green, red, and yellow

Displays three painted blocks with color set a in 320 x 200 graphic mode.

Blocks color Cyan, magenta, and white.

In the case of Plasma Display:

Screen is lighten in order of RED MAGENTA, GREEN CYAN, YELLOW WHITE.

Subtest 06 Display in 640 x 200 graphic mode

It displays in the screen Black & white.

Subtest 07 It cann't executes.

To be continued.

8-19

Subtest description (Continued)

Subtest 08 Screen Page test

Displays the contents of VIDEO RAM to the CRT in 40 x 25 test mode. VIDEO RAM contains a capacity of 8 screen pages and each screen page is displayed as all "0", all "1" and all "7" respectively.

Subtest 09 "H" Pattern display test

Display of "H" character on the whole screen.

8-20

8.7 FLOPPY DISK TEST

Summary of the FLOPPY DISK Test

This test performs the read/write test with sequencial address, random address, and specified address for FDD and its controller functions.


After pressing DIAGNOSTIC TEST screen.

"5" and "ENTER" keys at test selection MENU, the following message appear on

Test drive nu.ber select (1: FDDI, 2: FDD2, 0: PDDI&2) ?

1: Executes only FOOl test.

2: Executes only FDD2 test.

0: Executes FOOl and FDD2 test.

After you choose the drive number of FOD, then input it.

To be continued.

8-21

of the

Subtest and test mode selection (Continued)

The following screen appears for subtest and test mode selection.

FLOPPY DISK XXXXXXX




SUB-TEST MENU :

01 - Sequential read 02 - Sequential read/write 03 - Random address/data 04 - Write specified address 05 - Read specified address 99 - Exit to DIAGNOSTIC TEST MENU


Select desired subtest. by pressing two digits subtest number in SUBTEST MENU as shown above and "ENTER" key. Then select the test mode by pressing "l:YES" or "2:NO" and "ENTER" keys for TEST LOOP and ERROR STOP question respectively.

The selected subtest starts and test information such as SOBTEST Bo., PASS COUNT, ERROR COUNT, WRITE DATA, READ DATA, ADDRESS ,and STATUS are displayed and updated during execution as shown above.

Refer the following subtest description. Refer to the ANNEX C for error status code.

8-22

Subtest description

Subtest 01 Sequential read test

Reads all tracks sequencially and checks CRC.

Subtest 02 Sequential read/write test

Wri tes data to all tracks sequencially, and then reads the data back and compares them with the original data. CThe data pattern, "BsADAD H", is repeated.)

Subtest 03 Random address/data read/write

Writes random data into tracks gelected at random, and then reads the data back and compares them with the original data.

Subtest 04 Specified address write test

Writes the data into a track and a head specified and head address done through the Keyboard.

Subtest as Specified address read test

Rate:

Reads the data from the track and head address specified through the Keyboard.

Use one of the following "Format" programs to format a work disk according to the disk type. In the case of 2DCFORMAT /4), formatted tracks are a thru 39. In the case of 2DDCFORMAT), formatted tracks are a thru 79.

8-23

8.8 PRINTER TEST

Summary of the Printer Test

This test performs the test of ripple pattern, functions (six print modes), and wraparound for printer and its controller.



PRINTER TEST


SUB-TEST MENU :

01 - Ripple pattern 02 - Function 03 - Wrap around

XXXXXXX


99 - Exit to DIAGNOSTIC TEST MENU


Select desired subtest by pressing two digits subtest number in SUBTEST MENU as shown above and "ENTER" key. Then select the test mode by pressing "l:YES" or "2:NO" and "ENTER" keys for TEST LOOP and ERROR STOP question respectively.

The selected subtest starts and test information such as SOBTEST _0., PASS COUNT, ERROR COUNT, WRITE DATA, READ DATA, ADDRESS ,and STATUS are displayed and updated during execution as shown above.


8-24

subtest description

Subtest 01 Ripple pattern test

Prints characters (codes "20H" through "7EH") on a line rotating the line pattern by one character to the down lines.

Subtest 02 Function test

Normal Print Double Width Print Compressed Print Emphasized Print Double strike Print All Characters Print

Subtest 03 Wraparound test

Checks the data, control, and status lines wi th the Printer Wraparound Connector(Part No.

).

Note: Subtest 01 and subtest 02 needs the channel selection.

8-25

8. 9 ASYNC (RS232C) TES~

Summary of the ASYNC(RS232C) ~est

This test performs the data transmission (Send/Receive) with the CCM Wraparound Connector(Part No. ).


After pressing "7" and "ENTER" at test selection, the following screen appears for subtest and test mode selection.

ASYNC TEST XXXXXXX.




SUB-TEST MENU :

01 - W~ap a~ound (channel-1) 02 - W~ap a~ound (channel-2) 03 - Point to point (send) 04 - Point to point (~eceive) 05 - Ca~d modem loopback 06 - Ca~d modem on-I ine test 07 - Dial teste~ test 99 - Exit to DIAGNOSTIC TEST MENU


..,----- ------- ------- -,,£ r-------J oJ

in sUBTEsT MENU as shown above and "ENTER" key. Then select the test mode by pressing "l:YEs" or "2:NO" and "ENTER" keys for TEST LOOP and ERROR STOP question respectively.

The selected subtest starts and test information such as SUBTEST 80., PASS COUNT, ERROR COUNT, WRITE DATA, READ DATA, ADDRESS, and STA~US are displayed and updated during execution as shown above.


8-26

Subtest description

Note: Communication mode of subtest 01 - 05 is as follows; Async, 9600 BPS, 8 data bit + parity (even), 1 step bit, data = 20H - 7EH. From subtest 03 to subtest 07 need the channel selection.

Subtest 01 Wrap around test (channel - 1)

Performs a data send/receive test with the wraparound connector for the channell.

Subtest 02 Wrap around test (channel - 2)

Performs the same test as subtest 01 for the channel 2.

Subtest 03 Point to point test (send)

Sends data (codes 20H through 7EH) to another communication device referred to as a receiver, and receive the data from the receiven, then compared them with original data.

Subtest 04 Point to point test (receive)

Receives the data from another communication device (referred to as a transmitter) comparesthem with original data then back the data to the transmitter. Note: Subtest 03 (send side) and subtest 04

(receive side) is pare.

Subtest 05 Card modem loopback test

Sends data to a card modem, then receives the data looped back in the card modem, then compares them with original data.

Subtest 06 Card modem on-line test

Sends data to a card modem through data a PBX, then receive looped back and compares them with original data. Communication mode is 110/300/1200 BPS, 8 data bits + no parity,· 1 stop bit, data = 20H - 7EH codes.

To be continued.

8-27

Subtest 07 Dial tester test

Performs pules dial and tone dial test with a dial tester. The pulse dial test sends the pulse "1-2-3-4-5-6 -7-8-9-0-1-2" twice. The tone dial send the data "1-2-3-4-5-6-7-8-9-*-0-#" twice.

8-28

8.10 BARD DISK TEST

Summary of the BARD DISK Test

WARNING

The data on the HOD will be lost permanenty during the write operations in subtests 2, 3, 4, 6 and 8.

Current disk contents will be completely destroyed. Save the data on Bard Disk before execute this program if you don' t want to do so.

If you execute the subtest 2, 3, 4, 6 and 8 must set the partition of BDD. (Refer to 8.20 Set the partition)

This test performs the read/write test with sequential address, randam address, and specified address and so on for HOD and its controller function.

To be continued.

8-29


After pressing "8" and "ENTER" keys message on the screen.

appear the following

Test drive number select (1: BDD1r 2: BDD2r 0: BDD1&2) ?

1: Executes the test of only drive 1. 2: Executes the test of only drive 2. 3: Executes the test of drive 1 and drive 2.

After you choose the above number, then press it. The following screen appears on the display for subtest selection.

HARD DISK TEST XXXXXXX




SUB-TEST MENU :

01 - Sequential read 02 - Address uniquence 03 - Random address/data 04 - Cross talk & peek shift OS - Write/read/compare(CE) 06 - Write specified address 07 - Read specified address oe - ECC circuit (CE cyl inder) 99 - Exit to DIAGNOSTIC TEST MENU


Selected desired subtest by pressing two digits subtest number in SUBTEST MENU as shown above and "ENTER" key. Then select the test mode by pressing "l:YES" or "2:NO" and "ENTER" keys for TEST LOOP and ERROR STOP question respectively.

The selected subtest starts and test information such as SUBTEST ROer PASS COUNT r ERROR COUNT r WRITE DATAr READ DATA, ADDRESS, and STATUS are displayed and updated during execution as shown above.

Refer to the ANNEX C for error status code.

8-30

subtest description

Subtest 01

Subtest 02

Subtest 03

Subtest 04

Subtest 05

Subtest 06

Subtest 07

Subtest 08

Sequential read test(CYL.0-6l0,CYL.6l0-0)

Performs the Forword Read(0-6l0 tracks) and Reverse Read(6l0-0 tracks).

Address uniquence test

Writes the address data(sector by sector) track by track, then reads the data and compare them. Following three kind of reads operations are performed.

(Forward sequential, Reverse sequential, Randam)

Randam address/data test

write, read and compare the data at randam address (Cyl, Head, and Sec) and randam length.

Cross talk & peek shift test

Write, read and compare the worst pattern data (8types such as BSADADH, 4AS2S2H, EB6DB6H, l49249H, 63B63BH, 9C49C4H, 2DB6DBH, and D24924H) cylinder by cylinder to check the interference between the tracks.

CE cylinder(6ll) Write/Read/Compare test

The Worst pattern data (BSADADH) is used in this test.

Specified address write test

Writes the data at the specified cylinder and head address.

Specified address read test

Read the data at the specified cylinder and head address.

ECC circuit test

Checks the ECC circuit functions at CE cylinder (611 cylinder).

8-31

8.11 REAL TIMER TEST

Summary of the REAL TIME test

This test performs the check test of the calender and timer.



REAL TIME TEST

SUB-TEST XX PASS COUNT: XXXXX ""RITE DATA: XX ADDRESS XXXXXX

SUB-TEST MENU :

01 - Real time test

XXXXXXX


02 - Real time carry set 99 - Exit to DIAGNOSTC TEST MENU


Select desired subtest by pressing two dights subtest number in SUBTEST MENU as shown above and "ENTER".

8-32

Subtest description

Subtest 01 Real time test

The Current date and time are display, and new date and new time are possible to be entered.

Subtest 02 Real timer set

WARNING : If this test execute, Current date and Current time return to "12-31-1985" "23:59:55".

Confirm that up date Current date and time are displayed on the screen. Start the from the menu as follow.

Current date

Current time

12-31-1985

23:59:55

8-33

8.12 NDP (8087) TEST

You can't execute this test. If you execute this test, error status is displayed on the screen.

8-34

8.13 HARD DISK FORMAT

Summary of the program

·WARNING : Current disk contents will be completely destroyed. Save the data on Bard Disks before execute this program if you don't want yo do so.

If Formats a Hard Disk Drive with the specified format and 4 types operation described in program description on next page.

Program execution

After pressing "2" and "ENTER" keys at task selection of DIAGNOSTIC MENU , the following screen appears before execution.

DIAGNOSTICS - HARD DISK FORMAT 1 - All track FORMAT 2 - Good track FORMAT 3 - Bad track FORMAT 4 - Bad track CHECK 9 - Exit to DIAGNOSTICS MENU

Press (NUMBER] key ?

To be continued.

8-35

Program description

(1) All track FORMAT (Execution time 6 minutes)

Executes format of Hard Disk.

Secter sequence Cylinder Head Sector Sector length Bad track

3 612 (0 - 611) 2 (0 - 1) 17 (1 - 17) 512 Byte/sector Up to 12 tracks (If more than track were typed-in, the program is terminated. )

All track format execute as follws.

1. Reads the all track, and then check the Bad track information now.

2. You input the Bad track information. 3. Formats the all track by Good track format. 4. writes the Bad track by information of 1 and 2. 5. Executes Read test to all track, and error track

dicide the Bad track.

(2) Good track FORMAT (Execution time 1 second)

Executes the format of appointed cylinder and track as good-track.

(3) Gad track FORMAT (Execution time 1 second)

Executes the format of appointed cylinder and track as bad-track.

(4) Bad track CHECK (Execution time 1 and half minutes)

Check for the bad-track by read operation about all-track on the Hard Disk, then it display list of bad-track.

8-36

8.14 SEEK TO LANDING ZONE

Summarry of the program

This program moves head of the Hard Disk Drive to Landing Zone.

Note: When it does not issues any command to HDD for 5 seconds, heads of the Hard Disk Drive moves to Landing zone antomatically.

8-37

8.15 BEAD CLEANING


It executes the head load, seek and read operation for the purpose of head cleaning.

The Clean ing Disk Kit (Part No. perform the cleaning properly.

Program execution

is required to

After pressing "4" and "ENTER" at task selection of DIAGNOSTIC MENU , the following screen appears before test execution.

HEAD CLEANING

Mount cleaning disk(s) on drive(s). Press any key when ready.

After the above message apper on the screen, then set the Cleaning Disk to FDD and press the any key.

The message of ·Cleaning start- is displayed on the screen and Head Cleaning is executed.

When it is finished, it return to the Diagnostic Menu.

8-38

8.16 LOG UTILITES


The error information detected while testing is logged in the memory or the test floppy disk. The logged error information is able to be displayed on the CRT or be printed out through the printer.

Program execution

The error information logged in the Memory or the floppy disk is displayed as shown below by press "5 II key during the task selecting operation.

Error Display

00000 ERRORS Qll. TEST NAME T

PASS count

Test name

Error count

Number of error log entrys

ERROR STATUS NAME

Read data

write data-

FDD address

Error status

(( 1:N.xt,2:Pr.v,3IExit,4:CI.ar,S:Print,~:FO L09 Raad,7:FO L09 Write JJ \.

Operation guide is displayed bottom of the screen. Error status name is displayed right side of the screen.

The following functional keys are available for the error display screen.

"1" key One page is scrolled upwards.

"2" key One page is scrolled downwards.

"3" key It returns to task selection.

"4" key All error logs in RAM are erased.

To be continued.

8-39

Note

"5" key

"6" key

"7" key

The error logs are printed out through the printer.

The error logs in floppy disk are displayed on the CRT.

The error logs in RAM are written to floppy disk.

When the error retry was made successfully, the "R" character is added at the head of error status. In this case; the error count is not updated.

8-40

8.17 RUNNING TEST


The Running Test makes a sequential and continuous execution of the test programs specified by the test list of system parameter with taking no man's intervention. Under the execution of Running Test, it displays the test name and subtest number being currently executed.

Program execution

Prior to the execution of Running test, the screen shows the following messages asking of execution or non-execution of printer and ASYNC wraparound test, and display selection .

(1) Printer wraparound test (1:YES/2:NO)?

1 It executes the printer wraparound test.

2 It does not execute the printer wraparound test.

(2) Asyne wraparound test (1:YES/2:NO)?

1 It executes the async wraparound test.

2 It does not execute the async wraparonud test.

The Running Test executes the following test programs

Test name to be tested

1. System

2. Memory

3. Display

* 4. FDD

5. Printer

6. RS232C

Subtest number in sequential execution

01

01, 02, 03, 04

01 - 08

02

03 (Printer Part No.

Wraparound connector is required.)

01 (CCM Wraparound Connector Part No. is required.)

Refer to ANNEX A , Test Program List, for summary of the subtests or Subtest description in each program module for the details.

(* mark: Automatically select "l"(one FDD) or "O"(two FDD.)

8-41

8.18 FDD UTILITES

(1) FORMAT

Formats a Floppy Disk

(2) COpy

Two-sided dob1e density double-track, 48TPI,MFM mode 512 Byte, 9 sectors/track (20) Two-sided dob1e dens i ty double-track, 96TPI, MFM mode 512 Byte, 9 sector/track (200)

Copys a Floppy Disk Copy with one FDD (Drive A) Copy with two FDDs (from drive A to B)

(3) DUMP

Displays contents of Floppy Disk (each type) or Hard Disk (designated sector).

8-42

8.19 SYS·TEM CONFIGURATION


It displays your system's configuration such as Memory si ze, Display type, Number of FDDCs), Number of HOD, Number of RS232C, Number of Printer and option.

SYSTEM CONFIGURATION

* - b40KB MEMORY

* - LCD DISPLAY

* - Z FLOPPY DISK DRIVE(S)

* - 1 ASYNC .ADAPTER

* - a HARD DISK DRIVE(S)

* - 1 PRINTER ADAPTER

* - a MATH CO-PROCESSOR

PRESS CENTER] KEY

Above message is an example of F/F type System.

8-43

8.20 SET THE PARTITION


This program set the partition of Hard Disk.

In the case of following items, you need to set the partition of Hard Disk.

1. Replacing the good spare HDD. Note: After formating the HDD, executes it.

(Refer to paragraph 8.12)

2. Breaking the media of HDD.

3. Executing the Hard Disk Test of Test & Diagnostic.

To be continued.

8-44

Program execution

Insert the MS-DOS System Disk into the internal disk drive, then turn on the power of the TllDD PLUS System. After MS-DOS loading, press the "ENTER" key twice. INPUT -FDISK- then press "ENTER" keys, then the following screen appears for the partiton setting.

Fixed Disk Setup Pre9ram

Tetal bll cyl inciers 17kb/cyl inder)

Partition iype Status Start End Size

1 DOS A o bl0

Max. avai iabie s~ace

Choose cne C~ t~e tel lewin9 eptiens

2 3

Create Partition Change Active Partition Delete Partition

bl1

o

Fress ESC to re~urn to DOS/FDISK o~tion

1: Executes partition setting

I Drive #1

1

2: Changes the strat address and end address of the partition.

3: Deletes the partition setting.

Refer to OWNER-S MANUAL.

8-45

ANNEX A: TEST PROGRAM LIST

TEST TEST NAME SUBTEST TEST ITEM No. No.

1 SYSTEM 01 ROM Checksum

2 MEMORY 01 Constant Data R/W test 02 Address Pattern R/W test 03 Memory Refresh Test

3 KEYBOARD 01

4 DISPLAY 01 Video RAM R/W Test 02 Character Attribute display 03 Character Set display 04 80 x 25 display 05 320 x 200 Graphic display 06 640 x 200 Graphic display 07 640 x 400 Graphic display 08 Screen Page Test

5 FDD 01 Sequential Read Test 02 Sequential R/W Test 03 Random Address/Data R/W Test 04 Specified Address Write Test 05 Specified Address Read Test

6 PRINTER 01 Ripple Pattern Test - 02 Function Test 03 Wraparound Test (It needs

wraparound connector.)

7 ASYNC/ 01 Wraparound (chanel-l)Test (RS232C) 02 (It needs wrapround connector)

02 Wraparound (chanel-2)Test (It needs wrapround connector)

03 Point to point Test (send) ( )

04 Point to point Test (recive) ( )

05 Card modem loopback Test 06 Card modem on-line Test 07 Dial tester Test

8-46

ANNEX A : TEST PROGRRAM LIST (Continued)

TEST TEST NAME SUBTEST TEST ITEM No. No.

8 HDD 01 Sequential read Test 02 Address uniquence Test 03 Random address/data Test 04 Cross talk & peek shift Test 05 Write/read/compare (CE) Test 06 Write specified address Test 07 Read specified address Test 08 ECC circuit (CE cylinder) Test

9 Real time 01 Real time Test 02 Real time carry set Test

10 NDP 01 NDP Test

8-47

ANNEX B: AVERAGE EXECUTION TIME

TEST TEST NAME SUBTEST EXECUTION TIME NO. NO.

1 SYSTEM 01 1 Second

2 MEMORY 01 59 Seconds (640 KB) 02 17 Seconds

03 35 Seconds

3 KEYBOARD 01

4 DISPLAY 01 1 Second 02 1 Second 03 1 Second 04 1 Second 05 3 Second 06 7 Second 07 15 Second 08 15 Second

5 FDD 01 65 Seconds 02 130 Seconds 03 12 Seconds 04 1 Second 05 1 Second

6 PRINTER 01 110 Seconds 02 15 Seconds 03 1 Second

7 ASYNC/ 01 1 Second (RS232C) 02 1 Second

03 1 Second 04 1 Second 05 5 Second 06 10 Second 07 60 Second

8-48

ANNEX B : AVERRAGE EXECOTION TIME (Continued)

TEST TEST NAME SUBTEST EXECUTION TIME NO. NO.

8 HOD 01 6 Second 02 10 Second 03 30 Second 04 13 Second 05 2 Second 06 1 Second 07 1 Second 08 2 Second

9 Real Time 01 02

10 NDP 01 1 Second

8-49

ANNEX C: ERROR STATUS CODE LIST

DEVICE NAME

SYSTEM

MEMORY

COMMON

FDD

PRINTER

ASYNC/ (RS232C)

ERROR CODE

01

01 02

FF

01 02 03 04 06 08 09 10 20 40 60 80

01 08 10 20 40 80

01 02 04 08 10 20 40 80 88 33 34 36

8-5D

STATUS

ROM Checksum Error

Parity Error PROTECTED MODE NOT CHANGE ERROR

Compare error

Bad Command Address Mark Not Found Write Protected Record Not Found Media removed on dual attach card DMA Overrun Error DMA Boundary Error CRC Error FDC Error Seek Error FDD not drive Time Out Error

Time Out Fault Select Line Out of Paper Power off .Busy Line

DSR Off Time Out CTS Off Time Out RX EMPTY Time Out TX BUFFER FULL Time Out Parity Error Framing Error Overrun Error Line Status Error Modem Status Error NO CARRIER (CARD MODEM) ERROR (CARD MODEM) NO DIAL TONE (CARD MODEM)

ANNEX C ERROR STATUS CODE LIST (Continued)

DEVICE NAME

HDD

NDP

ERROR CORD

01 02 04 05 07 09 OA OB 10 11 20 40 80 AA BB CC EO Fa

01 02 03 04 05 06

8-51

STATUS

Bad command error Bad address mark Record not found HDC NOT RESET Device not initialize DMA Boundary error Bad secter error Bad track error ECC error ECC recover enable HDC error Seek error Time out error Device not ready Undefined Write fault Status error Not sense error (HW.code=FF)

NO CO-PROCESSOR Control word error Status word error Bus error Additional error Multipul error

ANNEX D: WRAPAROUND CONNECTOR

1. Wraparound connector for printer (Dsub 25 pin male)

9) + DATA 7( 4) 4) + DATA 2

8) + DATA 6( 3) 3) + DATA 1

7) + DATA 5( 2) 2) + DATA 0

(6) + DATA 4(16) (16) - INT PRT

(17) + DATA 3( 1) (1) - STROBE

+ SELECT (13 )

+ P. END (12)

+ BUSY (11)

- ACKNOWLEDGE (10)

- ERROR (15)

2. Wraparound connector for RS232C

3) TRANSMIT DATA

7) REQUEST TO SEND

( 4) DATA TERMINAL READY

RECEIVE DATA

------------r-- CLEAR TO SEND L-- CARRIER DETECT

I DATA SET READY L....- RING INDICATE

2)

8 ) 1)

( 6) ( 9)

3. Direct connection cable for RS232C

(Dsub 9" pin Fumale) ( 3) TD

( 4) DTR

7) RTS

5) GND

2) RD

1) CD

( 6) DSR ( 8) CTS ( 9) RI

8-52

(Dsub 9 pin Fumale) RD 2)

DSR 6) 1---- CTS 8)

RI 9)

CD 1)

GND 5)

TD 3)

RTS 7)

DTR 4)

APPENDIX A

Bus Controller GA (Gate Array)

The Bus Controller Gate Array is a 2,600 gate flat package type with 100 lead chip. It contains following functions. Signal name and meaning of each pin, and description of each function block are covered in this section.

1) Clock generator

2) Command decoder

3) Bus controller

4) 8-16 bit conversion controller

5) Wait controller

6) DMA bus controller

7) DMA Page register

8) RAM/ROM select controller

9) NMI controller

101 Keyboard Data Controller

11) Circuitry compatible to 8255

12) TURBO

80 51

81 50

10

1 30

A-I

RCSELO

CASTl DACKOO A191 -

A161

A15l

OACK30-DACK20

PAGWRO

NMIRGO PARERll, TESTl IN T871

10071-01

TC20UTl EFDSLl PPICSO AOll

SW4l-11

K8CLl KBDTl-

S20-00

DMAEN1 BHEl A001

I ORDY 1 HRQDM1

TURBOO

OSC141 TESTl TEST2

01

Figure A-I Bus Controller GA Block Diagram

RAM - Controller

r-;:= :::::.

ROM

- 1 IController

b 'I I DMA Pag e Register

~ NMI - Contro11er -

--

-== 1--------------1-- --~ -. I .1 !'ort B

~ I

, rI Latch , r - - - - - - - - - - - - -' -,-

I I I I Port C I I Buffer "-----..1 Port A L-I Buffer ~

I r I I I I 1) I

I I I

I K.B. I I Data • I I S~P I I I

~---------------------------------- ______ I

Comnland --.. Controller =J -I,

V Bus Controller

r-

I '---

Wait/DMA Controller

-~CIOCk 4.7717.16MHz

4.IIMHz 14.31818MHz Generator /.IXI'fH1

,

A-2

MAD81

MEWEO RASTO DME SLO RAS41-

RASO 1 CASHEl CASLE1

ROMENO ROMC SO

NM 11

TMGA T1

SPKDRO

KBCLKl KBDTAl I RQll

INTAO MRDO MWRO 10RDO 10WRO CALENl

HLDA1 ADOB 1 WDLA Tl WDL ENO BWDIR1 BDLENO BWHENO

RGTO CPADEO PRDYl RDYDMl

CPUCLKI DMCLK1 TMCLK1

LOWSPO

Interface Signal (In=35 r Out=38 r I/0=17)

Pin

1

2

3 4 5 6 7 8 9

10

11 12 13

14 15 16 17 18

19

20

21

2.2

23

24 25 26 27

I/O Signal Name Description

I CAST 1 CAS timing signal. This signal is qenerated from delayed RAST.(lOO ms)

0 KBCLKI Data transfer clock to Keyboard controller. Low level at Port-B bit6 ="0".

Vcc +5v 0 DMCLKI DMA(82C37) clock, 4.77 MHz. 0 KBDTAI Data to Keyboard controller. I DACK30 DMA acknowledqe signal for channel 3. I DACK20 DMA acknowledge siqnal for channel 2. I DACKOO DMA acknowledge signal for channel O. I HRQDMI DMA request siqnal from 82C37. I DMAENI DMA address enable signal (A19-A16).

This signal is generated from the AEN siqnal of 82C37.

0 RDYDMI Bus ready siqnal in a DMA cycle I KBDTI Data from the Keyboard controller. I KBCLI Clock signal from the Keyboard controller.

It is used to transfer data from the Keyboard controller.

0 TMCLKI Clock signal for 82C53. GND Ground

0 TMGATI Control signal to qate 2 of 82C53. I TC20UTI Output siqnal from channnel 2 of 82C53. 0 INTAO Interrupt acknowledge command.

Response siqnal to interrupt request o. IRQll Interrupt level 1 signal.

(for Keyboard interrupt) I TEST 1 Output command inhibit signal.

If "Low", inhibit (command input = mode). If "High", enable (command output = mode).

0 ROMENIO ROM read enable~nal. Active Low when (FOOO - F7FFF) MERD.

0 RASTO RAS timing signal. This signal is output with RASO-RAS4 at same time. It is inhibited when memory refresh time.

0 RASll RAS timing of 128 KB memory block. RASll for 128 KB - 256 KB.

0 RASOI RASOI for 0 - 128 KB . 0 CAS LEI CAS timig, low side (even address) • 0 CASHEI CAS timig, hiqh side (odd address). 0 PRASI RAS signal for parity bit. ( 0 - 512 KB )

Note: Least significant digit of the signal name stands for active level. 0: Low, l:High

A-3

Interface Signal (Continued)

Pin I/O Signal Name Description

28 vcc +5v 29 0 RAS2l RAS timing of 128 KB memory block.

RAS2l for 256 KB - 384 KB. 30 0 RAS3l RAS3l for 384 KB - 512 KB. 31 0 RAS4l RAS4l for 512 KB - 640 KB. 32 0 MAD8l Address IIA8 11 for 256 K x 1 parity RAM. 33 0 CPADEO DMA HOLDA signal.

CPU address bus is disable/DMA address bus is enable.

34 0 ROMCSO ROM select signal. (ROM=FOOOO-FFFFF)

35 0 SPKDRO Speaker drive signal. 36 I IORDYl Bus ready signal. 37 0 ADOBl Address bit O. 38 I/O IOWRO I/O bus data write command. 39 I/O IORDO I/O bus data read command. 40 GND Ground 41 I/O MWRO Memory data write command. 42 I/O MROO Memory data read command. 43 I PPICSO PPI select signal.

This signal is active low. 44 I NMIRGO NMI set signal.

This signal is active low. 45 I PAGWRO DMA page Req. write signal. 46 I TURBOO Set signal to CPU clock control Reg. 47 0 LOWSPO CPU clock mode.

(IiHighll=7.l6 MHz, .. Low" = 4 . 7 7 MH z ) 48 I PONCLO Power on clear signal. 49 I RCSELO Timing signal to Row/Column switching. 50 0 ROMENO ROM read enable signal. This2i.9:,nal is

generated when (F8000-FFFFF)·MERD. 51 I/O A191 CPU/DMA address lines. CPU address is in-

put when input mode. DMA page reg. content is output when output mode (DMA cycle). Address line bit 19.

52 I/O A181 Address line bit 18. '53 Vcc +sv 54 I/O A171 Address line bit 17 55 I/O A16l Address line bit 16 56 I Alsl Address line bit 15. 57 I A141 Address line bit 14. 58 I A131 Address line bit 13. 59 0 CALENI CPU address latch signal.

A-4



60 0 HLDAI Timing signal same to CPADEO but it goes to Exp. bus.

61 0 WDLATI Low data (even) latch signal for word read operation to 8 bit Bus.

62 0 WDLENO Low data (even) enable signal for word read operation to 8 bit Bus.

63 0 BDLENO Low data (even) enable signal for byte read/write operation.

64 0 BWDIRI Specifys data direction. Held to be low except IOWR and MEWR to I/O Bus.

65 GND Ground 66 0 BWHENO High data (odd) enable signal for byte or

word read/write operation. 67 0 ME WE 0 WE timinq signal for s~stem RAM. 68 I/O IOD7l Bidirectional data bus bit 7. 69 I/O IOD6l Bidirectional data bus bit 6. 70 I/O IOD5l Bidirectional data bus bit 5. 71 I/O IOD4l Bidirectional data bus bit 4. 72 r/o rOD3l Bidirectional data bus bit 3·. 73 I/O IOD2l Bidirectional data bus bit 2. 74 I/O IODll Bidirectional data bus bit 1. 75 I/O IODOI Bidirectional data bus bit O. 76 I PAREROI Parity bit for odd address data. 77 I PARERll Parity bit for even address data. 78 Vcc +5v 79 I AOOI Address line bit O. 80 I AOll Address line bit 1. 81 0 NMII Non maskable interrupt signal. 82 0 CPUCLKI CPU Clock: 4.77 MHz ( SLOW)

7.16 MHz (FAST) 83 0 RESETI Reset pulse. This siqnal is active hiqh. 84 0 PRDYI CPU ready siqnal. 85 I sao CPU status siqnal bit O. 86 I SIO CPU status siqnal bit 1. 87 I S20 CPU status siqnal bit 2. 88 I BHEI Bus high enable.

Decides bus mode, it is used with AO

BREI AO Descr iption 0 a Whole word 0 1 Upper byte - odd address 1 0 Lower byte - even address 1 1 None

A-5



89 I INT871 8087 interrupt siqnal. 90 GND Ground 91 I/O RGTO This gate sends a low pulse to RQ/GT pin

of the CPU when the GA receives a HRQDMl signal from the 82C37. Then it sends a HOLDAl signal to the 82C37 when it receives a low pulse from the CPU. It also sends a low pulse to the CPU from this qate when the DMA cycle is complete.

92 I OSC141 Output signal from OSC. 14.31818MHZ

93 I EFDSLI External FDD select switch signal. 94 0 DMESLO V-)itRAM select signal. 95 I TEST2 If. "Low" , clock duty is 1/2.

If "High", clock duty is 1/3. 96 TEST3 Test pin. 97 I SW41 Configuration switch signal bit 4. 98 I SW31 Configuration switch signal bit 3. 99 I SW21 Conf iguration switch signal bit 2.

100 I SWll Configuration switch signal bit 1.

A-6

Followings are summarized descriptions about each functional block in this GA.

1) Clock Generator

The Clock Generator receives 14.31818 MHz clock, then generates CPU clock, DMA clock and Timer clock.

CPU clock DMA clock Timer clock

4.77 MHz/7.l6 MHz * 4.77 MHz (Duty 50%) 1.18MHz (Duty 50%)

* :CPU clock rate is changed by selecting mode (Fast/Slow). The clock duty is selected to 1/2 or 1/3 by TEST2 pin.

2) Command Decoder

Commands to I/O controller or memory are generated by decoding CPU status.

CPU Status Command S2 Sl SO 0 0 0 INTAO 0 0 1 IORDO 0 1 0 IOWRO 0 1 1 (None} 1 0 0 MERDO 1 0 1 MERDO 1 1 0 MEWRO 1 1 1 (None)

3) Bus Controller

The Bus Controller controrls data bus by decoding commands described paragraph 2).

A-7

4) 8 -- 16 bit conversion controller

a bit -- 16 bit conversion is performed by this circuitry when an a bit bus is accessed. Bus, Wait timing is controlled by this circuitry.

5) Wait controller

The wait controller decides CPU wait cycle according to the each command described paragraph 2) by Bus Ready signal. The basic cycle timing of the each command is as follows.

C:mmand CPU Clock Rate 7.16 MHz 4.77 MHz

RAMCSvstem RAM) 4T 4TC6T) ROMCByte) ST 4TC6T) ROM(Word) lOT aTC12T) I/O BusCByte) 6T STC7.ST) I/O Bus ( Word) l2T lOT(lST) DMA ST STC7.ST)

Note: The cycle timing with parenthesises is counted as the cycle timing under the clock rate of 7.16 MHz.

6) DMA Bus Controller

The DMA Bus Controller issues DMA request signal and controls bus. It issues a bus disconnection request signal (RQ/GT) to the CPU as a response to the DMA request from the DMAC. It issues HOLDAI signal to DMAC.when the bus is disconnected, then DMA cycle starts. After the DMA cycle is complete, it changes the bus connection to the CPU by sending a signal to the RQ/GT gate of the CPU. The Output of I/O address decoder is inhibited during a DMA cycle.

A-a

7) DMA Page Register

This register is to save the most significant 4 bits of the address lines (A19 - A16) during a DMA cycle. It is composed of 3 sets of 4-bi t reg isters and they are assigned to the following I/O addresses.

I/O Address Command Descr~ption

OSI IOWR DMA Channel 2 Page Register

7 ----- 4 3 2 1 0 I IA191AlSIA171A161

OS2 IOWR DMA Channel 3 Page Reqister OS3 IOWR DMA Channel 0 and 1 Paqe Reqister

8) RAM/ROM Select Con troller

This circuit is for RAM/ROM address select control on the system board. It issues RAS/CAS signals to the RAM and ROM for the control.

A). RAM select on the system board. I~ uses the informations of address signal (0 - 640 KB) and configuration. DIP switches on the system board for the RAM selection.

DIP Switch SW3 SW2

0 0 1 1

no" = ON "I" = OFF

0 1 0 1

/ Memory Size

256 KB (00000 - 3FFFF) "Q.S..6) KB (40000 - 5FFFF)

512 KB (60000 - 7FFFF) 640 KB (SOOOO - 9FFFF)

A-9

B). RAM/ROM Selection. RAM/ROM select signals are generated from address signals as follows.

Address Memory Select Signal 19 IS 17 16 15 14 13 a a a - - - - RASa (00000 - lFFFF) a a 1 - - - - RASI (20000 - 3FFFF) a 1 a - - - - RAS2 (40000 - 5FFFF) 0 1 1 - - - - RAS3 (60000 - 7FFFF) 1 0 0 - - - - RAS4 (SOOOO - 9FFFF) 0 - - - - - - PRAS (00000 - 7FFFF) 1 1 1 1 a - - ROMENlO(FOOOO - F7FFF) 1 1 1 1 1 - - ROMENO (FSOOO - FFFFF) 1 a 1 1 - - - DMSL (BOOOO - BFFFF) 1 1 0 0 - - - DMSL (COOOO - CFFFF)

C). Refresh Address Control. The refresh address of the RAM is given by DMA address (A7 - AO). But RAM address is given as Al - A16. A16 is input as a least significant bit (AO) of ROW address of the RAM, and it is changed to as AO. AO is used for ODD/EVEN selection of the data bus except refresh cycle. Note: "ADS" of the 256 KB RAM (for parity-bits) is given by switching A17 and AIS. ROW(Al7)/COLUMN(AlS) selection is done by "RCSO" signal.

J) NMI Controller.

This circuitry is to send a NMI (Non Maskable Interrupt) signal to the CPU when it detects a memory parity error or SOS7 Interrupt. Par i ty detection is controlled by PB4 bit of the PPI. If the PB4 is "0", it can detect an error but if the PB4 is "1", it can not detect an error. The output of the NMI is controlled by NMI register. If "1" is set to NMI register, the output is enable but if "0" is set, the output is disable. The NMI reg ister is reset to "0" when power is turned on, and it is set by writing "SOh" to I/O address "OAxh" (x:don't care) . It is also reset to "0" when "0" is written to I/O address "OAxh".

A-lO

Clear Mask

Set Mask

* When Power On Reset. * When "OOh" is written to I/O address

"OAxh".

* When "80h" is written to I/O address "OAxh".

Note: When the system is 256 KB memory type, par i ty check is not performed. If the system has expansion memory unit, parity check is performed. The parity generator is contained within the Bus Controller GA, and the parity bit RAI.'1 is contained within the expansion memory board. Error detecting' function is inhibi ted when the RAM switch is set to 256 KB memory size.

10) Keyboard (K.B.) Data Contro11er.

This circuitry is to receive bit-serial data from the K.B. controller (80C49), then the data is converted to parallel data. If the PB7 is "0", the converted parallel data is enabled to be output to the PA but if the PB7 is "1", the output is disabled and K.B. data is cleared. When the PB6 is "0", K.B. clock is inhibited but if the PBG is "I", it becomes to be enabled. The K.B. data is composed of 8 bit data with a leading start bit total of 9 bits. When the circuitry receives one byte data from the K.B. controller, then it inhibits to receive any more data and issues interrupt signal (IRQl). The latch timing of each data bit from the K.B. controller is at a time of when K.B. clock is low and rising point of second DMA CLK pulse.

A-II

11) Circuitry Compatible to 8255.

This circuitry is compatible to intel 8255 (PPI) chip. It contains Port-A, B, C and mode control register.

A). Port A (I/O address = "060h"). Data setting to the register is performed by writing to the I/O address "060h". Getting the data from the register is performed by reading the same address after setting "0" to bit 4 of the mode register. Bit 4 of the mode register is usually set to "1" (when power on reset.) and the following data is gotten when read operation is executed.

h w en Mode Req. 1t 4 =11 1 " Bit PB7="O" PB7="l"

PA 0 I 1 N 2 Input P 3 Keyboard U 4 Data T 5

6 7 I)

B). Port B (I/O address = 10Glh"). Data setting to the register is performed by wri ting to

-the I/O address "06lh". Getting the data from the register is performed by reading t~e same address. The meaning of each bit of the register is as follows.

Bit Description PB 0 + Timer 2 qate speaker

a 1 + Speaker data U 2 Not used T 3 Read Hiqh/Low switch P 4 - Enable RAM parity check U 5 - Enable I/O channel check T 6 - Hold keyboard CLK low

7 - (Enable keyboard), + (CLR K. B. )

A-l2

Each bit of the register (PC bit) after power on reset is as follows.

C). Port C (I/O address = "062h") Data setting to the register is performed by writing to the I/O address "062h". Getting the data from the register is performed by reading the same address when bit 0 (PCO-3) and bit 3 (PC4-7) of the mode control register are set to "0". Bit 0 and 3 of the mode register are usually set to "1" (when power on reset.) and the following data is gotten when read operation is executed.

I N P U T

*SWI SWI

0 1

*SW3 SW2 , SW3 SW2

0 0 0 1 1 0 1 1

h w en d Mo e Req. 1t , = b' 0 3 "1" Bit PB3="0" PB3="1"

PC 0 "1" (Fixed) "0" (Fixed) 1 87 install (*SWl) "1" (Fixed) 2 RAM size 0 (*SW2) Drive 0 (*SW4) 3 RAM size 1 (*SW3) "0" (Fixed) 4 + Speaker drive signal 5 + Timing channel 2 out 6 + I/O channel check 7 + RAM parity check

.8087 Install 87 is not installed 87 is installed

Memory Size 256 KB 384 KB 512 KB 640 KB

A-13

*SW4

o = ON 1 = OFF

INumber~Of FeD

D). Mode Control Register (I/O address = "063h"). This register is set as follows by writIng the data "99h" or "FFh" to the address "063h" or power on reset.

Bit 7 6 5 4 3 2 1 o State 1 x x 1 1 x x 1

x: don't care

Bit State Description 0 PC latch data (PCO-3) is selected as

0 read data of PCO-3. 1 SW data is selected as read data of

PCO-3. 0 PC latch data (PC4-7) is selected as

3 read data of PC4-7. 1 Status information is selected as read

data of PC4-7. 0 PA latch data is selected as read data

4 of PA. 1 K.B. data is selected as read data of

PA. 0 -----------

7 1 Enables to set mode control register. Resets PortA, PortB, PortC.

A-14

APPENDIX B

I/O Controller GA (Gate Array)

The I/O Controller Gate Array is aI, 500 gate flat package type with 100 lead chip. Two I/O Controller Gate Arrays are used on the system PCB. It pritends as I/O Decoder Gate Array or Bus Driver Gate Array by selecting the voltage level of 50 pin of the GA.

1) I/O Decoder GA

The I/O Decoder GA is to decode I/O chip selection. It is composed of Printer port, precompensation circuit for FDD write data and DMA request signal delay circuit.

2) Bus Driver GA

The Bus Driver GA is composed of data busses and address busses between the CPU and rnemory,I/O devices.

80 51

81

100 31

1 30

B-1

Fi~r~"a-l I/O Qecoder GA BloCk Diagram

I/O Control Signals ROMC so"" INTAO IORD20 IOWR20 > EFDAD FOIRCI OMAENI ON3F FO

A091-AOll, MBI

r~l.st'r oACK20 EFOSLl FoC ITI FOCRQl

FOO Cont

FOD Writ e Data AFoCWDI

s" .. 1 J FOCWEl E::. SCKFDI PSO PSI

Control

FSTEPI

PRT/FOO Status RSLI Nl RATFDI I SLCll IPEl I ERRO IACKO >- t:: DSKCO IB SYI , F071-FoOl

RESETO IOBOSO="Low·

1/0 Decoder

FoO Control

r--'" (Reg.)

RESET t

f FDo

1- Wr i te I==::. Precompensation

Prlnter Data

~ Reg.

RESET t

:-- Printer Control

;:=:. (Reg.) --RESET I

B-2

I' I/O Control Signals OMAC SO INTCSO PI TC SO PPICSO PAGWRO NM I RGO TURBOO MOMSLO 100lRI 10oENO FooENo FOCC SO 232SLO 232ENO

FDD Control Si gnals FoAK Tl FOACKO MONBI MONAI OSELBI OSELAI FRSTI I RQ61 OR021

FDD Write dat a FOCWOl

PRT Write Data OP 070-0P 000

I R071 I P INTI

PRT Status

====>USLINI AUTFOI STROBl

'""----> MLPX. I

I/O Decoder GA Interface Signal


1 I ROMCSO ROM select signal. 2 0 PPICSO 8255 (compatible circuit) register select

signal. This signal is active when address is 060h-07Fh.

3 VCC +5v 4 GND Ground 5 0 PAGWRO DMA page register set signal.

This signal is active when (080h-09Fh). lOW is made.

6 0 TURBOO TURBO register (FAST/SLOW) set signal. This signal is active when address is OEOh-OFFh.

7 I TCO Terminal count signal from 8237. 8 I DACK20 ACK siqnal of channel 2 of DMA. 9 I INTAO Interrupt acknowledge signal from the

Bus Controller GA. 10 0 DMACSO DMAC (82C37) select signal. This signal

is active when address is O-OlFh. 11 0 PITCSO 82C53 select signal. This signal is

active when address is 040h-05Fh. 12 0 INTCSO 82C59 select signal. This signal is

active when address is 020h-03Fh. 13 0 232ENO Bus enable signal to the Real Timer and

RS232C.This signal is active when Real Timer or RS232C is selected.

14 0 FDDENO Printer/FDD data bus enable siqnal. 15 - GND Ground 16 0 IRQ7l Pripter interrupt signal. This signal is

sent to IRQ7 pin of the 8259. 17 0 IRQ6l FDD interrupt signal . This signal is

sent to IRQ6 pin of the 8259. 18 0 DRQ2l DMA request signal. This signal is sent

to 8237 (DMAC) . 19 I ON3FFO This signal changes the address of RS232C

reqister and MODEM register. 20 I DSKCO Disk chanqe siqnal from the FDD. 21 I A09l A09l-AOll,AOBl are address lines which

are used to decode a I/O address. Address line bit 9.

22 I A08l Address line bit 8. 23 I A07l Address line bit 7. 24 I A06l Address line bit 6. 25 I A05l Address line bit 5. 26 I A04l Address line bit 4. 27 I A03l Address line bit 3.

B-3

[/0 Decoder GA Interface Signal (continued)


28 NO USE (Open) 29 NO USE (Open) 30 I AOll Address line bit 1. 31 0 MOMSLO MODEM register select signal.

When ON3FFO="High" , •.• 3F8h-3FFh. When ON3FFO="Low" , .... 2F8h-2FFh.

32 0 232SLO RS232C register select signal. When ON3FFO="High" .... 2F8h-2FFh~ When ON3FFO="Low" .... 3F8h-3FFh.

33 I PRTINO Ground 34 I EFDAO FDD drive number assignment signal.

i External FDD is assigned to the drive #1,

I when this signal is "Low" •

35 I A02l Address line bit 2. I 36 I RESETO Reset signal. This signal is active low. I I 37 I EFOSLI Printer/External FDO switching signal. I

If this signal is "high", the PRT/FOO connector is reserved for FDD interface.

38 I $CKFOI Same clock signal to the clock signal sent from ·the VFO to the FDC.

39 0 FOCCSO FOC chip select signal. , 40 GNO Ground

41 I FOCITI FOC interrupt signal. This signal comes from INT pin of the FDC.

42 0 NMIRGO NMI register set signal. This signal is active when ( OAOh -0 BFh) . lOW is made.

43 0 FOAKTI This signal goes to terminal pin of the FOC. (termination of R/W operation)

44 0 FOACKO Response signal to DMA request signal from the FOC. This signal is sent to the FOC.

45 I FOCRQl OMA cycle request siqnal from the FOC. 46 0 FRSTI FOC reset siqnal. 47 I FOIRCI FOO seek direction siqnal from the FOC. 48 I IBSYI Busy status from the Printer. 49 I/O F07l Local data bus for the Printer/FDD bit 7. 50 I IOBUSO Function select signal of the GA.

When this signal is high, the GA acts as I/O decoder.

51 I RATFOI Wraparound signal from the Printer control register.

52 I RSLINI Wraparound signal from the Printer control reqister.

B-4

I/O Decoder GA Interface Signal (continued)


53 VCC +5v 54 GND Ground 55 I IERRO Error status from the printer. 56 I IACKO ACK siqnal from the Printer. 57 I ISLCTI Status signal from the Printer. 58 I IPEI Status siqnal from the Printer. 59 0 AUTFDI Printer control signal from the Printer

control reqister. 60 0 STROBl Printer control signal from the Printer

control reqister. 61 0 SLINI Printer control signal from the Printer

control reqister. 62 0 OPDOO Printer data bit O. (from PRT data req. ) 63 0 OPDlO Printer data bit l.(from PRT data req. ) 64 0 OPD20 Printer data bit 2. (from PRT data req. ) 65 GND Ground 66 0 OPD30 Printer data bit 3.(from PRT data req. ) 67 0 OPD40 Printer data bit 4.(from PRT data req. ) 68 0 OPD50 Printer data bit 5.(from PRT data req. ) 69 0 OPD60 Printer data bit 6. (from PRT data req. ) 70 0 OPD70 Printer data bit 7.(from PRT data req.) 71 I/O FDOI Local data bus for the PRT/FDD bit O. 72 I/O FDll Local data bus for the PRTLFDD bit 1. 73 I/O FD2l Local data bus for the PRT/FDD bit 2. 74 I/O FD3l Local data bus for the PRT/FDD bit 3. 75 i/O FD41 Local data bus for the PRT/FDD bit 4. 76 I/O FD5l Local data ·bus for the PRT/FDD bit 5. 77 I/O FD6l Local data bus for the PRT/FDD bit 6. 78 VCC +5v 79 GND Ground 80 0 PINTI Printer control signal from the Printer

control register. 81 0 DSELAI Drive #1 select signal to the FDD. 82 0 MONAI Moter on siqnal to the FDD drive #1. 83 0 DSELBI Drive #2 select si~nal to the FDD. 84 0 MONBI Motor on siqnal to the FDD drive #2. 85 I FSTEPI Step pulse to the FDD. 86 I DMAENI DMA cycle indicatinq siqnal. 87 I IORD20 I/O read command. 88 I AOBI Address line bit O. 89 I IOWR20 I/O write command. 90 GND Ground

B-5

I/O Decoder GA Interface Signal (continued)


91 I CHENG FDD write precompensation control signal. This signal is fixed to low for the TIlDa PLUS system.

92 I NO USE Ground 93 I NO USE Ground 94 0 FDCWDI FDD write data. 95 I PSI FOD write precompesation control signal.

This signal is fixed to low for the TIIOO PLUS system.

96 I PSO FOO write precompesation control signal. This signal is fixed to low for the TIIOO PLUS system.

97 I AFDCWDI FDD write data from the FDC. 98 0 FOCWEI FDD write enable signal from the FDC. 99 0 IODENO I/O data bus enable signal to the Bus

Driver GA. 100 0 IODIRI I/O data bus direction signal to the Bus

Driver GA. This signal is low when I/O read operation.

B-6

Bus Driver GA (Gate Array)

The function of Bus Driver GA is implemented in the I/O Control GA. When the lOBUS (50 pin) is set to Ground, the I/O Control GA acts as the Bus Driver GA and following signal names and their functions are applied to the GA.

B-7

<

Figure B-2 Bus Driver GA Block Diagram

A0191-Ao161 19 -16

RCV

------ 15-0 Ao151-AoOol

"/ xcv ~

r-

MOP HI HOPLl

b PAREROI PARERll

Control Signals CALENI HLoAl AoSTBl BWoIRl WOLA Tl BoL ENO WoLENO 1001 Rl 100ENO BWHENO MEWEO lOBUS

RFRQl

19-16

La tc h 15-8

-----.../

Latch 7-0

I- 15-B

~ "l,ot

15-B Se I ec t

7-0 Se I ec t

/<==;""

>

::..:oA.:..::C..:.:..;KO::..;:O~ _______ ~.1 FIt

B-8

A19-A16

XMT

-----. A15-A8 Se I ec t XMT

r-" ------- --.--- Al-AO Select XMT

-.."

AoOBI 7-0 OMA071-oMA041

RCV

fL ------oHA031-oMAOOl

XC V

~""h 11 r-"'"

10071-10001 XC V

lL SY071-SyoOI

XC V < Selectr== I=-r k-

Latch WJ Co.tro 1 S1 9na 15

HOC SLO c:::=:=:=:=:::» 0 lOS LO

TIMSEO

Where RCV XMT XC V F IF

Receiver Transmitter Transceiver Flip-flop

oRQO 1

>

Bus Driver GA Interface Signal


1 0 AOll A15l-AOOl are least significant l6-bits of adddress lines from this GA. Address line bit 1.

2 0 AOOI Address line bit O. 3 VCC +5v 4 GNO Ground 5 0 PAREROl Parity error of address lines A015l-A008l.

It is active hiqh. 6 I/O 10001 10D71-IOOOl are bidirectional 8-bit data

bus. Data is output when IOOIR1.I00ENO. Bidirectional data bus line bit O.

7 I/O 10011 Bidirectional data bus line bit 1. 8 I/O 10021 Bidirectional data bus line bit 2. 9 I/O 10031 Bidirectional data bus line bit 3.

10 I/O 10041 Bidirectional data bus line bit 4. 11 I/O 10051 Bidirectional data bus line bit 5. 12 I/O 10061 Bidirectional data bus line bit 6. 13 I/O 10071 Bidirectional data bus line bit 7. 14 I ME WE 0 WE timinq siqnal for the system RAM. 15 GNO Ground. 16 I BWHENO Bus enable signal. This signal is used

with BWDIRI signal. When BWHENO.BWDIRl, A015l-AD08l ~ SY07l-SYDOl(orl007l-IOO01). When BWHENO .BWDIR1, A015l-AD08l ~ SYD7l-SYD01(orI007l-IOO01).

17 I BWOIRI Bus direction signal. This signal becomes low while CPU/DMA-I/O read cycle.

18 I BOLEN 0 Bus enable signal. This signal is used with BWDIR1. When BDLENO.BWDIRl is made, A007l-ADOOl -. SY071-SYD01(orI007l-I0001) . When BDLENO.BWOIRl is made, A007l-ADOOl ~ SYD7l-SYD01(orI007l-IOO01).

19 I WDLENO This signal is enable signal to send data which is latched by WDLATl signal to the AD07l-ADOOl.

20 I WDLATl Latch signal for the data from SYD7l-SYo01 or 10071-10001.

21 I HLOAI This signal is low when it is CPU mode, and high when it is DMA mode. When Low: AD19l-AOOOl -- A19l-AOOI. When high: 10071-10001 -- A15l-A08l

DMAD7l-0MADOl - A07l-AOOl.

B-9

Bus Driver GA Interface Signal (continued)


22 I CALENI Data on the AD19l-ADOOl is latched at the trailinq edqe of the CALENI.

23 0 A131 Address line bit 13. 24 0 A14l Address line bit 14. 25 0 A15l Address line bit 15. 26 0 A16l A19l-A16l are most significant 4-bits

of adddress lines from this GA. Address line bit 16.

27 0 A17l Address line bit 17. 28 Vcc +5v 29 GND Ground 30 0 A19l Address line bit 19. 31 I RFRQl Memory refresh signal. This signal makes

DRQOl signal to be high at the leading edqe of RFRQl siqnal.

32 0 A02l Address line bit 2. 33 0 A03l Address line bit 3. 34 0 A04l Address line bit 4. 35 0 A051 Address line bit 5. 36 0 A06l Address line bit 6. 37 0 A07l Address line bit 7. 38 O· A08l Address line bit 8. 39 0 A09l Address line bit 9. 40 GND Ground 41 0 AlGI Address line bit 10. 42 0 AlII Address line bit 11. 43 O' A12l Address line bit 12. 44 I DACKOO When memory refresh cycle, this signal

becomes to be low and it makes the DRQOl to be inactive.

45 I ADSTBI Latch signal for the data on IOD71-IOD01. The data is latched at the trailing edge of ADSTBI siqnal.

46 0 DRQOl DMA request (Refresh request) siqna1. 47 I/O MDPLI Parity bit for AD07l-ADOOl. 48 I/O MDPHI Parity bit for AD15l-AD08l. 49 I ADOBI System address bit O. 50 I lOBUS Function select signal of the GA.

When this signal is high, the GA acts as I/O decoder. When this signal is low, the GA acts as Bus driver.

51 0 A18l Address line bit 18.

B-lO



52 I/O DMADOI DMAD3l-DMADOl are bidirectional bus. Data direction on the bus is depend on level of HLDAI. When HLDAl=low: AD03l-ADOOl are output to the bus. When HLDAl=high: Data on the bus is input to the GA, then output to A03l-AOOl.

53 VCC +5v 54 GND Ground 55 GND Ground 56 0 PARERll Parity error line of AD07l-ADOOl.

When this siqnal is hiqh, parity error. 57 I IODENO I/O data bus (IOD7l-IODOl) enable signal.

This signal is used with IODIRI signal. When IODENO.IODIRI is made, IOD7l-IODOl are used as output lines. When IODENO.IODIRI is made, IOD7l-IODOl are used as input lines.

58 I IODIRI I/O data bus (IOD7l-IODOl) direction signal. This signal is used with IODENO signal.

59 0 HDCSLO HDC select signal. This signal is issued when the I/O address is lFOh-lFFh.

60 0 TIMSEO Timer IC (TC8250) select signal. This signal is issued when the I/O address is 2COh-2DFh.

61 0 DIOSLO Display controller select signal. This signal is issued when the I/O address is 3DOh-3DFh.

62 I/O SYDOI SYD7l-SYDOl are bidirectional a-bit data bus. When BWOIRl.(BDLENO+BWHENO) is made, they act as output lines. Bidirectional data bus bit O.

63 I/O SYDll Bidirectional data bus bit 1. 64 I/O SYD2l Bidirectional data bus bit 2. 65 GND Ground 66 I/O SYD3l Bidirectional data bus bit 3. 67 I/O SYD4l Bidirectional data bus bit 4. 68 I/O SYD5l Bidirectional data bus bit 5. 69 I/O SYD6l Bidirectional data bus bit 6. 70 I/O SYD7l Bidirectional data bus bit 7. 71 I o MAD 71 DMAD7l-DMADOl are address lines in DMA

mode. DMA address line bit 7.

B-ll



72 I DMAD61 DMA address line bit 6. 73 I DMAD51 DMA address line bit 5. 74 I DMAD41 DMA address line bit 4. 75 I/O DMAD31 DMAD31-DMADOl are bidirectional bus.

When HLDA1=low, they act as output lines. The output data are AD031-AD001. When HLDA1=high,they act as input lines. Bidirectional bus bit 3.

76 I/O DMAD21 Bidirectional bus bit 2. 77 I/O DMADll Bidirectional bus bit 1. 78 VCC +5v 79 GND Ground 80 I/O ADOOl AD151-AD001 are bidirectional address data

lines between the CPU and this GA. Address data line bit O.

81 I/O AD011 Address data line bit 1. 82 I/O AD021 Address data line bit 2. 83 I/O AD031 Address data line bit 3. 84 I/O AD041 Address data line bit 4. 85 I/O AD051 Address data line bit 5. 86 I/O AD061 Address data line bit 6. 87 I/O AD071 Address data line bit 7. 88 I/O AD081 Address data line bit 8. 89 I/O AD091 Address data line bit 9. 90 GND Ground 91 I/O ADIOl Address data line bit 10. 92 I/O ADlll Address data line bit 11. 93 I/O AD121 Address data line bit 12. 94 I/O AD131 Address data line bit 13. 95 I/O AD141 Address data line bit 14. 96 I/O AD151 Address data line bit 15. 97 I AD161 AD19-AD16 are address lines from the CPU.

Address line bit 16. 98 I AD171 Address line bit 17. 99 I AD181 Address line bit 18.

100 I AD191 Address line bit 19.

B-12

APPENDIX C

Display Controller GA (Gate Array)

The Display Controller Gate Array is a 5,000 gates, CMOS, 100-pin flat package type chip. It contains Color Graphics Adaptor which is able to control external CRT disply as well as internal plasma display. The Display Controller Subsystem can control following three types of displays. The signal name and it's meaning of each pin are described in this section.

Note:

A). 640 x 400 dot Plasma Display.

B). 640 x 200 dot LCD (Liquid Crystal Display).

C). 640 x 200 dot CRT (Cathode Ray Tube) Display.

External CRT display unit and internal Plasm~~fsPlay unit could not display a screen at same time. • You can select current display unit from them by keyboard operation.

Ctrl + Alt + Horne Internal display unit is selected.

Ctrl + Alt + End External display unit is selected.

The Display Controller GA is composed of following functions.

1) Plasma/LCD/CRT control function. This function is compatible with the MC6845 (CRTC) on software operation.

2) Attribute handling function.

3) Interface to CPU (I/O bus).

4) Interface to V-RAM, CG-ROM (Character Generator ROM).

80 51

81 50

100 ~.rr~----------,.~ 31

1 30

C-l

Figure C-l Display Controller Subsystem (OCS)

I/O bus A131-A061

R Al 21- R AO 51 I/O signals (8 )

V (23) RASELO " SYD71-SYD01 (1) Multlplexer

AO 51-AO 11, AOB1,A141 URA041-URA001 DIOSLO (5 ) IORD10 IOWR10 Display V-RAM v DMESLO Controller Control (Ad d re s s) MRDO GA (4) V-RAM MWRO (lOO-pin ( I/O) IORDY1 package) AT71-AT01 (' 1\ RESETO (8 )

" TEST CC71-CC01 (3) (8)

SB E1 ( 1 ) CGAXI ~ GOF1

l (1) ( 1 ) Latch

OSCI41 ~ ( 1) OSC171

., (1) ROM Address

PDPO ,.

(1) (6 ) FLTDSLI (1) CFNO

;:. ( 1 ) ~ ;0 C ER OMO (Ad d res s)

GND (1) , C G -R 0 M ( 4) (Out)

Vcc CG71-CG01 ( 4) (8)

(9 )

Video >1 Ex terna I Signals IDisplay

Buffer IPlasma or LCD I

C-2

Interface Signal


1 I CG3l Character generator output signal bit 3. 2 I CG41 Character qenerator output signal bit 4. 3 I VCC +5V 4 I CG5l Character qenerator output signal bit 5. 5 I CG6l Character generator output siqnal bit 6. 6 I CG7l Character qenerator output signal bit 7. 7 I CEROMO Chip enable signal for CG-ROM (Character

Generator - ROM). 8 I CG2l Character generator out~ut signal bit 2. 9 I CGll Character qenerator output signal bit 1.

10 I CGOI Character qenerator out:Qut signal bit O. 11 0 RSAOI Raster scan address bit O. 12 0 RSAll Raster scan address bit 1. 13 0 RSA2l Raster scan address bit 2. 14 0 RSA3l Raster scan address bit 3. 15 GND Ground 16 I SBE1 Reserved for LCD.(Ground) 17 0 INTEN1 Intensified font select signal.

(single dot/double dots character) 18 0 CGMOI Plasma font selection.

(8x8/8x16) 19 0 CGAX1 CG address latch. 20 0 RASELO Refresh address selection 21 0 RA12l Refresh address bit 12. 22 0 RA1l1 Refresh address bit 11. 23 0 RAlOl Refresh address bit 10. 24 0 RA091 Refresh address bit 09.

·25 0 RA08l Refresh address bit 08. 26. 0 RA07l Refresh address bit 07. 27 0 RA061 Refresh address bit 06. 28 I VCC +5V 29 0 RA051 Refresh address bit 05. 30 I OSC14l Clock 14.31818 MHz for the video signal

of CRT display. 31 I DIOSLO Display I/O selected. Access signal to

the I/O port of the GA. 32 I DMESLO V-RAM access signal for CPU or DMAC. 33 I/O SYD7l Data bus bit 7. 34 I/O SYD6l Data bus bit 6. 35 I/O SYD5l Data bus bit 5. 36 I/O SYD41 Data bus bit 4. 37 I/O SYD3l Data bus bit 3. 38 I/O SYD2l Data bus bit 2. 39 I/O SYD1l Data bus bit 1.

C-3


Pin I/O Signal Name Oescription

40 GNO Ground. 41 I/O SYOOI Oata bus siqnal bit O. 42 0 IOROYI I/O ready signal. 43 I RESETO GA reset siqnal. 44 I A051 CPU address bit 5. 45 I A041 CPU address bit 4. 46 I A031 CPU address bit 3. 47 I A021 CPU address bit 2. 48 I AOll CPU address bit 1. 49 I A141 CPU address bit 14. 50 I MWRO Memory write signal. (for V-RAM write) 51 I MROO Memory read siqnal. (for V-RAM read) 52 I IOROIO I/O read signal. It read out I/O port

data to the data bus BOOO-B007. 53 I VCC +5v 54 I IOWRIO I/O write signal. It write data on the

data bus to the I/O port. 55 I AOBI CPU address bit O. 56 I POPO Plasma display panel select. 57 I GOFI GA off. If this signal is high, the GA

becomes to be disable. 58 TEHI Ground 59 TFUI Ground 60 TCNI Ground ~:;~ 61 0 BFRO Video siqnal. lAt.'" J, 62 0 FRHVI Video signal. ",,",,~ ~ '..3J sync. signal for

composite CRT display. 63 0 FPVSl Video signal. Vertical ,sync. signal for

plasma/RGB CRT display. 64 0 SXVDl Video siqnal. 65 0 GND Ground. 66 0 LPHSI Video signal. Horizontal sync. signal for

plasma/RGB CRT display. 67 0 DlRl Video signal. Red signal for RGB CRT

display. 68 0 D2Gl Video signal. Green signal for RGB CRT

display. 69 0 D3Bl Video signal. Blue signal for RGB CRT

display. 70 0 0411 Video signal. Intensity signal for ~C.~T 71 I CHFONTO Chanqe character font siqnal. 72 I FLTDSLI Flat display selected. It changes internal

/external display. 73 I OSC17l Clock 17.5 MHz. 74 0 CEHO Chip enable high. chip selected signal

for the V-RAM.

C-4



75 0 WRCCO Write character code. It is used with chip enable signal to write the V-RAM. (evven address)

76 0 WRATO Write attribute data. It is used with chip enable signal to write the V-RAM. (odd address)

77 0 CELO Chip enable low. It is V-RAM selection signal.

78 Vcc +5v 79 0 URAOOI CPU/Refresh address bit O. 80 0 URAOll CPU/Refresh address bit 1. 81 0 URA02l CPU/Refresh address bit 2. 82 0 URA03l CPU/Refresh address bit 3. 83 0 URA04l CPU/Refresh address bit 4. 84 I/O ATOI Attribute data bit O. 85 I/O ATll Attribute data bit 1. 86 I/O AT2l Attribute data bit 2. 87 I/O AT3l Attribute data bit 3 88 I/O AT4l Attribute data bit 4. 89 I/O AT5l Attribute data bit 5. 90 I/O GND Ground 91 I/O AT6l Attribute data bit 6. 92 I/O AT7l Attribute data bit 7. 93 I/O CCOI Character code data bit O. 94 I/O CCll Character code data bit 1. 95 I/O CC2l Character code data bit 2. 96 I/O. CC3l Character code data bit 3. 97 I/O CC4l Character code data bit 4. 98 I/O CC5l Character code data bit 5. 99 I/O CC6l Character code data bit 6.

100 I/O CC7l· Character code data bit 7.

C-5

Display Controller Subsystem

Display Controller Subsystem (DCS) is composed of following components.

Table C-l

Display Controller GA CMOS 5 KG lOO-pin flat Packaqe

Video-RAM 32 KB 64 KSSRAMx4

CG-ROM 32 KB 256 K ROMxl

OSC CPU-CLK 14.31818 MHz Other 17.5 MHz

Others Multiplexer 74HC157x2 Latch 74HC273xl Display Buffer

Generally B stands for Byte, and b for bits.

Table C-2 is the operation mode of the DCS of internal plasm~/L..':'1) display and external CRT di~play.

Table C-2 Leo£) /

Operation Plasma (Pixels) ExLeJ::ual CRTCPixels) Mode Resolution Character Resolusion Character

Box Box 40x25 TEXT 320x400 8x16 320x200 8x8 80x25 TEXT 640x400 ·8x16 .640x200 8x8 320x200 GRAPH 320x200 8x8 320x200 8x8 640x200 GRAPH 640x200 8x8 640x200 8x8 640x400 GRAPH 640x400 8x16 not supported

C-6

Signals

The DeS has follwing groups of signals.

o I/O Interface Signals (23 lines)

o V-RAM Signals (34 lines)

o Character Generator (CG) Signals (16 lines)

o Video Signals (9 lines)

o Display Mode Select Signals (3 lines)

o Clock Input (2 lines)

o Miscellaneous Signals (5 lines)

1) I/O Interface Signals (23 lines)

DIOSLO: Display I/O Select (Input) This signal allows the CPU to read or write data from/to I/O port within the GA when this signal is low. IORDIO or IOWRIO should be low as well as DIOSLO for read or write operation to I/O port within the GA.

IORDIO: I/O Read (Input) I/O port data within the GA is transferred to the CPU through the SYD71-SYDOI when this signal is low and DIOSLO is low too.

IOWR10: I/O Write (Input) Data from the CPU is transferred and written to the selected I/O port within the GA through the SYD7l-SYDOI when this signal is low and DIOSLO is low too.

DMESLO: Display Memory Selected (Input) This signal allows the CPU to read or wr i te data from/to the Video RAM when this signal is low. MRDO or MWRO should be low as well as DMESLO for read or write operation to V-RAM.

C-7

MRDO: Memory Read (Input) Read operation to the V-RAM is executed transferred to the SYD7l-SYDOl when this DMESLO is low too.

MWRO: Memory Write (Input)

and read signal is

data is low and

Data from the SYD7l-SYDOl is wr.l.tten to the V-RAM when this signal is low and DMESLO is low too.

A051-AOll,AOBl,A141: CPU Address (Input) These are address data lines from the CPU or DMAC and high level is logical true. A03l-AOll and AOBI are used for selecting one of I/O ports within the GA during read or write operation to the I/O port within the GA. For memory read or memory write operation to the V-RAM, A05l-AOll,AOBl and A14l go through the GA then they are used to selecting memory location of the V-RAM with A13l-A06l.

SYD71-SYDOl: a-bit Data Bus (Input/Output) These are 8-bit data lines and high level is logical true. The data is go through these lines while read/write operation to the I/O port wi thin the GA or read/write operation to the V-RAM.

IORDYl: I/O Ready (Output) It is- ready when this line is high level. - If DMESLO is low (the CPU or DMAC requests V-RAM access), the GA holds this line low level to make the CPU or DMAC to waite until the end of the access. This signal line is held high level usually and it is also high when the CPU reads or wr i tes data from/to the I/O port within the GA.

RESETO: Reset (Input) The GA is reset when this signal line is low level.

C-8

2) V-RAM Signals (34 lines)

URA04l-URAOOl: CPU/Refresh Address 00 - 04 (Input) These lines used to send a part of CPU address and a part of refresh address to the V-RAM. The CPU address is from CPU address lines AOSl-AOll.

RA12l-RAOSl: Refresh Address 05 - 12 (Input) These lines are address lines for the V-RAM refreshment. RAl2l-RA06l as high-order bits of address lines are input to the D-RAM through the multiplexer which has another input of I/O bus address (AI31-A061), while URA041-URAOOI are directly connected input pins of the V-RAM. (see Fig x-I) There are two ways to read or write data from/to the V-RAM. One way is that the CPU reads or writes it from/to the D-RAM through the I/O bus. The other is Display refresh (read on ly) by the GA. The addressing of the each case is shown on the Table x-l.

CELO,CEBO: Chip Enable Low/High (Output) Tt:tese signals are chip-enable signals of the V-RAM, and they are active when low. The block diagram of the V-RAM control signals and logical operation of the signals are shown respecively on the Fig. x-2 and Table x-2. The V-RAM is composed of four 8Kx8bit SRAM (TC5565). CELO address l6KB of two S-RAMs starting from B8000h, and CEHO addresses l6KB of two S-RAMs starting from BCOOOh respectively. The RAMs connected to the data bus of CC7l-CCOl are assigned to even address and the RAMs connected ·to the data bus of AT7l-ATOl are assigned to odd address respectively. For V-RAM refresh, two byte read operation is done always. Whenever the CPU and DMAC reads the data stored in the V-RAM, two RAMs (two bytes) are accessed simultaneously, although only one of the two can be put on the data lines (SYD71-SYDOl) of the I/O bus. CC7l-CCOl are read out to the I/O bus SYD71-SYDOI if AOBI is low, and AT7l-ATOl are read out to the I/O bus SYD7l-SYDOl if AOBl is high. Two RAMs (CC71-CCOI and AT71-ATOl) become to be enable but only one RAM is written when the CPU or DMAC executes write operation.

WRCCO: Write Character Code (Output) WRATO: write Attribute Data (output) They are write enable signal to the V-RAM. Wri te operation into V-RAM is enabled when chip enable signal and one of WRCCO/WRATO to the V-RAM chip are low. It is also executed only when the CPU or DMAC request to write (DMESLO=low and MWRO=low). At this point, one of WRCCO and WRATO becomes low according to the AOBI state. WRCCO becomes low when AOBl is low, and write data on the I/O bus SYD7l-SYDOl is transferred to CC71-CCOI. WRATO becomes low when AOBl is low, and write data on the I/O bus SYD7l-SYDOl is transferred to AT7l-ATOl.

C-9

Table C-3

V-RAM CPU Memory Refresh Pin Signal Address TEXT Mode GRAPH Mode Name Name

CE CEHO/CELO Al4 MAl3 RSAI ------ ----------- ---------- --------------- ---------------

ADl2 RAl21 Al3 MAl2 RSAO ------ ----------- ---------- --------------- ---------------

ADII RAIII Al2 MAll MAll ------ ----------- ---------- --------------- ---------------

ADIO RAIOI All MAIO MAIO ------ ----------- ---------- --------------- ---------------

AD09 RA091 AIO MA09 MA09 ------ ----------- ---------- --------------- ---------------

ADOe RAOel A09 MAOe MAOe ------ ----------- ---------- --------------- ---------------

AD07 RA071 AOe MA07 MA07 ------ ----------- ---------- --------------- ---------------

AD06 RA061 A07 MA06 MA06 ------ ----------- ---------- --------------- ---------------

ADOS RA051 A06 MA05 MA05 ------ ----------- ---------- --------------- ---------------

AD04 RA041 A05 MA04 MA04 ------ ----------- ---------- --------------- ---------------

AD03 RA031 A04 MA03 MA03 ------ ----------- ---------- --------------- ---------------

AD02 RA021 A03 MA02 MA02 ------ ----------- ---------- --------------- ---------------

ADOI RAOII A02 MAOI MAOI ------ ----------- ---------- --------------- ---------------

ADOO RAOOI AOI MAOO MAOO ------ ----------- ---------- --------------- ---------------

WE WRCCO/WRATO AOO -- --

Note: * AI41-AOOI are I/O bus address lines from the CPU.

A051-AOOI and Al41 are input to CPU address input pins of the GA.

* MAI3-MAOO are Refresh Memory Address. They are generated by the 6e 45 compatible circu it wi thin the GA.

* RSAI-RSAO are Raster Scan Address. There are four Raster Scan Address lines « RSA3 (MSB) RSAO ( LSB) ), but only two lower-bi ts are used in graph ic s mode.

C-IO

Figure C-2 V-RAM Control Signals

TC5565 TC5565 8

I/O...----~ I/O~-f--- CC7l-CCOl

WRCCO---o WE 1-----0 WE r-o CE -0 CE

TC5565 TC5565 8

I/O - I/O 1----+--- AT7l-ATOl

-0 WE -0 WRATO -- WE r-o CE -0 CE

CELO CEHO

Table C-4 V-RAM Control Signals

V-RAM CPU Address Display Control .Signal Read Write Refresh

CELO if Al4l=low, if Al4l=low, if MAl3l or RSAl Low Low =Low, Low

CEHO if Al4l-high, if Al4l-high, if MAl3l or RSAl Low Low =Hiqh, Low

WRCCO High if AOBl=Low, High Low

WRATO High if AOBl=High, High Low

C-ll

RASELO: Refresh Address Selection (Output) This signal is an input selection signal to the V-RAM address multiplexer. If it is low, the display refresh address lines (RAI21-RA051) are selected as V-RAM address. If it is high, the I/O bus address lines are selected as V-RAM address.

CC7l - CCOI: Character Code Data Bus (In ut/Out ut) These lines are data bus from to the even address V-RAM. The even address V-RAM is used to store the character codes in TEXT mode.

AT7l - ATOI: Attribute Data Bus (Input/Output) These lines are data bus from/to the odd address V-RAM. The even address V-RAM is used to store the attribute codes in TEXT mode.

3) Character Generator (CG) Signals (16 lines)

CGAX1: CG Address Latch (OUtput) The character code from the V-RAM (CC71-CCOI) is set to the external latch circuit by this signal. The set timing of the external latch circuit is at the raising edge of this signal. The output from the external latch circuit is used for the address of CG-ROM. The character code is 8-bi t code, and it can s~lects one of 256 characters.

ROM Address (Output) Following 6 signals are also used as CG-ROM address as well as the character code mentioned above.

CGKOI : Plasma Font Selection. INTENl : Intensified Font Selection. RSA3l-RSAOl : Raster Scan Address.

Table x-3 and Figure x-3 shows ROM address assignment. CG-ROM (32 KB) has following character fonts.

8x8 single dot chara9ter set 8x8 double dot character set 8xl6 single dot character set 8xl6 double dot character set

C-12

The plasma display can not display intensif ied character like CRT display, thus double dot character is used for distinction between normal character and intensified character. INTENl signal is used to select single or double dot character.

INTENl=Low --- Single dot character. INTENl=High -- Double dot character.

CGMOl signal is used to select 8xl6 or 8x8 character font. CGMOl=Low --- 8xl6 character. CGMOl=High -- 8x8 character.

RSA2l-RSAOl and RSA3l are Raster Scan Address. The RSAOl is the Least Significant Bit (LSB).

CEROMO: Chip Enable for ROM (Output) It makes the CG-ROM to be enable for access.

CG7l - CGOl: Character Generator Output Signals (Output) These lines are output signals of the CG-ROM. The data addressed by ROM address is read out to the CG7l-CGOl lines, when CEROMO=O.

RSA3l RSA2l RSAll H L L H L L

-H L H H L H H H L H H L H H H H H H

RSAOl L H L H L H L H

C-l3

Raste r o 1 8 x 8 2 _Character ____ _ 3 4 5 6 7

~l byte---

Figure C-3 ROM Address Assignment

RSA3l RSA2l RSAll RSAOl H L L L H L L H H L H L H L H H H H L L H H L H H H H L H H H H L L L L L L L H L L H L L L H H L H L L L H L H L H H L L H H H

Raster o 1 2 3 4 5 6 7 8 9

10 11 12 13 14 15

----------------

8 x 16 -- Upper

8 x 16 - Lower -

- 1 byte--

Table C-5 ROM Address Assignment

ROM Add.Pin GA Siqnal AD14 +VCC AD13 CGMOl AD1·2 RSA3l ADll INTENl AD10 CC7l AD09 CC6l AD08 CC5l AD07 CC4l AD06 CC3l ADOS CC2l AD04 CCll AD03 CCOl AD02 RSA2l ADOl RSAll ADOO RSAOl

C-14

4000h

4800h

5000h

5800h

6000h

6800h

7000h

7800h 7FFFh

32 KB - ROM 8x16 Single Dot Lower Half 8x16 Double Dot Lower Half 8x16 Single Dot UpEer Half 8x16 Double Dot UEEer Half

8x8 Single Dot

8x8 Double Dot

Note: Addresses Oh-3FFFh of CG-ROM are not used.

I

4) Video Signa1s (9 1ines)

There are 9 video signals which are output from the GA. They are sent to the plasma display or external CRT display. The signals are used in the each unit as shown Table C-6.

Table C-6 Video Signals

GA Signal Plasma Display CRT D1S )lay RGB Composite

LPHSI PHSYO CHSYl FPVSl PVSYO CVSYI FRHVI CHVSYO DlRl PDlO CRVI D2Gl PD20 CGVl D3Bl PD30 CBvl D4Il PD40 CIvl CIvl SXVDl PSCKO CVDl BFRO CBLNKO

5) Display Mode Selection Signals (3 1ines)

CBFONTO: Character Font Change (Input) This signal is to change the font desplayed on the screen. The function of this signal is shown on the Table C-7.

FLTDSL1: Flat Display Selected (Input) This signal is to select one of internal and external display unit. If this signal is high level, the internal plasma display is selected. If this signal is low level, the external CRT display (RGB, Composite) is selected.

PDPO: Plasma Disp1ay Panel (Input) This signal is to specify the type of internal display unit. If this signal is low level, a plasma display unit (640x400 pixels) is used as internal display unit. If this signal is high level, a LCD display unit (640x200 pixels) is used as internal display unit.

Rote: Relation between signals of CHFONTO, FLTOSLl, POPO and character fonts on the screen are shown on the Table C-7.

C-lS

Table C-7

Mode blt 3 of GA Input GA Output Selected Selected attribute CHFO FLTD PDPO INTE CGMO DisolaY Disolay byte NTO SLI Nl 1 Display Display

80x25 0 H H H H H LCD 8x8 Double or 1 H H H t H LCD 8x8 Sinqle

40x25 0 L H H L H LCD 8x8 Sinqle 1 L H H H H LCD 8x8 Double

80x25 0 H H L L L Plasma 8x16 Sinqle or 1 H H L H L Plasma 8xl6 Double

40x25 0 L H L H L Plasma 8x16 Double 1 L H L L L Plasma 8x16 Sinqle

80x25 0 H L x H H CRT 8x8 Double or 1 H L x H H CRT 8x8 Double

40x25 (Hiqh Liqht) 0 L L x L H CRT 8x8 Sinqle 1 L L x L H CRT 8x8 Single

(Hiqh Liqht)

6) Clock Input (2 lines)

OSC14l: Oscillator 14 MHz (Input) This clock is the input signal to generate a video signal for the CRT display. The frequency of the clock must be 14.31818 ~1H z •

OSC171: Oscillator 18 MHz (Input) This clock is the input signal to generate a video signal for the plasma .display. The frequency of the clock must be 17.5 MHz (60Hz).

7) Miscellaneous Signals (5 lines)

GOFl: GA Off (Input) It forces the GA to be disable if this signal is high. It forces the GA to be disable when the other display adaptor is installed in the I/O expansion box and the external display adaptor is used.

SBEl: SBE-LCD (Input) This signal is reserved for LCD display.

C-16

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05~ .- I<I:SEl ~ e" I j.ooo 01. It\) . _ ~~'-- Cf.2

IAI

!;?)----- -

2

TO LED PJ8

(jOt FAST,- . ---- . Qi.1 GREEN .• ' Vcr.. ---___ O~

~~ sfi Atj - - --- .. - =~_- Q~ ~RANGE (i,l) S~U:10... --.--.--.--- ..... _ P4 oRANGE

~- !-Q.IIY_J;!W .. -.. -.--.---- ______ .... .Q1 RED 9) LoWS~I_. ___ -... ----.-- ____ !)!;> RED

(lib FlliFO (G} G~I,.)

115 oRANGE 'd~ SW _ .0.')

3

Vcr:

·, .. ' .. ···M

4 5

~J - - SPKT6£'1D __ ._ l.f0 12 ___ .. __ _

y ~- j"~H --- IQ) 3 09__ CI31

2 y- .J.9.9_ ~~KKI--I.iv 07 R II; -

y 1 MDSL 0 (ijJ

.... -'---. 04/. !~!{TI£i;~ f--'Y!

P09GG P09FF._

SP!f1I.,1f.l ._

_ PO~I)P

0ld 5L srls-EN lC6J

---- I [

In: \'ISEII I'"

(IIFTI\ F:Ii II v

o

@GI.IR-l H _~_~]_J 10K

.-.- --.-----------~------ --.-.- - _ ... --_ .... _ ..... _P(j9EE

. Vec In --;~ @--- -.. ----- t!LSfl.r--l .,h1JRQL @ MIROU _____ . ___ . __ .

.- OUI21 .Q~ __ OR 06

qB) . - 2 lC.(-i~ I

y _.!.L _____ .. _

0 3 I

Y 09 _____

0 2 qW INTO 05 5032

1'" "J-

- P09J ... (§)-... P09HH 2

- - -- ••.. __ ._.1 kJ--31(,) 1

DQ --..!.!

06

--I==~l I y~ - .

0 I I Y 04

0 0 r::~" . 1~IIOK

!YJ YS--c---fR 11 i]-,J L

5EL ClIS7

(~_ ONJFFO @ GND - 5L

q EN ICII _9!

II.?

IU~\'ISEIJ IMTE

Ii!;SU;NEIJ IIY IIIAWIN(; IJATE

2

1R04L. --G'> -~-.--

__ IRQ;,t -- --_._---(5)

_CRTMJL

FLIDSJ"L. __ ~

I. RS232C MoDE "H"(OFF)·-- IRO.3(2FF)

ilL" (ON) --. IRo.4(JFF)

2. MoDEM MoDE

"H" (oFF)--- IR()4(JFF)

"L"(ONI ---IROJ(2FF)

..

A

Ii

c

D

E

F

G

H

J

K

L

A

B

c

IJ

E

F

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J

K

L

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( j?) 1611~: ___ si _ 4i

:--~ ~I--·--:--- -@ at--

68 D7 6':1 6 1.0 5 71. 4 1~ 3 1;J 2 11 I 7S 0

(2)-- J\I~I . __ '" IBi - SI __ in- s~

:::: iti~-===~==i! Iji-- - - 51 !Ji j- --- - - 58

t~)--I(~ji- ------ - 80 W--BHEO

_______ - 19 01 _ __ _____ 88 00 -- BHE

C!)--~m------ ----glls2 w-- SlJ(j---ss- II OJ- ------ ------------ +0

I 2

ICS8

- J4 ~~5~~?'Q_ ------(!..D noMSL)so Ro"1!=NQ_ '4' R~ME -'21 ----- -- - ~

RoME I )2? __ W~~!? _____ @ RAST )27 PI3ASL __ --(6) mAS -i -RAS4! ____ I· RASIl-~----· --j' 31 _

~ --~ ---. -:::- -11 ~~~: I ~ 2'- - -- - OI----(6)

61 WDLATI ____ (ii' WDLAl - - ----- ----. E' NO ~ 62 Wl1L " __ 1

wtllEN )64----swbtR! __ t awDI -GJ--"-- BblE~Q.---,;:;) BIl..HI--·---- - - \€,

66 BWtfENO -- --/2) BWHEN) ---- \!:

I

AOB 37 ADOBL ______ --oo 59 _. ___ CN.~!::'L __ .. _~®

~~E )j9_IQRQ.Q ____ ~) ~o 38 __ H1WRO. __ .. _._ <J)

JoWR )4~ ___ MBI,)SL ---(4) MEn );'i. ___ ty!_WijQ __ @

3

@- GI~l) ______ !U It _br- 02 (~)- l --(Jf, B r 01 __ ._

(GI--- - - -.--- US--b~ userJ -. V~c__ OJ XI (V~ ----.--- _. __

fiI.3IBI8MHz Vcc -8 GND-4

, .. , ... ,.

" 5

_ __ ..QS.1.!~_L ___ . __ QV

-----,------

@-l-- 96 I 2 _ (YJ--Yfc- -----== ~~ TESTI FAST~l---fAS.Il-0.@ lV)------------- -- '" J GATE2 I~ TMGATI (S)

(5) lC20UlI -'1. TC21 92 OSC CPCLK~? __ C-P.!.LCLKI --

OMClK O~ ____ Q.MCLKil...-{l,(J) rnJ (j}_C_A.STL__ 01 TMCL i4... ___ TMtLRi--(!,f}~ _ CAST ------(5)

<a>--_KBCI,.! ____ !3 CASI( _?f> ___ -~~~!-I~~ -(f!~Pll 12- KI CASL[ __ ~S ___ ~ASLEI--{§.l BO\TI - ---------(Jv

(\J)...£P-'-<;'~Q-- 43 KBClK- _Q~ ___ !SBCLK I -T _Nty11RG.9_-=4~r f'1~5CS KBWli- -()~ ___ K.BD!Ai---<a) t _ I~A.Q.YYBO 45- tII~G IRQI 19 IRa I P----<W

([D- TURBoO---,i6- GWI~ t~ - TURBWR SPK 35 SPKDRO -@ @ -DA~I<~g_-=-_===_g~ ~lCK~ ~~ )1-8--t~.TAQ---t.s(l)

- ~ . rjQ.-·-_. __ U6 0 91 __ Rf>!.Q._. ___ 1 _

i tlM'~N_'-______ L .EN "- -j j ___ !l!lYRML_. 1"-J

- PARER" 77 IPAREI

~REROI 16 PAREO VRA~~4-- DM~_~® I -- Hf~(~O""! -- ---- °09- HRa RGT GO ____ .HL_OAL. __ ~ ~4 - IEP

<M-- --- - OROY - -- - - CPADEQ _. __ _ OOE}-JJ----- --- - - - 7

Ot)?i~ -15RDY'---___ . -. - ,36 InDY ©--~ND 89 1871NT MEWEb§1 MEWEL __ {gtJ1

PRDYI-&~-- -- P89Yl --- -- (j) @-EF_Q.-S.t,L ____ c;lJ_IEFOO

RF.\'ISI-:!'OY

CIII,CKI':11 II\'

(t~ PoNCl"O ___________ 148_ ~~-~~---B~~Ul ----~ lID

-- vcc lQI:S._ (YJ ---- --------tR2Jd-

R~\,ISEIJ III\TE

IIESU;NEU IIY

o I

Vee -03,28,53,18

GND-I5,40,65,9Q

l'RINTI'" IIOARII

l'iI~AWIN(; III\TE

.,

MNI~ NMII ill

(J)-~JL_--------~ !3 CJ>--S'!\I4! 2U"

~=~NJ~=-=-~---~~!&3 - ~ (6)_RC~El.-Q ______ A~ - MAS~? MADSI ~)

r·nu-. BUS CNT GA

ISII.IU~WIN(; No. 1"1\;:5 Nn-rEV-MARK

I " TOBHIBA CORPnF1"'TION

A

Ii

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F

G

II

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A

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E

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G 2 3 (V)_Vrr ,.. Syoll 4 5 - t B Ir, . - - ----I~.r)· 9! ·l- .'--"

H,H- . ':;!I -R;'f . __ 4!__ I A i~;)~ .;J! -

I~S7

F'lH/FI1U

- AU'31 21 A'3

([?l.. . ~.~ .. 8 i. :. ~~ ~ Ubi ?l! 6 usi 25 5 o~i 26 4

- lljl 'l7 3 . . 1121 35 2

. iili 30 I (~) ALIBI _ 00 0 q) iiM_"H~L ~ I.lMA @ . ioi~U2o m loRD q) ioWR2lJ 89 loWo (~i>. - 20-.- (JSKCU ___ ._ . . ( DlSK (5)--------

::- IN I An .. ()~<. IN11\ IIUI - -- -M'('Sl) 01 R-MSI I'" Ho ._J_ . ----.- •. ( 0 _ (9)-----

- OI-lJHu.. __ . 19 2321\0 (3)---' ....

- I CO _. ___ . O.?(jlCO <1J -- t)At~ 20 .. . oo( DACK2 <:V EFi)~U __ .. ~4. FSW tH) --.- FDCIJI._.. 41 FINT q~ --FDCRQ.I _____ 45 FORO. Q?)------ - .....

. !CI~FU.I -- .;Ja ICl<m (!~--FS1H'1 e~ STEP (I'.h -.-. l!1 ,~ FDlRC! --- -- FOCoR (g)- --- .-

0;1 Vcc--.-----SO-lIa8USO

n~~s ') !Q_. ___ !.Jtvl.l\C5U ~l_ ISJCS'! 1 ____ PJlCSO - 004,1 15?CS ,-,-~ __ IN1CSO 15\ rr'ICS ,Q~---- !'FJ.CSU --- .. {§) NMlST'4Z----I)!Mlr~GO .. --. - - qYl

lURBW )Q§ _____ '-'JRSnCJ -.-.. '!9> FAGHEG )..Q5 .. ___ ~AGwi~u <19' -.. ... flY>

232SL _)~l----232SL,O 2J2BF. ) -.-

MoDEM ,\JL ___ MPMSLO loom lQO. ____ nmiR I laUEN ') ~9 .. __ JotjENQ

FOBE[)!4 FOCS )J~ ___ .H)CCSO

lie)

u.~- /e1 ®~)

--- (gJ

@)

FDlCI :~ .... -~ --f:~~~~k. _~ -__ . . ~. F[)I\K ~84 ___ MQNe! .. -.- ... --- ~4~i

~g~?~ ~t.-._. ~ __ '.~~~ .. C ijj ~~~~~~ ~~ OSL? 81 _ o.SH.AI._ ._ .. _ .. (!4> oSLI 46 _____ .1:."85.1.1. _____ (12)

FRE ·ii~ .. _._ IRo,qL ------ (Sl _ ma6 - i.B_._ORQ._2J ____ -- (~ lID ORQ.--

H<'J __ ~L. __ _ , n 2 i --!!---r~ it] ------ 0-1 -

iOK

_0__ 15 l!

t?)---SYjOl: _A~ D1

l ~~=-' -.~·n--- __ }l_ ~ ~~~_ j:=-~ =~-~1 3

-.- L .. -·

FOcw~-~e---EQ~WEI AFoCW 9L_ ~fl)~Y;iOl---'@) PS .. ~L E~O ---.-.--- I PSI _.~5 ._.!'.s. i ------ :t

FOCWo .. 94_tl~~Br----Qf'._9;1 __ GNo .----@.©.l

_. __ . ..l!_ --12 2 (2J-------.Q-1 -7i I .. .-.--- 0

@ ___ E:foSLI J7-IFDo

@J- GND ~-; PRTlNO

.- IPE I S6~PE Q6>---jsLcri. __ . ~1 SLCT

J

----iACRo -- _56_ ACK ----1 ERRO ~ . ERR

IBS.Y.L ___ 46 BSV --=·BSI..Hi!_-·-~f- RSIN

(@-RATI:P-I-_-"---'RAFo

(i) RESETO J6gRESET

CHENGIJ~-] -----.------- ~)

PjO~_- ~g:,~ __ QPO {g -_'-_dj~.l S 68 --.---A6f-_!!Q __ _ .. 66- J_O _ 3-64- 2Q __ _ 2-6J---io _ I --~- 00 __ @)

IRClllG- l89.11 PINT _f!O_EH!lJ i ----(5) SLlN-liL-_~LlNi -.<@ RSTB !2Q_$t.8Q.f~j_----

AUTF S9 AUTFol---=-==~_~

<Y.I--- [- -.-----l-.-. _ Vcc - 03,28,5J, 18 GNO-Ol!,IS,29, l!0,Sl!,65, 19,90

NC -IJ,Il!

l'u:nsEII 11,\ n: 11'HINTW "OAHII I TIT I.E '10 DEC DOER G A ,. pm. ~:.' IIIHAWIN(; N". 1"'\1;6 No rEV MI\HK

. -ATION

m",-" ., I ... .... . . jW'N" II ... , II _ _ _______ TOBHIBA co" ..... ~_ IIESII;NEII In 3 - 1 4 I l"IlI:.l"!\ F Ii II y 2

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RE\'iSEIl"Y

CIIECKFII IIY

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<. j?):-- __ _ SYID~: __ ____ __ __ 51 __ __ _ 4 i _________ __ ~ I

-~-:_ ~: __ :_~~: - -11 @ ____ -tii

Q!} ________ ~p~~~o (IJ)------- FPAI5.ri

Q~ ___ ---Jm~_~A.L ___ _ (13)----- - WlNOWI --lil)--- WcLki-----@ WF'i_~fiTi lI5) 1 ROI (ij)_____ yce ~5)--------lNbEXi

I 2 J 1

~ °IB~ 29 5 ~ ..t 2? 3 ~~ 2 2S_ I 24_ 0

10K mji2J~C;~

00 -~-L -m;Ro,!~([j)~ INT ---------- - FDCU-' -([D-

HL !~ SDS JJ.l ________ E:>.IllE I e 44 ---------WE --~------~W-C~f.L-- I

WOT -15--------- ___ J~<;;'~.D.l I LCDR __________ JOIRCL_ I

4:;? 41 .10 JQ

ROP MFM _!12_ WNO SYNC - 4J __ - -SYNC I tAl WCK RWCK--IG--- Fwski ---~I WP FRSP _ 14____ __ IFslEpi ~

09llRO I! ROY J5 lOx

USOQj-

USI -ga _ E?O _QP PSO -r--- PS! __ @ PSI __ 0____ -

1--FDc---r lC8586F

IC24

.. Ff)CCSO _ _ 2.1-~CS (U) --._- AAo81 __ _____ ____ ?~_ AO l~)-__ ------ ioRPj(l. - 2'09( RO <;1) iOWRIf.l __________ ( WR (;J) - -- --- - ~i:KFl11 J 7 CK q:p - ----- FRSTI ---------- -..!~- RSr (!J)-------- ---- -

11 Vee -- "j9~1_ _ yee _ IV) Vee -- -- '.!

GNO 3f} ________ 9NQ_ ---@ '-------- -- .-

Ij~:\"ISEIl 11,\ IE rHiNH~ij illlAllh

3 I 4 5

______ -f_WSKQ ____ @

.. -_. L w -~:.~~m FS!~PL.~ ___ _ _ _ - _01]CI'.c18

NC -01,12,23

GND-38

Vee -17 ,39

rUTU:' FOe

IIESII;NEII 11\- I'fRAWiNi; IIATE r ii 12 TffiI\WiNI; Nfl 11'Ar~N°T~EVMARK

2--' I 3 T T""~""A r"nAPORATION

A

c

D

E

F

G

H

J

K

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A

B

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F

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u

J

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'U:\1sEIflW

em:i:I\":II 11\-

n

1

!IS) nEAO'y' I

(l;) GND (~) ~ND (y) ____ Vee

~V) Vee

01 IC OG B os A

FI 01 [l 02

PIGA

, , fiSC 116MIIl

OJ I XS Vee -08 SI GNO-04

I 2 I

.-- . ___ .EI,(_HP

l~1

HI('G ~6

DI~OIJGPOI -SE0<3i;2Oc:--

01 IXG lC25 VOOI 24 02 XD

VS~I .12 X{II - Q~X02 21

WIN 08

3 I

PI68_.. 3911H 1c30 ¥--c--I----[C-D

101 F : II J311F(25V) _ .. _- --_ ... -

_._----_ .•. _-- _. -

4

Vee

GND

___ S.cKFOI

WINDWI

@

© 00

--@

F' 1 PIJCC

(.>~'2 . FD .. CR_UI_. r~llrt\~~ij~~e .. -. -~~----~. LOCK

Q(L _~ Fi5Rojr~-=---~: I ~\Ci~ 06 .---.---.- --- B.D~TAI - ----@

~ _ sr NCr _ - .~-.. M J . .. - os us.--.-HODM ___ ~ L:~~-" · -..... -, PIJ/, . ~ - ORO. _ . __ . . . __ ... 01 SYNC

SG . RD

-lB if,8' . 10 LB\-...... .u-·-- MFM . ..J!. MIN

@\._.Q!>I_D___ . ~2 . TRG '.I --.-- -2Q __ CR

_14·ICaNT

. __ wc.u~ L ____ @

ISK PlfD C21 PI6C ·---·---t- --mr~?l-:j~K--JJJo~F-----

----[Ri4.eJ -- -------

100 LPFII _16_._ .. _PI6L. -.--- .. --- ----fRL4.§J·-··--PiG-J --.--

I F C29 C28 PI6G Wl<-oFSTI

IS- .PE? -H- - --·-·-1------- ---1/-·- .----, '[jRIS2J---

0.04711F O.OlilF __ i

IJ GND ---{BJ1i]_ VSS21 .-- - - ......... --.--.--@ 1.2K

- . ---_ .. __ .. _---_.- .P.1_~Ii __ ._ ._._ ... _______ '. _____ ..J

- - ffiJ - 15518.-1 56Jl.!< '. PIq,L . .::...:.:3 1<1r-.-j---LiUs~~.:~ C 12 -C.R!

'~n'SEII IIATE jI'HIN·' I", lIoAI11I Inlu: . VF6

5

II.·:SU;NEU II\' rRA\\ 'NI; IIAlE r ll 13' l,jRAWIN(; Nil I"A'(aN"-INEVr.I:\ RK

. I " I,. ~ ."

I

I

? I :i 4 TO_HI_. COR,"ORATIDN

-

A

B

C

D

E

F

G-

Il

J

K

L

A

B

c

J)

E

F

-G

II

J

K

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o I

N1'iMAL : I -- 2 OI·J

EXT. FDD l.-liiDE: oFF

EXT. FDD DRIVE A : 2 - J olJ

lV) Vee

(ii>-- M.el~RI (ij). __ [lC;H R i . 101<

LR.6 I 1 - - - I I ('l 3 I

__ GNU 12 I ~)-- .. --H'l----- . I

<y) Vee

1 1 I S I () i I L ____ . _ I

a 1)-.. qJ) -(l2) -

InK IRS I MoNAI bSfL'" FSIDFI

@ ____ E.QJ.R_~_I Q2J.- .- FS1FPI

(!J> FDCWDI

-I

I 2 1 I

l~ @

®

3

GND

Vee

MeNSO __ . _____ bS~U~Q ____ _

1 4

PJ7 L:_ --- -]IJ,15,17, 19,21,23, 2S

I -.- -----,01,03,05,07,09

-r~~~:~~~J SflJ~O _____ (§)

--jMQ!~U~.L. ___ @ ______ _ ( DRIVE B)

EFD$LJ ---l--~ ..... -= __

SlOEQ - -- ~6_ bJRCO_._ ------- -- - '-12

-- SlEPO_ - '=i4 ----- YVG.~TP __ .. ---~-- .--- ._.18

WRDAO ___ lQ.. EFOSLt __ @QJX@

EFOAO </J) SEL~O . @ p!<!~ .. _

jf1~a~=~----lJ j A) (DRIVE

@_GIIID_ -'--T-'-'

GND [---'-1 @ --- .. - -.-.--------- 13 IS 17 19 21 23,25 ---- '" , , Vee r------, @-----.... --- --- L-.. ____ --'OI,OJ,05 ,01, 09

~ DIRCO ~--'----ru--17 0 03 ---- .. ------------ -- -----.---------... 12 15- 0 2 05 -- _. ____ . __ .ST.EPtL .. __________ -- i4 --- WGATO--"---

13 0 .QL .. - -.- -- --. -- .. -. --- .. -- --------- 18 --i-I-- 0 09 _____ . __ WfIDAO - - ----i6·

(D- - H~~f U1·-.9~-I~\COBI...M...----l- FDWEI @ ___ FOCWEI ._!..CL 1 . . ---.-..... ----- .--... ------- .. -- ---------@

REVISE!) oY R~~\'IS~:IJ HAll, -rRINn:llfIOARfI rnu: FDD DRiVER 1

5

UnXKl-:tl hV m:SI(;NW II\, IRA WfJllI; Ii" ii' rrr t4' _IIJRAWIN(; No. ]"AY9 Nil tin:\' r.tAHK

I ,-A

E

F

G

II

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K

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A

B

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l"IIECKEIi 11\.

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liJ>. L>SFt 81

II.!> .. FDCWLJI

@._ .. _EUWE I

IjZ) _ .. ES.J.UFI

tl4> .. _~FlJli.

__ . UG ~ DSKCO 02. t~U()

A I~-· ~~ ···~-~~H~ .. 2/i -- R~)AO .. _ .. (J8 __ BLJYli· PJ1

t.. 06 __ .~I_~.KCO

B :~:::~: !ito .. _ .. _ 24 ._._BPAO _Q~ _. __ RDYO

@~_._._fWSK I

@) ____ lPDOI_ 14 --.

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2

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Ol~_r ___ ·.Qi~~~·-

3 4

BUSYI @)

ACKO _____ @

. PEI __ . _______ @)

SElEC 1._____ _ _ @)

ERR!>RQ_ .. _.. @

_QS'!<~9---{]) I(~ 1< U INDEXI '.>

ti~ 91

- r~ 94. . Rio,~· -.. .. RIO!) -

- .. Riol .----- R 98

f- ... - ...

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14 __

j.. .i 11 .. : i2 - Q_~-=-:! q

EXT ._. ________ ~!.._ ... _. . iii 0 • y LL _._ ._~'_._._·-·-08·-D 3 V 09 .. . __ . ___ ~I-·· 04 D 2 V -2L- 1-1--1-@} EXRpVO

n •• ------ D 1 ~ - - -- ... -... -----

_._ .... _ 02 V

-E!~.e~J~!~- 13 _ WPROTI ®

!L-~ __ RDOA!_@

oq~ ~ ;C:±t= _ _ . __ ._. ___ I3E}\Q,(1 @ i

.. D 0 V~

JDRVR CN387

04 A ) C 01 .. .Q~J CLfC1~·~ r 1\-··'5 :~ ICI1

KR\'ISEIl Ii,HI·:

"F:SI(;N~:II II\,

n

DRVR CN240

~ ... GNO 01 I -- .. (,G,.------;---.. ~

IMAWII'lI; li,\H:

?

DRIVER n

4

5

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(FlH/Hlll>

PJI4 C-:ill

CJijJ

r=-~j~ I··

L~~jJ

BUS., I It,iblii3i

I

101< IRi~G I

.!VK -. 1l~1;?5 J

AC.I<!,l -....... iiil~ iiJSEL81 .. _. illi271

PE I '-"l" J~iJ.~ 1 nxwul _._ tJU28 I ~;F.LECI. . ..... ii}i~ I HJWE I ---[H.i~o I ..

--.-.. - J F.nr~q(~)., .-. r 15 .-.- iFSWE

eR8 Iti P'-9_~

@.Y.~c..12['lJ 155184

101< --U~'2.~_I·

10K -. W.UjJ

lOt< -. U3j~.AJ·

101< ·:nH~.JI

IOI~

UUitl 10K

- LBi.L'i1 2.2K

.- ill.UBI

1 -

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PD11

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51

41

JI

I

21< (I~) II. _, I R 'JiJ

2 I

IBSYI (ill

2K (!5>_.lACKO <fI) Ih~l·· . L<ft __ GND@

2.2~ @) 100PF_J'p~-' <LD -tH ~-' I· ... -.. ---.-. 2K @l ISLCTI ([]) ... ut§_~u -. --.... . 2K @ . lmrm Qj) .. LkaIl-- ----.-..

2.2K . UL&B.I------ -- r~SLlNI (jj)

2.2K ·(RiiQJ---·-·-··· .- RATFDI «J)

.. , L~~~~h--·--·----·-· IPID1bCi@ 2.2K 31 .

L~.j~~J----··· --- --.----- if~t>AI!~

C26 L O.lIlF~r

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trw -- rRilIJ

J 2.2K 2L -- -... -1 . LR !3~J 21 If (wpm§)

REvlsW BY

CIlEi.:KEIi 11,'

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IUI< L~.i.i.5.1-·-

IU:\"ls"lJ IIAT"

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2.2K liLB]]

tLili !"HINTI-:IJ IliiAIW

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_. __ ._ ~ 0 I iiNLi~

I"kAWIN(; IjAH:

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3 I 4

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'I)_lWP}O_ -. 0'1 LSOO. 51,02 II.. I __ J~.~! .-

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toshiba t1100 plus - maintenance manual · toshiba tiioo plus is a portable personal computer which...

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