tpttdo (daisy chain b/w fpgas) tpttdo probe for jtag tpttms tptdi tptclk
TRANSCRIPT
![Page 1: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/1.jpg)
TPTTDO (Daisy Chain b/w FPGAs)
TPTTDO
Probe for JTAG
TPTTMS
TPTDI
TPTCLK
![Page 2: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/2.jpg)
Probe for SPI / I2C
TPMOSI
TPSCLK
TPMISO
TPSEL1
TPSEL0
TPSDA
TPSCL
NOTE :U35 is I2C Bus Isolator
![Page 3: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/3.jpg)
Probe for IPM Bus
TPSDABTPSCLB
TPSDAA
TPSCLA
NOTE :U5 (bottom) is I2C Bus Isolator for IPMB AU6 (top) is I2C Bus Isolator for IMPB B
![Page 4: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/4.jpg)
Probe for GND
TPG3
TPG5
TPG6
TPG2
TPG1
TPG4
![Page 5: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/5.jpg)
Probe driven by FPGA
TP1_2
TP2_2
TP3_2
TP1_1
TP2_1
TP3_1
NOTE :TP1 , 2, and 3 are connected to AD3, AD4, and AD2, respectively.
![Page 6: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/6.jpg)
Power distribution (1)
PIM In : 48VOut : 3.3V & -48V
Power ConverterIn : -48VOut: VCC12
U16In : VCC12Out : VCC3V3(20A)
U17 In : VCC12Out : VCC1V0(20A)
![Page 7: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/7.jpg)
Power distribution (2)
U22In : VCC1V8Out : VDDR1 (1.5V)(3A, linear)
U32In : VCC1V8Out : VDDR2 (1.5V)(3A, linear)
U29In : VCC3V3Out : VCC2V5(3A, linear)
U18 In : VCC12Out : VCC1V8(10A)
U23 In : VCC12Out : MGTAVTT(10A)
U21 In : VCC12Out : MGTAVCC(10A)
![Page 8: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/8.jpg)
U17U16
117
118
121
120
VCC12
VCC12
VCC12@U16, U17
![Page 9: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/9.jpg)
VCC3V3@U29
U29
157
VCC3V3
![Page 10: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/10.jpg)
MGTAVCC (1.0V)@U21
U21
86
89
65
76
MGTAVCC
![Page 11: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/11.jpg)
MGTAVTT (1.2V)@U23
132
90
122
105
MGTAVTT
U23
![Page 12: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/12.jpg)
203.3V (management)
193.3V (management)
Management 3.3V @ PIM
![Page 13: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/13.jpg)
66_1
68_1
67_1
67_2
66_2
68_2
VCC1V8
VCC1V8
VCC1V8@FPGA
![Page 14: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/14.jpg)
VDDR1@U22VDDR2@U32
Pin5 or Pin4. Pin5 looks easier to avoid short with PIn3 of GND
U22
U32
![Page 15: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/15.jpg)
55_2
75_2
155_2
115
53_2
60_2
53_1
55_1
54_1
75_1
54_2
59
_1
VCC3V3
VCC1V0
VCC3V3
56_1
56_2
15
6_1
155_1
15
6_2
60_2
59_2
VCC2V5
VCC1V0
VCC3V3
VCC3V3
Polarized Capacitors(330uF, Yellow big ones)
VCC1V8
![Page 16: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/16.jpg)
Polarized Capacitorsaround PIM C40 (470uF), C35, C36 (120uF)They have to have bar on downside as shown below
![Page 17: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/17.jpg)
Chip Orientation withTiny dot silkscreened on board (examples)
![Page 18: TPTTDO (Daisy Chain b/w FPGAs) TPTTDO Probe for JTAG TPTTMS TPTDI TPTCLK](https://reader036.vdocument.in/reader036/viewer/2022070402/56649f265503460f94c3dcec/html5/thumbnails/18.jpg)
CLOCK setting
U27=GTXREFCLK
U11=SYSCLK
Typical Setting
125 MHz{1, 0, 1, 1, 0, “X”}
0
10
1
150 MHz{0, 0, 1, 1, 0, “X”}
200 MHz{0, 0, 0, 1, 0, “X”}
156.25 MHz{1, 0, 1, 1, 0, “X”}