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What is the Micron Automata Processor? 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor3 Realization of a Non-deterministic Finite Automata (NFA) in hardware Interesting adaptation of conventional SDRAM architecture 8-bit input generates the “row address” Routing matrix Provides the “column address”

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Track Pattern Recognition with the Micron Automata Processor Michael Wang Scientific Computing Division, Fermilab CMS Software/Computing R&D Meeting, December 7, 2015 Introduction Fermilab LDRD project to investigate the feasibility of using the Micron Automata Processor (AP) in HEP pattern recognition applications. Others working with me on this: Fermilab: Chris Green University of Virginias Center for Automata Processing: Ke Wang Current goal is to demonstrate a proof-of-principle. Do this on an ideal toy detector Outline Background on Micron AP Description of toy detector Implementation of a track finder on the AP Brief description on testing procedure Preliminary results from tests Some to do items 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor2 What is the Micron Automata Processor? 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor3 Realization of a Non-deterministic Finite Automata (NFA) in hardware Interesting adaptation of conventional SDRAM architecture 8-bit input generates the row address Routing matrix Provides the column address From regular expressions to particle trajectories 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor4 su r t a ra s y h i g s v t r su s y symbol A - symbol B - symbol C - symbol D - hit address 1 hit address 2 hit address 3 hit address 4 An obvious application of the Automata Processor is in performing high-speed searches on input data streams for regular expression matching or finding words in a dictionary. In this example, the input string susy is matched to a dictionary entry in exactly 4 symbol cycles no matter how big the dictionary. However, the symbols need not be limited to characters in a string. For example, they could be replaced by wire, strip, or pixel addresses in a HEP tracking detector. 15,17,23,25,31,32,35,36,41,45 Basic operating principle of an automata track finder 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor5 R {15}{25}{35}{45} L1L2L3L4 The idea is to create a pattern bank containing every possible track pattern. Each pattern is represented by an Automata network like the one showed above (with latch attributes enabled). Detector hits are fed into the AP sequentially by layer and all hit combinations with matching patterns in the bank are found. Addresses of detector hits read out by layer: Layer 1Layer 2Layer 3Layer 4 Micron AP readout architecture 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor6 Test case 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor7 R-z R- Proof of principle application: hypothetical pixel detector based electron track trigger. Demonstrate that automata processor can, in principle, be used to find tracks. Toy detector approximating CMS phase-1 pixel (barrel) 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor8 Like real detector: Same number of faces/layer 8 modules/face with 2 x 8 ROCs/module 80 rows x 52 columns/ROC Long dimension of pixel and ROC column along detector z-axis Same total number of pixels/layer Unlike real detector: 165 um x 98 um pixels (instead of 150 um x 100 um) Pixels form uniform grid laid out over cylindrical surface of each layer Each face is a cylindrical tube segment Instead of a flat rectangular area LayerFacesNpix in phiNpix in ZNpix *Radii close to but different from real detector in order to maintain same total Number of pixels per layer using a fixed pixel size of 165 um x 98 um. Simulated events for toy detector 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor9 Single Zee eventZee event with 50 pileups Pythia Z to ee signal, pileups using Pythia minimum bias 4 samples with same signal events but overlaid with 50, 80, 110 & 140 PUs Particles tracked through 4T solenoidal field No stochastic processes like MSCT and energy loss Charged tracks produce single pixel hit upon layer traversal at 100% efficiency Unstable particles decayed randomly into appropriate channel based on B.R. and with exponential decay length distributions based on c-tau Photons converted into ZOA pairs at pixel detector layers Implementing the track finder on the automata processor Creating a dictionary or pattern bank Define the symbols for the dictionary Divide detector into sectors for convenience Generate the patterns Program the dictionary into the automata processor Define the automaton: basic unit of interconnected STEs representing a single pattern Load symbols representing each track into the automaton creating as many instances as there are patterns in a bank 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor10 Defining the alphabet of our dictionary: hit addreses 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor11 R-Phi view: projection on a plane Perpendicular to cylindrical axis (coordinates: radius R & azimuthal angle Phi) R-Z view: a little like looking from side of cylinder (coordinates: radius R & Z 3D track patterns possible in principle but impractical due to number of patterns Instead, decompose into R-phi and R-Z views Defining Sectors and Roads for Pattern Banks 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor12 Divided R-Phi view into 72 overlapping sectors. R-Z view: divide Layer 1 into 32 sections in z and Layers 2, 3, and 4 intno 16 sections in z Find all possible combinations of 4 sections forming roads pointing back to luminous region. Generating pattern banks 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor13 Shown below are all possible positively charged tracks for a particular R-Phi sector and R-Z road generated with a single electron gun: Basic automaton for track finder requiring all 4 hits 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor14 Energy range constraint on calorimeter cluster EM cluster coordinate (phi or eta depending on view) STE pairs representing 16-bit hit addresses in the 4 layers Latches to enable appropriate half of 16-bit STE pair on odd or even cycle Reporting STE Size of Pattern Banks R-phi view: 72 banks with 5830 patterns each R-z view: 244 banks with ~4662 patterns each In principle, for an ideal detector like our toy detector, number of patterns can be reduced by using rotational symmetry in the R-phi view and mirrro symmetry in the R-z view Also using relatively fine-grained patterns in this proof-of- principle. Patterns can be reduced by using coarser patterns. 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor15 Testing the automata track finder 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor16 Point EM clusters above threshold back to primary interaction vertex (assumed known) and readout hits in narrow window (region-of-interest) around possible track direction Select only the two pattern banks corresponding to the region-of-interest Feed hits into the automata chips (emulator) containing the banks for each view Find at least one pair of matches from both views occurring on same symbol cycle Result of test for the 50 pileup sample Out of 1257 em clusters whose associated hits were within detector acceptance, only 8 were photons misidentified as electrons Benchmarks on automata processor 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor17 Results based on Micron SDK emulator. Includes estimates of latencies associated with internal data transfers from event memory to output event buffer based on latest numbers provided by Micron (under nda) Does not yet include latencies associated with: Transferring match results from output event buffer to external hardware Additional processing in external logic (FPGA) to require coincidence in reports from both views. Benchmarks on x86 cpu (single core) 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor18 Track match algorithm requiring all 4 hits on x86 CPU (2 nd gen Intel core i7) Left plot: uses all hits in ROI; Right plot: breaks out of hit loop as soon as first match is found Does not take into account latencies associated with data transfer to/from memory Estimated processing times 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor19 x86 cpu results for the 140PU sample (assume 3GHz clock): All hits: 398,925 cycles x 0.333ns = 133 microseconds Quit on 1 st match: 251,445 cycles x 0.333ns = 84 microseconds AP results for the 140PU sample (assume 133Mhz clock): R-phi view: 311 cycles x 7.5ns = 2.3 microseconds R-Z view: 435 cycles x 7.5ns = 3.3 microseconds Note: Matching in both views are done simultaneously To do items Implement x86 track match algorithm on many-core for comparison: Grad student at Univeristy of Virginias Center for Automata Processing working on this Estimate additional cycles required by external hardware to read output report events for two views and check for coincidence: Working with Fermilab engineers on this Compile automata with optimizations to get better estimate of number of patterns that fit on a chip: Chris Green will look into this now that newer SDK has addressed bugs of earlier versions Run on actual hardware: UVa-CAP in process of scheduling delivery of hardware with Micron for January /7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor20 12/7/15Michael Wang | Track Pattern Recognition with the Micron Automata Processor21 End