library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity lights is Port ( clk : in STD_LOGIC; r : out STD_LOGIC_VECTOR (3 downto 0); g : out STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_VECTOR (3 downto 0));end lights;

architecture Behavioral of lights isshared variable count1: integer := 0;signal testclk: std_logic := '0';shared variable count:std_logic_vector(4 downto 0):="00000";begin

clock: process(clk)beginif(rising_edge(clk)) thencount1 := count1 + 1; if(count1 = 500000) thentestclk r