transcending digital processing - nmi · single sided fan-out or fan-in ... design rules and...
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© BPA Consulting Ltd.
3D Embedded Packaging -Transcending Digital Processing
Packaging in a Post Moore's World
Nick Pearne / Bill BurrBPA Consulting, Ltd.
Dorset House, Kingston RoadSurrey
© BPA Consulting Ltd.
3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Computing Systems Evolution
2
© BPA Consulting Ltd.
3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Generations of Integrated Circuits
● 1st- Small Scale Integration (SSI)– 3 to 30 transistors/chip. Early 1960s
● 2nd- Medium Scale Integration (MSI)– 30 to 300 transistors/chip. Late 1960s
● 3rd- Large Scale Integration (LSI)– 300 to 3,000 transistors/chip. Mid 1970s
● 4th- Very Large Scale Integration (VLSI)– more than 3,000 transistors/chip. Early 1980s
● 5th- Ultra Large Scale Integration (ULSI)– more than one million transistors/chip. Mid 1980s
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Quad NAND Device64 transistors
"VLSI" Device750,000 transistors
"ULSI" GPU with integrated memory450 million transistors
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
The World is Flat
● The Silicon Fabrication Process has been essentially planar- buildup of conductive and insulating layers onto and into the silicon wafer
● This planarity has determined the form factor for subsequent levels of packaging & interconnection
4
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Size + Complexity
5
300 mm
2010: 32nm Quad-Core Processor(758 million transistors)
200 mm
100 mm
1971: 10µm 4 bit Processor(2300 transistors)
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
The Digital World- What Could Be Achieved
● Calculator- Accounts at home● PC- Desktop publishing, computer graphics, e-mail, World
Wide Web, Video Games● Laptop/Notebook- Computing and communications "on the
go"● CD Player- the cutting edge of Digital Sound
6
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
The Great Bit Race
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source: Karl Rupp
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Then Came the Mobile 'Phone
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Systems Integration in the Cell PhoneSystems Integration in the Cell Phone
Source : H.Ueda JEITASource : H.Ueda JEITA source: JEITA
Systems Integration in the Cellular Phone
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
A Business- Open to Human Interaction
9
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Processor in Your Pocket
10
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Diversification- the New Dimension
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● "Processing"
● "Experience"
source: ITRS
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Where The Rubber Hits the Road
● "Processing"– active devices– more transistors per unit
area = higher cost– 3D packaging = higher
interconnect complexity
● "Experience"– actives, passives, MEMS,
power, RF– non-digital functions =
mixed component types– mixed signals / RF =
layout, floorplan, parastics issues
12
source: Chipworks
source: Georgia Tech PRC
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Putting it All Together
13
source: OKI Semiconductor
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
What is "Embedding"..?
● Embedding uses the space within an organic substrate for active and passive components
● Typically <400 embedded connections● Embedding requires a new business model,
integrating component, substrate, and assembly operations: the "Organic Fab"
● Components are embedded inside an organic substrate (PCB core) by combination of:– Component placement/bonding– Component encapsulation/embedding– Substrate buildup (lamination)– Circuitization– Final Finishing/Singulation/Test
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What is Embedded Component?
Embedding uses the space within an organicsubstrate for active and passive components
AT&S is amongst the leading chip embeddingproviders – others in Europe; Japan; Korea; Taiwan
3D Component Packaging in Organic Substrate | Mark Beesley, AT&S | GSF 2012, Shanghai
Typically < 400 embedded connections
Component Assembly Lamination Structuring
HDI/Sequential MLB
source: AT&S, BPA Archives
© BPA Consulting Ltd.
3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
The Integration Advantage- "Organic Fab"
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300mm Wafer
● Almost 4X the carrier area for structuring / interconnection / finishing processes
source: AT&S, BPA Archives
© BPA Consulting Ltd.
3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Embedding Options
● Single Sided Fan-out or Fan-In● Adjust semiconductor footprint through
design rules and redistribution layers
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"Wafer Level" Packages
Aluminum or CuRedistribution Line
Active Silicon
Solder Terminal
Passivation Layers
"Board Embedded" Packages
Component�Level�Reliability
Criteria :Appearance�:�no�void,�no�delamination:Circuit�resistance�change�:�less�than�20%�from�T=0
Test�Vehicle�� PKG�Size:�5.15�x�5.15�mmStructure:�4PI,�0.5mm�pitich with�98�I/O
Board�Level�Reliability
Pass-40deg.C�<->125deg.C
(Ramp�rate�controlled)
1000�cyclesThermal�Cycle
Pass1500G�!30!Board�Drop
ResultConditionsItem
Test ResultsEvaluation�board�layout Bump�allocation
Evaluated�connections�of�peripheral�bumps�(weakest�parts)�
Connection reliability evaluation on a rigid mother board
source: STATSChipPac
● "Via" Type● "Pad" Type
source: TransSiP
Fan-In Wafer Level RDL for Ease of Die Embedding
1) Eases large panel dieplacement requirements.
2) Relaxes laser via tolerancerequirements.
3) Lowest cost option for finest interconnects (highest density).
4) Provides corrosion barrier for embedded integrated circuits.
5) Higher overall yields!!
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Ways to Skin the Cat- 1
● "Via Connection"
17
2
3. Definitions
3.1 Technology of device embedded substrate
There are two types of device embedded substrates, one type is to mound active and/or passive device on a base
substrate and covered by organic resin and the other is to form device on a substrate and then covered by organic resin.
The device embedded substrate also includes composite type substrates which consist of mass produced inorganic
ceramic including LTCC (low temperature co-fired ceramics) substrates (hereafter they are called just ceramics) on which
passive devices are embedded as shown in Figure 4, and the other type as shown in Figure 5 where the ceramic substrate
is used as a base on which active and passive devices are mounted and the entire body is covered by organic resin,
however, details of inorganic ceramics are not specified in this document. Such a ceramic is treated just handled as a
base of a device embedded module.
Classification of device embedding is given in Table 1. Active devices include bare die, wafer-level package (WLP), BGA,
LGA, and QFN. Passive devices include chip component, complex chip component like an array and integrated passive
device (IPD). Module and MEMS are embedded onto the substrate after packaging and molding into module and MEMS.
The component formed during substrate formation is not covered in this document but also included in Table 1. There are
two types of formed passive component embedding, one is to form passive components using thick film or thick film
technology on the base of silicon or compound semiconductor and/or on the stacked chip at the wafer level or on
package-on-package (PoP), and the there is to use sheet-type passive device on an organic substrate first and then other
devices are embedded.
Figure. 2 Completed device embedded substrate (pad connection)
Figure 3 Completed device embedded substrate (via connection)
Embedded devicePattern formation
Pattern formationLayer connection (via)
Layer connection
(via)
Com
ple
ted d
evic
e e
mbedded b
oard
Solder resist
Solder resist
Embedded devicePattern formation
Pattern formationLayer connection (via)
Layer connection
(via)
Com
ple
ted d
evic
e e
mbedded b
oard
Solder resist
Solder resist
Cu plated viaCu plated connectionEmbedded with terminals upward
Base
Active device
Solder resist
Cu plated viaCu plated connectionEmbedded with terminals upward
Base
Active device
Solder resist
Pro + compatible with industry standard LVH
(laser via hole) buildup processes + On-chip design rules (40µ pads/100µ
pitch)
Con - copper plating required on devices-
additional cost - registration is an issue - no wiring on encapsulating layer
EIPC Summer Conference Milan, Italy, September 13th & 14th, 2012
Lars Böttcher, System Integration & Interconnection Technologies [email protected]
© Fraunhofer IZM
Development of embedding technology
printed resistor
printed capacitor
discrete resistor
discrete capacitor
embedded chip
1970 1995 2000 2005 2012
first patent
Concepts Î Research Î Collaboration Projects Î Industrialization
HIDING DIES
History of Embedding
source: FlipChip
source: Fraunhofer IZM
© BPA Consulting Ltd.
3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Ways to Skin the Cat- 2● "Pad Connection"
18
2
3. Definitions
3.1 Technology of device embedded substrate
There are two types of device embedded substrates, one type is to mound active and/or passive device on a base
substrate and covered by organic resin and the other is to form device on a substrate and then covered by organic resin.
The device embedded substrate also includes composite type substrates which consist of mass produced inorganic
ceramic including LTCC (low temperature co-fired ceramics) substrates (hereafter they are called just ceramics) on which
passive devices are embedded as shown in Figure 4, and the other type as shown in Figure 5 where the ceramic substrate
is used as a base on which active and passive devices are mounted and the entire body is covered by organic resin,
however, details of inorganic ceramics are not specified in this document. Such a ceramic is treated just handled as a
base of a device embedded module.
Classification of device embedding is given in Table 1. Active devices include bare die, wafer-level package (WLP), BGA,
LGA, and QFN. Passive devices include chip component, complex chip component like an array and integrated passive
device (IPD). Module and MEMS are embedded onto the substrate after packaging and molding into module and MEMS.
The component formed during substrate formation is not covered in this document but also included in Table 1. There are
two types of formed passive component embedding, one is to form passive components using thick film or thick film
technology on the base of silicon or compound semiconductor and/or on the stacked chip at the wafer level or on
package-on-package (PoP), and the there is to use sheet-type passive device on an organic substrate first and then other
devices are embedded.
Figure. 2 Completed device embedded substrate (pad connection)
Figure 3 Completed device embedded substrate (via connection)
Embedded devicePattern formation
Pattern formationLayer connection (via)
Layer connection
(via)
Co
mple
ted
devic
e e
mb
edde
d b
oa
rd
Solder resist
Solder resist
Embedded devicePattern formation
Pattern formationLayer connection (via)
Layer connection
(via)
Co
mple
ted
devic
e e
mb
edde
d b
oa
rd
Solder resist
Solder resist
Cu plated viaCu plated connectionEmbedded with terminals upward
Base
Active device
Solder resist
Cu plated viaCu plated connectionEmbedded with terminals upward
Base
Active device
Solder resist
Pro + standard components and assembly
processes used (solder / conductive adhesive)- no added cost
+ pad-to-device registration issues confined to well-known assembly issues and tolerances
+ hybrid processes (conductive post / LVH) can be used for maximum flexibility
+ wiring channels available in encapsulating layer(s)
Con + most solutions are proprietary or derivatives
of proprietary technologies (ALIVH, B2iT) + Density for conductive post solution limited to
0.2mm pitch
Embedded WLCSP- Camera module
© 2011 Dai Nippon Printing Co.,Ltd. All Rights Reserved.14
CONFIDENTIAL
Embedded passives into main board (about 250pcs)
Embedded BEmbedded B22itit Application (Mother board) Application (Mother board)
t0.33mm
Max
Structure䠖12LayerThickness䠖t=0.96mm
SSD Motherboard- 250 embedded passives
source: DNP
© BPA Consulting Ltd.
3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
The Integration Imperative● Footprint Reduction (Miniaturisation)● Integration (Ease of Use)● Reliability● Performance● Time to Market
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Option 1:Integrated Packaging + Anylayer MLB => significant form factor reduction
Option 2:Integrated Packaging + Standard HDI MLB => reduced ramp risk, reduced cost, some form factor reductionStandard PWB
Complex SoC on interposer
Discrete component packages- supply chain flexibility but complex BOM and PWB interconnectShort product lifecycle can't
tolerate SoC development leadtime
source: AT&S, BPA Archives
© BPA Consulting Ltd.
3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
Mounting and Interconnection Options
20
7
Table 3 Jisso mounting and interconnection of device embedded substrate
Interconnection Jisso mounting Device
Process Interconnection Structure
Wire bonding Wire melt-connection Die bonding Chip
Flip-chip bonding Metal bonding
Contact connection
Metal bonding
Contact
Wafer level
packaging (WLP)
Reflow
Polymer bonding
Soldering
Conductive paste
Package Reflow
Polymer bonding
Soldering
Conductive paste
Soldering
Conductive paste
Rectangular chip Reflow
Polymer bonding
Soldering
Conductive paste
Rod-type chip Reflow
Polymer bonding
Soldering
Conductive paste
Soldering
Conductive paste
Module Reflow
Polymer bonding
Soldering
Conductive paste
Pad bonding
Mounting
MEMS Reflow
Polymer bonding
Soldering
Conductive paste
Soldering
Conductive paste
Chip Via connection Copper plating
Conductive paste
Die bonding
Wafer level
package (WLP)
Via connection Copper plating
Conductive paste
Package Via connection Copper plating
Conductive paste
Copper plating
Conductive paste
Rectangular chip Via connection Copper plating
Conductive paste
Rod-type chip Via connection Copper plating
Conductive paste
Module Via connection Copper plating
Conductive paste
Via bonding
Mounting
MEMS Via connection Copper plating
Conductive paste
Copper plating
Conductive paste
Note: Shape and surface treatment of terminals of embedding device should be agreed between user and supplier of the
device.
7
Table 3 Jisso mounting and interconnection of device embedded substrate
Interconnection Jisso mounting Device
Process Interconnection Structure
Wire bonding Wire melt-connection Die bonding Chip
Flip-chip bonding Metal bonding
Contact connection
Metal bonding
Contact
Wafer level
packaging (WLP)
Reflow
Polymer bonding
Soldering
Conductive paste
Package Reflow
Polymer bonding
Soldering
Conductive paste
Soldering
Conductive paste
Rectangular chip Reflow
Polymer bonding
Soldering
Conductive paste
Rod-type chip Reflow
Polymer bonding
Soldering
Conductive paste
Soldering
Conductive paste
Module Reflow
Polymer bonding
Soldering
Conductive paste
Pad bonding
Mounting
MEMS Reflow
Polymer bonding
Soldering
Conductive paste
Soldering
Conductive paste
Chip Via connection Copper plating
Conductive paste
Die bonding
Wafer level
package (WLP)
Via connection Copper plating
Conductive paste
Package Via connection Copper plating
Conductive paste
Copper plating
Conductive paste
Rectangular chip Via connection Copper plating
Conductive paste
Rod-type chip Via connection Copper plating
Conductive paste
Module Via connection Copper plating
Conductive paste
Via bonding
Mounting
MEMS Via connection Copper plating
Conductive paste
Copper plating
Conductive paste
Note: Shape and surface treatment of terminals of embedding device should be agreed between user and supplier of the
device.
Mounting MethodMounting Method
source: JPCA
● Pad Bonding– multiple connection options– supports components of different thicknesses
● Via Bonding– compatible with industry standard processes– potentially higher I/O densities
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
3D Embedded SiP
● Supports multiple device types: actives, discrete passives
● Off-the-shelf components can be used (WLP, CSP) ensuring industry-standard depth / breadth of supply
● ALP (Anylayer post) connections enable maximum layout flexibility and wiring density
● Overall cost advantage compared to Via processes
21
0
100
200
300
400
Conventional ALP SiP LVH SiP
PWBProcessComponent
source: TransSiP
Comparative Production Cost and Assembly: 250 embedded passive components
Rel
ativ
e C
ost,
%
source: Fujikura
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"
● Many ways to approach the challenge
● Key Drivers-– integration– codesign– reliability– cost– time to market
22
Achieving "More than Moore"- the 3rd Dimension
source: SPIL
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3D Embedding: Beyond Digital
"Packaging in a Post Moore's World"23
Thank you for your attention!