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Table of Contents

1 Software tools - General .................................................................................................. 4 1.1 BSP ................................................................................................................................................................ 4 1.2 FPGA BSDK .................................................................................................................................................... 4 1.3 Host BSDK ..................................................................................................................................................... 4 1.4 GNU Radio..................................................................................................................................................... 4 1.5 FPGA MBDK ................................................................................................................................................... 4 1.6 Host MBDK .................................................................................................................................................... 5 1.7 Documentation ............................................................................................................................................. 5

2 Perseus601x .................................................................................................................... 5 2.1 General ......................................................................................................................................................... 5 2.2 BSP ................................................................................................................................................................ 5 2.3 Host BSDK ..................................................................................................................................................... 5 2.4 FPGA BSDK .................................................................................................................................................... 5 2.5 FPGA MBDK ................................................................................................................................................... 5 2.6 Documentation ............................................................................................................................................. 5

3 Perseus611x .................................................................................................................... 6 3.1 General ......................................................................................................................................................... 6 3.2 Host BSDK ..................................................................................................................................................... 6 3.3 FPGA BSDK .................................................................................................................................................... 6 3.4 FPGA MBDK ................................................................................................................................................... 6 3.5 Documentation ............................................................................................................................................. 6

4 RTDEx.............................................................................................................................. 7 4.1 FPGA BSDK .................................................................................................................................................... 7 4.2 Host BSDK ..................................................................................................................................................... 7 4.3 FPGA MBDK ................................................................................................................................................... 7 4.4 Host MBDK .................................................................................................................................................... 7 4.5 Documentation ............................................................................................................................................. 7

5 Record/Playback ............................................................................................................. 8 5.1 FPGA BSDK .................................................................................................................................................... 8 5.2 Host BSDK ..................................................................................................................................................... 8 5.3 FPGA MBDK ................................................................................................................................................... 8 5.4 Host MBDK .................................................................................................................................................... 8 5.5 Documentation ............................................................................................................................................. 8

6 RTDExSync ...................................................................................................................... 9 6.1 FPGA BSDK .................................................................................................................................................... 9 6.2 Host BSDK ..................................................................................................................................................... 9 6.3 FPGA MBDK ................................................................................................................................................... 9 6.4 Documentation ............................................................................................................................................. 9

7 Radio420 ....................................................................................................................... 10 7.1 BSP .............................................................................................................................................................. 10 7.2 FPGA BSDK .................................................................................................................................................. 10 7.3 Host BSDK ................................................................................................................................................... 10 7.4 FPGA MBDK ................................................................................................................................................. 10 7.5 Host MBDK .................................................................................................................................................. 10

3

7.6 Documentation ........................................................................................................................................... 10

8 MI125 ........................................................................................................................... 11 8.1 BSP .............................................................................................................................................................. 11 8.2 FPGA BSDK .................................................................................................................................................. 11 8.3 Host BSDK ................................................................................................................................................... 11 8.4 FPGA MBDK ................................................................................................................................................. 11 8.5 Host MBDK .................................................................................................................................................. 11 8.6 Documentation ........................................................................................................................................... 11 8.7 Limitations .................................................................................................................................................. 11

9 MO1000 ........................................................................................................................ 12 9.1 BSP .............................................................................................................................................................. 12 9.2 FPGA BSDK .................................................................................................................................................. 12 9.3 BSDK Windows ............................................................................................................................................ 12 9.4 FPGA MBDK ................................................................................................................................................. 12 9.5 Host MBDK .................................................................................................................................................. 12 9.6 Documentation ........................................................................................................................................... 12 9.7 Limitations .................................................................................................................................................. 12

10 Timestamp .................................................................................................................... 13 10.1 FPGA BSDK .................................................................................................................................................. 13 10.2 Host BSDK ................................................................................................................................................... 13 10.3 FPGA MBDK ................................................................................................................................................. 13 10.4 Documentation ........................................................................................................................................... 13

11 RTDExTs ........................................................................................................................ 13 11.1 Host BSDK ................................................................................................................................................... 13 11.2 Documentation ........................................................................................................................................... 13

12 Other modules .............................................................................................................. 14 12.1 Aurora Module ............................................................................................................................................ 14 12.2 ADAC250 Module ........................................................................................................................................ 14 12.3 MI250 Module ............................................................................................................................................ 14 12.4 LVDS-xIn-xOut Module ................................................................................................................................ 14 12.5 ADC5000 Module ........................................................................................................................................ 14 12.6 Mestor LVDS Module .................................................................................................................................. 14

13 Release 6.6.0 ................................................................................................................. 15 13.1 Perseus 601x General ................................................................................................................................. 15 13.2 MI125 .......................................................................................................................................................... 16 13.3 MO1000 ...................................................................................................................................................... 16 13.4 Other modules ............................................................................................................................................ 18

4

1 Software tools - General

1.1 BSP

Removed

All BSP examples have been removed from the software suite.

1.2 FPGA BSDK

New

Support of Xilinx ISE 14.7 Support of the Perseus611x carrier Support of the new cores for Perseus601x

RTDExSync

Timestamp

Updated

All BSDK examples have been modified with up to date cores and now use standardized addressing for custom registers.

All cores and example projects have been modified to fit the new folder architecture.

1.3 Host BSDK

New

Host libraries and applications now support compilation in Visual Studio 2012. Host libraries source code has been added to the release. Users can now modify them to suit their needs. Example applications have been added to better showcase the use of our FMC modules and FPGA cores. A new example architecture has been implemented. Support of the new host modules

RTDExSync

RTDExTS

Timestamp

Updated

Command Line Interface has been updated with new features. The bus_access library has been rendered obsolete. A connection state is now used for all host C functions. All libraries, applications and examples have been modified to fit the new folder architecture.

1.4 GNU Radio

Updated.

GNU Radio Plug-in has been modified to use new folder architecture.

1.5 FPGA MBDK

New

Support of MATLAB 2013B. Support of the Perseus611x carrier. Support of the new cores for Perseus601x.

RTDExSync

Timestamp

Updated

Nutaq’s MBDK compilation flow has been improved to support multiple carrier types. All MBDK examples have been modified with up to date blocks and now use standardized addressing for

custom registers. All blocks and examples have been modified to fit the new folder architecture.

5

1.6 Host MBDK

Removed

Host MBDK is currently not supported in this release.

1.7 Documentation

New

Upgrading to ADP 7.0.pdf

2 Perseus601x

2.1 General

New

Perseus601x uses Central Command Engine (CCE) version 3.2.

2.2 BSP

Removed

All BSP examples have been removed from the software suite.

2.3 Host BSDK

New

Added Carrier module in EAPI for carrier based functions.

2.4 FPGA BSDK

New

Added Carrier detection to differentiate between Perseus601x and 611x.

2.5 FPGA MBDK

Update

Perseus601x MBDK support has been updated for MATLAB 2013B and Nutaq’s new MBDK compilation flow.

2.6 Documentation

New

The Perseus Programmer’s Reference Guide document has been created.

Updated

The Perseus User’s Guide has been modified. All software related information has been moved to the Perseus Programmer’s Reference Guide document.

The Perseus App Notes have been modified to reflect the new folder architecture.

6

3 Perseus611x

3.1 General

New

Perseus611x uses Central Command Engine (CCE) version 3.2

3.2 Host BSDK

New

Added Perseus611x support for the following modules at the host level RTDEx Record/Playback Custom registers System Monitor Firmware update and bitstream flashing

Added Carrier module in EAPI for carrier based functions.

3.3 FPGA BSDK

New

Added Perseus611x support for the following modules at the FPGA level RTDEx Record/Playback Custom registers System Monitor Firmware update and bitstream flashing

Added Carrier detection to differentiate between Perseus601x and 611x

3.4 FPGA MBDK

New

Perseus611x MBDK support has been added for MATLAB 2013B and Nutaq’s new MBDK compilation flow. Added Perseus611x support for the following modules at the FPGA level

RTDEx Record/Playback Custom registers

3.5 Documentation

New

The Perseus Programmer’s Reference Guide document has been created.

Updated

The Perseus User’s Guide has been modified. All software related information has been moved to the Perseus Programmer’s Reference Guide document.

The Perseus App Notes have been modified to reflect the new folder architecture and to detail Perseus611x support.

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4 RTDEx

The RTDEx core is fully supported for both Gigabit Ethernet and PCI Express on both the Perseus601x and Perseus611x as described in the following sections.

4.1 FPGA BSDK

New

Support of the core on Perseus611x. BSDK example for Perseus611x on both Gigabit Ethernet and PCI Express.

Updated

RTDEx cores now support Xilinx ISE 14.7. BSDK example for Perseus601x on both Gigabit Ethernet and PCI Express modified with up to date core and

with standardized custom register addressing.

4.2 Host BSDK

New

RxStreaming and TxStreaming applications have been introduced. RTDEx examples have been modified to fit new example architecture. Batch and shell scripts have been

added. All applications and examples are supported on Perseus611x.

Updated

The RTDEx host C library has been modified to use a connection state instead of the obsolete bus_access handle.

Removed

The RTDEx Command Line Interface class has been removed.

4.3 FPGA MBDK

New

Support of the block on Perseus611x. MBDK example for Perseus611x on both Gigabit Ethernet and PCI Express.

Updated

FPGA MBDK block for the RTDEx has been modified for the use of MATLAB 2013B and Nutaq’s updated MBDK flow.

MBDK example for Perseus601x on both Gigabit Ethernet and PCI Express modified with up to date block and with standardized custom register addressing.

4.4 Host MBDK

Removed

Host MBDK block for the RTDEx is not supported in the present release.

4.5 Documentation

Updated

RTDEx Programmer’s Reference Guide has been updated with the application descriptions. RTDEx and Record Playback Examples Guide and RTDEx MDBK html documents have been modified with

the up to date example procedure.

8

5 Record/Playback

The Record/Playback core is fully supported on both the Perseus601x and Perseus611x as described in the following sections.

5.1 FPGA BSDK

New

Support of the core on Perseus611x. BSDK example for Perseus611x on both Gigabit Ethernet and PCI Express.

Updated

Record/Playback cores now support Xilinx ISE 14.7. BSDK example for Perseus601x on both Gigabit Ethernet and PCI Express modified with up to date core and

with standardized custom register addressing.

5.2 Host BSDK

New

Record/Playback dedicated applications have been introduced. Record/Playback examples have been modified to fit new example architecture. Batch and shell scripts

have been added. All applications and examples are supported on Perseus611x.

Updated

The ram and recplay Command Line Interface classes have been replaced with the rtdex_recplay class and its functions.

The recplay host C library has been modified to use a connection state instead of the obsolete bus_access handle.

5.3 FPGA MBDK

New

Support of the block on Perseus611x. MBDK example for Perseus611x on both Gigabit Ethernet and PCI Express.

Updated

FPGA MBDK block for the Record/Playback has been modified for the use of MATLAB 2013B and Nutaq’s updated MBDK flow.

MBDK example for Perseus601x on both Gigabit Ethernet and PCI Express modified with up to date block and with standardized custom register addressing.

5.4 Host MBDK

Removed

Host MBDK block for the Record/Playback is not supported in the present release.

5.5 Documentation

Updated

Record Playback Programmer’s Reference Guide has been updated with the application descriptions. RTDEx and Record Playback Examples Guide and Record/Playback MDBK html documents have been

modified with the up to date example procedure.

9

6 RTDExSync

The RTDExSync core is introduced with full support for Perseus601x as described in the following sections.

6.1 FPGA BSDK

New

RTDExSync core has been introduced. BSDK example for Radio420 and RTDExSync on PCI Express.

6.2 Host BSDK

New

RTDExSync host C library has been introduced. RTDExSync dedicated applications have been added. A Radio420 RTDExSync example has been added.

6.3 FPGA MBDK

New

RTDEx block has been modified to add a RTDExSync mode. MBDK example for Radio420 and RTDExSync on PCI Express.

6.4 Documentation

New

RTDExSync Programmer’s Reference Guide document has been added. Radio420 – RTDExSync Examples Guide document has been added. RTDExSync MBDK html documentation has been added.

10

7 Radio420

The Radio420 FMC is fully supported on the Perseus601x as described in the following sections. It is not yet supported on the Perseus611x carrier.

7.1 BSP

Removed

BSP example has been removed from release.

7.2 FPGA BSDK

New

Radio420 RTDExSync BSDK example on PCI Express has been introduced.

Updated

Radio420 core has been updated for use in Xilinx ISE 14.7 Radio420 core IQ data interfaces have been modified for both RX and TX. IQ interleaving and deinterleaving

is now done inside the core and is no longer the designer’s responsibility. Radio420 RTDEx Record/Playaback examples for Gigabit Ethernet and PCI Express have been modified with

up to date core and with standardized custom register addressing.

7.3 Host BSDK

Updated

Radio420 API has been modified to control up to 4 MI125 FMC per carrier.

New

Radio420_Init application has been introduced. Radio420 examples have been modified to fit new example architecture. Batch and shell scripts have been

added.

7.4 FPGA MBDK

New

Radio420 RTDExSync MBDK example on PCI Express has been introduced.

Updated

FPGA MBDK block for the Radio420 has been modified for the use of MATLAB 2013B and Nutaq’s updated MBDK flow.

Radio420 MBDK block IQ data interfaces have been modified for both RX and TX. IQ interleaving and de-interleaving is now done inside the core and is no longer the designer’s responsibility.

Radio420 RTDEx Record/Playaback examples for Gigabit Ethernet and PCI Express have been modified with up to date blocks and with standardized custom register addressing.

7.5 Host MBDK

Removed

Host MBDK block for the Radio420 is not supported in the present release.

7.6 Documentation

New

Radio420 – RTDExSync Examples Guide document has been added.

Updated

Radio420 Programmer’s Reference Guide has been updated with the Radio420_Init application description and new IQ data interfaces.

11

Radio420 Examples Guide and Radio420 MDBK html document have been modified with the up to date example procedure.

8 MI125

The MI125 FMC is fully supported on the Perseus601x as described in the following sections. It is not yet supported on the Perseus611x carrier.

8.1 BSP

Removed


8.2 FPGA BSDK

Updated

MI125 core has been updated for use in Xilinx ISE 14.7 MI125 Record example for Gigabit Ethernet has been modified with up to date cores and with standardized

custom register addressing.

8.3 Host BSDK

Updated

MI125 API has been modified to control up to 4 MI125 FMC per carrier.

New

MI125_Init application has been introduced. MI125 examples have been modified to fit new example architecture. Batch and shell scripts have been

added. MO1000-MI125 examples have been modified to fit new example architecture. Batch and shell scripts have

been added.

8.4 FPGA MBDK

Updated

FPGA MBDK block for the MI125 has been modified for the use of MATLAB 2013B and Nutaq’s updated MBDK flow.

MI125 Record example for Gigabit Ethernet has been modified with up to date block and with standardized custom register addressing.

8.5 Host MBDK

Removed

Host MBDK block for the Mi125 is not supported in the present release.

8.6 Documentation

Updated

MI125 Programmer’s Reference Guide has been updated with the Mi125_Init application description. M125 Examples Guide and MI125 MDBK html document have been modified with the up to date example

procedure.

8.7 Limitations

When used in external clock mode, the clock must be between 67.5 MHz and 125 MHz.

12

9 MO1000

9.1 BSP

Removed


9.2 FPGA BSDK

Updated

MO1000 core has been updated for use in Xilinx ISE 14.7 MO1000 example for Gigabit Ethernet and PCI Express has been modified with up to date cores and with

standardized custom register addressing.

9.3 BSDK Windows

Updated

MO1000 API has been modified to control up to 4 MO1000 FMC per carrier.

New

MO1000_Init application has been introduced. MO1000 examples have been modified to fit new example architecture. Batch and shell scripts have been

added. MO1000-MI125 examples have been modified to fit new example architecture. Batch and shell scripts have

been added.

9.4 FPGA MBDK

Updated

MO1000 FPGA MBDK block has been modified for the use of MATLAB 2013B and Nutaq’s updated MBDK flow.

MO1000 example for Gigabit Ethernet and PCI Express has been modified with up to date blocks and with standardized custom register addressing.

9.5 Host MBDK

Removed

Host MBDK block for the MO1000 is not supported in the present release.

9.6 Documentation

New

MO1000 Programmer’s Reference Guide has been updated with the MO1000_Init application description. MO1000 Examples Guide and MO1000 MDBK html document have been modified with the up to date

example procedure.

9.7 Limitations

Due to the amount of power required by the MO1000 FMC in a double-stack configuration, every Perseus on the field prior to November 1

st 2014 needs to be modified to work properly in that mode, otherwise,

unexpected reboot of the FMC can occur. The I2C communication with the MO1000 sometimes hangs. A reconfiguration of the MO1000 should be

performed to get back to normal operation. There is a remote possibility (<1% chance) the MO1000 FMC calibration will take longer than usual, possibly

terminating with an error code. If this happens, the calibration should be re-executed to get back to normal operation.

All the tests were performed with a maximum data rate of 250MHz. Data rates up to 300MHz can be achieved by design, but will not be supported by Nutaq. Use at your own risk.

13

In a dual stack master-slave clock configuration, there could be variable output skews (from boards configuration to next configuration) between the outputs of the master and the slave boards for DAC interpolation rates of 2x, 4x and 8x using the revision C of the board.

10 Timestamp

The Timstamp core is introduced with full support for Perseus601x as described in the following sections.

10.1 FPGA BSDK

New

Timestamp core has been introduced. Timestamp core has been added to Radio420 RTDex Record/Playback example;

10.2 Host BSDK

New

Timestamp host C library has been introduced. A timestamp application has been introduced. Radio420 examples have been modified to add the timestamp application.

10.3 FPGA MBDK

New

Timestamp MBDK block has been introduced. Timestamp block has been added to Radio420 RTDex Record/Playback example;

10.4 Documentation

New

Timestamp Programmer’s Reference Guide document has been added. Timestamp MBDK html documentation has been added.

11 RTDExTs

The RTDExTs software module is introduced with full support for Perseus601x as described in the following sections.

11.1 Host BSDK

New

RTDExTs host C library has been introduced. RTDExSync dedicated applications have been added. A Radio420 RTDExSync example has been added.

11.2 Documentation

New

RTDExSync Programmer’s Reference Guide document has been added. It contains a section on RTDExTS

14

12 Other modules

12.1 Aurora Module

Release 7.0 does not support the Aurora module.

12.2 ADAC250 Module

Release 7.0 does not support the ADAC250 module.

12.3 MI250 Module

Release 7.0 does not support the MI250 module.

12.4 LVDS-xIn-xOut Module

Release 7.0 does not support the LVDS XinXout module.

12.5 ADC5000 Module

Release 7.0 does not support the ADC5000 module.

12.6 Mestor LVDS Module

Release 7.0 does not support the Mestor LVDS module.

15

13 Release 6.6.0

13.1 Perseus 601x General

13.1.1 General

Starting from CCE version 2.12.12, update to a new CCE (or older CCE as long as it is more recent than 2.12.12) can be done through the CLI.

13.1.2 BSP

New

Added MO1000 BSP support

13.1.3 BSDK Windows

New

Added MO1000 BSDK support Added System Monitor BSDK support and inserted System Monitor core in all BSDK examples.

Updated

Added CLI functionality CLI will halt script after first command error

13.1.4 BSDK Linux

Added MO1000 BSDK support

13.1.5 MBDK

New

Added MO1000 MBDK support Added System Monitor BSDK support and inserted System Monitor core in all BSDK examples.

13.1.6 Documentation – Major changes

New

Upgrading to ADP 6.6.pdf MO1000 Programmer's Reference Guide MO1000 Examples document for Perseus

MO1000 MBDK html documentation

MO1000 User's Guide PicoDigitizer User’s Guide has been split in two documents, the PicoDigitizer125 User’s Guide (for both

PicoDIgitizer125 and PicoDigitizer125-1000) and the PicoDigitizer250.

Updated

Added MO1000 module to the CLI Programmer’s Reference Guide The Perseus MBDK User’s Guide has been updated for MO1000.

16

The Matlab demonstration documentation listing has not been updated for MO1000. The System Monitor module has been added to the Perseus User’s Guide. Added Software Support section to the PicoSDR and PicoDigitizer User’ Guides Modified Perseus Firmware Update document to use modified update_cce command. Modified the Programmer’s Reference Guide RTDEx to add the section 6.6 “Increasing the Throughput of

the PCIe RTDEx”

13.2 MI125

13.2.1 BSP

New

Added MO1000-MI125 stack BSP support BSP example

Corrected an issue that could prevent the MI125 calibration phase to succeed Corrected an issue that could cause sample errors in the MI125 acquisition even if the MI125 calibration

succeeded.

13.2.1.1 BSDK Windows

Added MO1000-MI125 stack BSDK support. Visual Studio example

Increased data retrieval speed in record example. Corrected an issue that could prevent the MI125 calibration phase to succeed

13.2.2 BSDK Linux

Added MO1000-MI125 stack BSDK support Makefile example

Increased data retrieval speed in record example.

13.2.3 MBDK

Added MO1000-MI125 stack BSDK support MBDK example

Corrected an issue that could prevent the MI125 calibration phase to succeed

13.2.4 Documentation

Added MO1000-MI125 stack example procedure in the MO1000 Perseus Examples document Modified MI125 BSDK and MBDK example documents with up to date screenshots

Corrected the MI125 FMC HPC pinout in the MI125 User’s Guide.

13.2.5 Limitations

When used in external clock mode, the clock must be between 67.5 MHz and 125 MHz.

13.3 MO1000

13.3.1 BSP

New

Added BSP support MO1000 FPGA core MO1000 driver library MO1000 BSP example

17

13.3.2 BSDK Windows

New

Added BSDK support for Windows

MO1000 EAPI module MO1000 CLI module Xilinx Platform Studio example Visual Studio example CLI examples

13.3.3 BSDK Linux

New

Added BSDK support for Linux

MO1000 EAPI module MO1000 CLI module Makefile example CLI examples

13.3.4 MBDK

New

Added MBDK support MO1000 MBDK FPGA block MO1000 MBDK FPGA example model MO1000 MBDK Host block MO1000 MBDK Host example model

13.3.5 Documentation

New

Added MO1000 Programmer's Reference Guide Added MO1000 Examples document for Perseus

Added MO1000 User's Guide Added MO1000 MBDK html documentation Added MO1000 module to CLI Programmer’s reference Guide

13.3.6 Limitations

Due to the amount of power required by the MO1000 FMC in a double-stack configuration, every Perseus on the field prior to November 1

st 2014 needs to be modified to work properly in that mode, otherwise,

unexpected reboot of the FMC can occur. The I2C communication with the MO1000 sometimes hangs. A reconfiguration of the MO1000 should be

performed to get back to normal operation. There is a remote possibility (<1% chance) the MO1000 FMC calibration will take longer than usual, possibly

terminating with an error code. If this happens, the calibration should be re-executed to get back to normal operation.

All the tests were performed with a maximum data rate of 250MHz. Data rates up to 300MHz can be achieved by design, but will not be supported by Nutaq. Use at your own risk.

In a dual stack master-slave clock configuration, there could be variable output skews (from boards configuration to next configuration) between the outputs of the master and the slave boards for DAC interpolation rates of 2x, 4x and 8x using the revision C of the board.

18

13.4 Other modules

13.4.1 RTDEx Module

A new mode of operation of the RTDEx_Receive function has been added. The mode (eRTDExWaitTimeoutOrFirstError) will return with valid data after the first packet discontinuity in the data stream. This mode is responsible for the data retrieval speed upgrade when using the record/playback module. This mode of operation is only pertinent on the Gigabit Ethernet medium.

13.4.2 Record/Playback Module

The adp_record_playback.c wrapper file has been modified to use the new RTDEx mode in order to significantly improve the performance of reading data from the Perseus memory.

13.4.3 Aurora Module

This module software support was not changed in this release

13.4.4 Radio420 Module

Adjustments have been made to both the TX and RX automatic calibrations done by the Radio420 modules of the CCE. These adjustments are embedded in the CCE and the Radio420 standalone Microblaze library.

The LO leakage and Sideband suppression calibrations of the TX have been improved to produce better results across the frequency range of the Radio420.

The RX DC Offset calibration has also been improved to successfully calibrate the DC offset across all gain setups of the Radio420 RX.

The Radio420 4x4 example has been modified to correct a release 6.5 problem in the initialization of the second Perseus

13.4.5 ADAC250 Module


13.4.6 MI250 Module


13.4.7 LVDS-xIn-xOut Module


13.4.8 ADC5000 Module


13.4.9 Mestor LVDS Module


13.4.10 2x10GE SFP+ Module


19

13.4.11 QSFP SFP+ Module


13.4.12 Unsupported Modules

The following modules are not supported by the release 6.6 of ADP Software Tools:

USB-2-GPIO-32 adapted Radio421

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