Characteristics of Digital IC’s :-

Voltage and Current Parameters

Fan-out

Noise Margin

Propagation Delay (Speed of Operation)

Power Dissipation

Operating Temperature

Contents

Characteristics of Digital IC’s Voltage and Current Parameters

Voltage parameters (Threshold Levels)Ideally the input voltage levels of 0V & + 5V (for TTL) are called as logic 0 & 1 levels.But practically it’s not always possible to obtain voltage levels exactly as the these values. Hencethere’s the necessity to define the worst case input voltages.

0

Logic 1

Logic0

Input voltage

Undefined

VCC (supply)

VIH (min)

VIL (max)

t(a) Input voltage parameters

(I) VIL (max) - Worst case low level input voltage : This is the maximum value of input voltage which will be considered as a logic 0 level. Ifthe input voltage is higher than VIL (max), then it won’t be treated as a low (0) input level.

(II) VIH (MIN) - Worst case high level input voltage :This is the minimum value of the input voltage which will be considered as a logic 1 level. If the input voltage is lower than VIH (min), then it will not be treated as a high (1) input.

(III) VOH (max) - Worst case high level output voltage :This is the minimum value of the output which will be considered as a logic HIGH(1) level. If the output voltage is lower than this level then it won’t be treated as a HIGH(1)output.(IV) VOL (max) - Worst case low level output voltage :This is the maximum value of the output voltage which will be considered as a logic LOW(0) level. If the output voltage is higher than this value then it won’t be treated as a LOW(0) output.LOW(0) output.

0

UndefinedLogic 0

Logic 1

VOH (min)

t

Output voltage

(b) Output voltage parameters

VCC (supply)

V OL(max)+

+

_ _VOH VIH

LOW HIGH

HIGH

+

+

_ _VOL VIL

HIGH LOW1 LOW

Voltage parameters on a logic circuit

LOW HIGH

Current parameters :(a) IIL - Low level input currentIt is the current that flows into the input when a low level input voltage in the specifiedrange is applied.

(b) IIH - High level input current :It is the current that flows into the input when a high level voltage input voltage in the specified range is applied.

(c) IOL - Low level output current:This is the current that flows from the output when the output voltage is in the

specifiedlow(0) voltage range and a specified load is applied.

(d) IOH - High level output current :This the current flowing from the output when the output voltage is in the specifiedHIGH(1) voltage range and a specified load is applied.

If the output current floes into the output terminal then it is called as a sinking currentand if the output current flows away from the output terminal then it is called as a sourcing current.

HIGH

LOW

+5 V

LOWHIGH

IOL IIL

HIGHLOW

LOW

HIGH

IOH IIH

Current Parameters

For example, the fan – out of the driving gate which is driving N number of gates is N. Fan – out is also called as the loading factor. If the specified fan – out of a gate is 10 then we should not load it more than 10 gates. Fan – out depends on the nature of input devices that are connected to an output.

Fan – out:Fan-out is defined as the maximum number of inputs of the same ICfamily that a gate can drive without falling outside the specified output voltage limits. Higher the fan out higher the current supplying capacity of gate.

Driver gate

N number of load gates

Fan - out

Noise Margin :Noise Immunity is defined as the ability of a logic circuit to tolerate the noise without causing any unwanted changes in the outputs.A quantitative measure of noise immunity is called as noise margin.

Invalid

Invalid

Valid l logic “1”

Valid logic “ “0”

Valid logic “1”

Valid logic “0”

(a) Input profile (b) (b) Output profile

VNL

Voltage VOH (min)

VIH (min)

VIL (max)

VOL (max)

VNH

The difference between VOH (min) and VIH (min) is known as the high level noise margin VNH. Similarly the difference between VIL (max) and VOL (max) is called as the low level noise margin VNL.

High level noise margin, VNH = VOH (min) - VIH (min)

Low level noise margin, VNL = VIL (max) - VOL (max)

Propagation Delay : (Speed of Operation):Propagation delay is defined as time delay between the instant of application of an input pulse and the instant of occurrence of the corresponding outputpulse.

+VccOutput

H H

L

H

L

H

Input

Output

Input

Output

50%

50%

50%

50%tPHL tPHLtPLH tPLH

Input

Input

Output

From the above figure the two propagation delays observed are:

1. tPHL : The propagation delay measured when the output is making a transition from HIGH(1) to LOW(0) state.

2. tPLH : The propagation delay measured when the output makes a transition from LOW(0) to HIGH(1) state.

Power Dissipation :

There should be reduction in the power dissipation taking place in the logic IC in order to protect the IC against damage due to excessive temperature, to reduce the loading on power supplies. Another importance of power dissipation is that the product of power dissipation & propagation time is always constant. Therefore reduced power dissipation may lead to increase in propagation delay.We have, P = VCC X ICC where ICC = current drawn from power supply.

The values of ICCH & ICCL are measured with open circuited outputs (no load), because the load will change with these values. ICCH & ICCL are of different values. Hence, ICC (avg) = (ICCH + ICCL) / 2

PD (av) = VCC x ICC (avg)

00

0

0

00

0

0

0

01

1

1

1

1

1

11

11

11

+VCC+VCC

ICCH ICCL

Power dissipation

ICCH = current drawn with all its outputs high.

ICCL = current drawn with all outputs “0”,

11

Operating TemperatureThe temperature range acceptable for the consumer and industrial applications is

o o o o

0 to 70 C and that for the military applications is -55 C to 125 C.

The performance of gates will be in the specified limits over these temperature ranges.

TopicsTopics

2 INPUT TTL NAND GATE2 INPUT TTL NAND GATE

TOTEM POLE OUTPUT STAGETOTEM POLE OUTPUT STAGE

UNCONNECTED INPUTSUNCONNECTED INPUTS

OPEN COLLECTOR OUTPUTSOPEN COLLECTOR OUTPUTS

WIRED ANDINGWIRED ANDING

Multiple Emitter TransistorMultiple Emitter Transistor

The multiple emitter transistor can have upto 8 emitters for an 8 The multiple emitter transistor can have upto 8 emitters for an 8 input NAND Gate.input NAND Gate.

D1,D2D1,D2BE JunctionsBE Junctions D3D3CB Junction.CB Junction. The transistor can be turned ON by forward biasing either D1 or The transistor can be turned ON by forward biasing either D1 or

D2(or both).D2(or both). The transistor will be OFF if and only if The transistor will be OFF if and only if bothboth the BE junctions are the BE junctions are

reverse biased.reverse biased.

Two Input TTL NAND GateTwo Input TTL NAND Gate

A and B are input terminals.A and B are input terminals.

They can either be Low(0 Volts They can either be Low(0 Volts ideally) or High(+Vcc ideally).ideally) or High(+Vcc ideally).

Operation:-Operation:- Case 1 :- A and B both LOWCase 1 :- A and B both LOW Case 2 :- Either A or B LOWCase 2 :- Either A or B LOW Case 3 :- A and B both HIGHCase 3 :- A and B both HIGH

Case 1- A and B both LowCase 1- A and B both Low

Both BE Junctions of transistor Q1 are Both BE Junctions of transistor Q1 are forward biased.forward biased.

D1 And D2 will conductD1 And D2 will conduct

Voltage at C is forced to 0.7VVoltage at C is forced to 0.7V

Q2 is OFF.Collector Voltage Vx Rises Q2 is OFF.Collector Voltage Vx Rises to +Vcc.to +Vcc.

Q3 is in Emitter follower mode.Q3 is in Emitter follower mode.

Y=1 (HIGH)Y=1 (HIGH)

Case 2 – Either A or B LOWCase 2 – Either A or B LOW

One input is grounded and the other is One input is grounded and the other is left open or connected to Vcc.left open or connected to Vcc.

Voltage at C is forced to 0.7VVoltage at C is forced to 0.7V

Q2 is OFF.Collector Voltage Vx Rises Q2 is OFF.Collector Voltage Vx Rises to +Vcc.to +Vcc.

Q3 is in Emitter follower mode.Q3 is in Emitter follower mode.

Y=1 (HIGH)Y=1 (HIGH)

Case 3- A and B both HIGHCase 3- A and B both HIGH

Both inputs A and B are Both inputs A and B are connected to +Vccconnected to +Vcc

D1 and D2 are reverse biased.D1 and D2 are reverse biased. D3 is forward biased.D3 is forward biased.

Base current is supplied to Base current is supplied to transistor Q2 via R1 and D3transistor Q2 via R1 and D3

Q3 is OFF as voltage as X Q3 is OFF as voltage as X drops down.drops down.

Q4 is turned ON as voltage at Q4 is turned ON as voltage at Z increases.Z increases.

As Q4 goes into saturation, As Q4 goes into saturation, Y=0 (LOW)Y=0 (LOW)

Totem Pole Output StageTotem Pole Output Stage

The arrangement of Q3 and Q4 on The arrangement of Q3 and Q4 on the Output side of TTL NAND the Output side of TTL NAND Gate.Gate.

With QWith Q33 in the circuit , current in the circuit , current

flowing through Rflowing through R33 will be zero will be zero

when output Y=0,and Qwhen output Y=0,and Q44will will

become ON, which reduces the become ON, which reduces the power dissipation.power dissipation.

AdvantagesAdvantages

Q3 is ON and acting in the Q3 is ON and acting in the Emitter follower mode. It will Emitter follower mode. It will therefore have a very low therefore have a very low output impedance.output impedance.

Therefore the output time Therefore the output time constant will be very short for constant will be very short for charging up any capacitive charging up any capacitive load on the output. load on the output.

Unconnected InputsUnconnected Inputs

If any input of TTL NAND Gate is left open, disconnected or floating,it If any input of TTL NAND Gate is left open, disconnected or floating,it acts as if logic 1 is applied to it.acts as if logic 1 is applied to it.

Therefore,the corresponding BE junction of the input transistor is not Therefore,the corresponding BE junction of the input transistor is not forward biased.forward biased.

Open Collector CircuitOpen Collector Circuit

It is the same 2 Input TTL It is the same 2 Input TTL NAND Gate but with R3 NAND Gate but with R3 and Q3 removed.and Q3 removed.

The collector point of Q4 is The collector point of Q4 is brought out as output.brought out as output.

External resistance R3 is External resistance R3 is connected for proper connected for proper operation.It is known as operation.It is known as pull up resistance.pull up resistance.

OperationOperation

Case 1- Case 1- A=B=0 A=B=0 Y=1Y=1

Case 2- Case 2- Either A=1,B=0 Either A=1,B=0 or A=0,B=1 or A=0,B=1 Y=1Y=1

Case 3- Case 3- A=B=1A=B=1 Y=0 Y=0

Wire ANDingWire ANDing

Wire ANDing means tying the outputs Wire ANDing means tying the outputs of gates together to obtain AND of gates together to obtain AND function.function.

QQ4A4A & Q & Q4B 4B represent the output of the represent the output of the

transistors. A common output up transistors. A common output up resistance is used for output of resistance is used for output of transistors. Also the transistors Qtransistors. Also the transistors Q4A4A and and

QQ4B4B are operated as switches. are operated as switches.

1.1. MOS LOGIC FAMILYMOS LOGIC FAMILY2.2. MOSFET AS A SWITCH MOSFET AS A SWITCH 3.3. N-MOS INVERTERN-MOS INVERTER4.4. P-MOS INVERTERP-MOS INVERTER5.5. CMOS-LOGICCMOS-LOGIC6.6. CMOS NAND GATECMOS NAND GATE7.7. CMOS CHARACTERISTICSCMOS CHARACTERISTICS

MOS LOGIC FAMILYMOS LOGIC FAMILYMOSFETMOSFET

Depletion MosfetDepletion Mosfet Enhancement type mosfetEnhancement type mosfet

or E-Mosfet or E-Mosfet

P channel Mosfet N channel MosfetP channel Mosfet N channel Mosfet

(PMOS)(PMOS) (NMOS) (NMOS)

Gate is the Control Terminal Gate is the Control Terminal

MOS MOS TECHNOLOGYTECHNOLOGY

PMOS NMOS CMOSPMOS NMOS CMOS

(Uses P Channel E-MOSFETs) (N channel E-MOSFETs) (Uses PMOS & NMOS) (Uses P Channel E-MOSFETs) (N channel E-MOSFETs) (Uses PMOS & NMOS)

ADVANTAGES OF MOSFETs:ADVANTAGES OF MOSFETs: Easy & InexpensiveEasy & Inexpensive Small SizeSmall Size Consumes Little PowerConsumes Little Power

DISADVANTAGES OF MOSFETs:DISADVANTAGES OF MOSFETs: due to accumulation of Static Charges MOSFETs can get damage due to accumulation of Static Charges MOSFETs can get damage using the proper handling procedures, it possible to minimize the using the proper handling procedures, it possible to minimize the possibility of damagepossibility of damage

MOSFET AS A SWITCHMOSFET AS A SWITCHBiasing : Biasing : N-Channel MOSFETN-Channel MOSFET

DDrain to source voltage – Positiverain to source voltage – Positive VVGSGS Control Resistance Control Resistance

VVGS GS decide ON or OFFdecide ON or OFF

MOSFET OFFMOSFET OFF

If VIf VGSGS =0 ,MOSFET Turns OFF =0 ,MOSFET Turns OFF

drain current=0 drain current=0

If VIf VGSGS > V > VTT , MOSFET Turns ON , MOSFET Turns ON

MOSFET ON

N-MOS INVERTERN-MOS INVERTER

INVERTER with A PASSIVE LOADINVERTER with A PASSIVE LOAD

Resistor used as passive load .Resistor used as passive load .

OPERATIONOPERATION

VVinin < V < VTT ,Mosfet Will be OFF ,output=+ ,Mosfet Will be OFF ,output=+vvDDDD

VVinin > V > VTT , Mosfet Will be Fully On, output=0 , Mosfet Will be Fully On, output=0

PMOS INVERTERPMOS INVERTER Schematic Diagram :-Schematic Diagram :-

OPERATION :-OPERATION :-

VVinin =0 ,Y Output is High (-V =0 ,Y Output is High (-VDDDD))

VVinin= -5 V (logic 1) ,Output is Low(0). = -5 V (logic 1) ,Output is Low(0).

SUMMARYSUMMARY INPUT Vin Q2 OUTPUT Y

0 Volts(0) OFF -VDD (1)

-VDD (1) ON 0 (Logic0)

CMOS LOGICCMOS LOGIC

1.1. Use P & N channel mosfets connected in SERIES.Use P & N channel mosfets connected in SERIES.

2.2. Drains Connected Together .Drains Connected Together .

3.3. Input applied at common gate.Input applied at common gate.

ADVANTAGES OF CMOS LOGIC:-ADVANTAGES OF CMOS LOGIC:-

1.1. Faster Faster

2.2. Less Power ComsumptionLess Power Comsumption

CMOS IS USED AS :-CMOS IS USED AS :-

1.1. CMOS NAND GATE CMOS NAND GATE

2.2. CMOS NOR GATECMOS NOR GATE

CMOS NAND GATECMOS NAND GATESchematic DiagramSchematic Diagram

1.1.Q1 & Q2 are P – channel Mosfet.Q1 & Q2 are P – channel Mosfet.

2.2.Q3 & Q4 are N -channel Mosfet.Q3 & Q4 are N -channel Mosfet.

3.3.A controls status of MOSFETs Q1 & Q3.A controls status of MOSFETs Q1 & Q3.

4.4.B controls status of MOSFETs Q2 & Q4.B controls status of MOSFETs Q2 & Q4.

OPERATIONOPERATION

1.1. When A=B=0When A=B=0

1. Q1 & Q2 Will be ON 1. Q1 & Q2 Will be ON

2. Q3 & Q4 Will be OFF2. Q3 & Q4 Will be OFF

3. Y=+V3. Y=+VDDDD

2. When A=0,B=12. When A=0,B=1

1.1.Q1 is ON , Q3 is OFFQ1 is ON , Q3 is OFF

2.2. Q2 is OFF , Q4 Will Be ONQ2 is OFF , Q4 Will Be ON

3.3.Output=+VOutput=+VDDDD

3. When A=1 , B=03. When A=1 , B=0

1.1.Q1 is OFF , Q3 is ON.Q1 is OFF , Q3 is ON.2.2.Q2 is ON , Q4 is OFF.Q2 is ON , Q4 is OFF.

3.3.Output Y = +VOutput Y = +VDD DD

4. With A=1 , B=14. With A=1 , B=1

11. Q1 & Q2 Both are OFF. Q1 & Q2 Both are OFF

2. Q3 & Q4 both are ON2. Q3 & Q4 both are ON

3. Output Y =0 (LOW)3. Output Y =0 (LOW)

CMOS characteristicsCMOS characteristics:: Power supply voltagePower supply voltage::a)a) The 4000/14000 and 74c series operate over wide range of power supply The 4000/14000 and 74c series operate over wide range of power supply

voltage(3v to15v)voltage(3v to15v)

b)b) The other cmos families such as 74HC/HCT,74 AC/ACT,74AHC/AHCT The other cmos families such as 74HC/HCT,74 AC/ACT,74AHC/AHCT operate over voltage range of 2 to 6operate over voltage range of 2 to 6

Power dissipation:Power dissipation:a)a) power dissipation of cmos devices is very low when they are in static statepower dissipation of cmos devices is very low when they are in static state

b)b) Power dissipation is low under dc operating condition and at low Power dissipation is low under dc operating condition and at low frequencies but power dissipation increases as frequency increasesfrequencies but power dissipation increases as frequency increases

Frequency 0(dc) 100KHZ 1MHZ

Power dissipation

10nW 0.1mW mW

Switching speed:Switching speed:a)a) It can be faster than the NMOS or PMOS deviceIt can be faster than the NMOS or PMOS device

b)b) Switching speed for various CMOS icsSwitching speed for various CMOS ics

Static sensitivity:Static sensitivity:a)a) The MOS ICS are susceptible to damage due to staticThe MOS ICS are susceptible to damage due to static

electricity. such static electricity get generated due to electricity. such static electricity get generated due to

simple day to day actionsimple day to day action

b) Such damage is called electrostatic discharge(ESD)and b) Such damage is called electrostatic discharge(ESD)and

we have to use resister diode network for protectionwe have to use resister diode network for protection

Family 4000 74HC/HCT

74AC/ACT

74AHC

Propagation Delay

50ns 8ns 4.7ns 4.3ns

FAN OUT:FAN OUT:a)The input resistance of cmos device is very higha)The input resistance of cmos device is very high

So their input current is very small almost zero. so So their input current is very small almost zero. so

cmos gate can drive a large no of other cmos gates cmos gate can drive a large no of other cmos gates

Hence fan out of cmos device will be large asHence fan out of cmos device will be large as

compare to fan out of TTLcompare to fan out of TTL

b)Typically the fan out is restricted to 50 for operation below b)Typically the fan out is restricted to 50 for operation below 1 MHZ.1 MHZ.

Topics:-Topics:-

1.Tristate Logic o/p1.Tristate Logic o/p

2. Interfacing -2. Interfacing -

a.TTL driving CMOSa.TTL driving CMOS

b.CMOS driving TTLb.CMOS driving TTL

3.Comparison of CMOS & TTL3.Comparison of CMOS & TTL

Tristate Logic OutputTristate Logic Output

Fig:-A Tristate CMOS inverterFig:-A Tristate CMOS inverterWhen both MOSFETs are in the OFF state, the output is When both MOSFETs are in the OFF state, the output is in its high impedance state. in its high impedance state. When E=1, the inverter operates in a normal way.So here When E=1, the inverter operates in a normal way.So here either Qeither Q11 or Q or Q22 is ON depending on i/p A. is ON depending on i/p A.

But when E=0, both QBut when E=0, both Q11 & Q & Q22 are OFF irrespective of i/p are OFF irrespective of i/p

A.A.

Advantages Of CMOS :-Advantages Of CMOS :-

1.1. Low power dissipation.Low power dissipation.

2.2. High fan out.High fan out.

3.3. Capable of working over a wide range of supply Capable of working over a wide range of supply voltage.voltage.

4.4. High packaging density since MOS devices need High packaging density since MOS devices need less space.less space.

Disadvantages Of CMOS :-Disadvantages Of CMOS :-

1.1. Propagation delays longer than TTL.Propagation delays longer than TTL.

2.2. Slower than TTL.Slower than TTL.

3.3. Due to static charge it may damage.Due to static charge it may damage.

4.4. Need Protection circuitry.Need Protection circuitry.

INTERFACINGINTERFACING It means connecting the o/p of one sys. to the i/p of It means connecting the o/p of one sys. to the i/p of

another sys. with different char.another sys. with different char. Direct connections cannot be formed when electrical Direct connections cannot be formed when electrical

char. of two ckt are diff.char. of two ckt are diff. So “interface” circuit is inserted betn the “driver” & So “interface” circuit is inserted betn the “driver” &

“load” ckt.“load” ckt. The task of interface ckt. Is to accept the o/p of the The task of interface ckt. Is to accept the o/p of the

driver ckt. & “condition” it so that it is compatible with driver ckt. & “condition” it so that it is compatible with the load ckt.the load ckt.

Driver System

Interface

Load System

TTL Driving CMOSTTL Driving CMOS The o/p current capability of TTL ICs is much The o/p current capability of TTL ICs is much

higher than the I/p current values of CMOS ICs. higher than the I/p current values of CMOS ICs. So there is no problem for TTL to drive CMOS as So there is no problem for TTL to drive CMOS as far as current is concerned.far as current is concerned.

But there is problem when compare vtg. levels But there is problem when compare vtg. levels TTL & CMOS bcoz VTTL & CMOS bcoz VOH(min)OH(min) of TTL series is very of TTL series is very

low as compared with Vlow as compared with VIH(min)IH(min) reqd for CMOS reqd for CMOS

series like 400B, 74HC etc.series like 400B, 74HC etc. So as to raises the o/p level of TTL gate to about So as to raises the o/p level of TTL gate to about

+5V in the HIGH state an external pull up resistor +5V in the HIGH state an external pull up resistor is introduced as shown in fig.is introduced as shown in fig.

Fig. TTL Driving CMOSFig. TTL Driving CMOS

Introducing external pull up resistor will provide Introducing external pull up resistor will provide the sufficient vtg. Level at the i/p of the CMOS the sufficient vtg. Level at the i/p of the CMOS gate.gate.

TTL can also drive high vtg. CMOS.TTL can also drive high vtg. CMOS.

CMOS Driving TTLCMOS Driving TTL

Equivalent ckt. in HIGH state.Equivalent ckt. in HIGH state. Equivalent ckt. In LOW state. Equivalent ckt. In LOW state.

For For For For low low high high state state state state

o/p o/po/p o/p

Sr

No.

Para. For driving gate (CMOS) of 4000 B series

Para. For the load gate (TTL) of 74 series

1. VOH(min)=4.95 V VIH(min)=2 V

2. VOL(max)=0.05 V VIL(max)=0.8V

3. IOH(max)=0.4 mA IIH(max)=40µA

4. IOL(max)=0.4 mA IIL(max)=1.6mA

CMOS Driving TTL in HIGH stateCMOS Driving TTL in HIGH state Here the CMOS o/p vtg. is high (1) . From table…Here the CMOS o/p vtg. is high (1) . From table… From these we come to know that the CMOS o/p can supply From these we come to know that the CMOS o/p can supply

sufficient vtg. & current to the TTL inputs.sufficient vtg. & current to the TTL inputs.

CMOS Driving TTL in LOW stateCMOS Driving TTL in LOW state Here the CMOS o/p vtg. is low(0). From table…Here the CMOS o/p vtg. is low(0). From table… So, the low state o/p vtg. VSo, the low state o/p vtg. VOLOL of CMOS satisfy the V of CMOS satisfy the VILIL reqd. reqd.

of TTL. But Iof TTL. But IOL(max)OL(max) of CMOS gate is not sufficient to drive of CMOS gate is not sufficient to drive

even a single TTL gate with Ieven a single TTL gate with IIL(max)IL(max)=1.6 mA.So, use a non-=1.6 mA.So, use a non-

inverting buffer betn. CMOS & TTL to increase current inverting buffer betn. CMOS & TTL to increase current sourcing capacity.sourcing capacity.

Comparison of CMOS & TTLComparison of CMOS & TTLSr.

No.

Parameter

CMOS TTL

1. Device used N-channel & P-channel MOSFET

BJT

2. Noise immunity

Better than TTL Less than CMOS

3. Switching speed

Less than TTL Faster than CMOS

4. Power dissi/gate

PD=0.1 mW. Used for battery backup.

10 mW

5. Fan out Typically 50 10

6. Power supply vtg.

Flexible from 3V-15V

Fixed=5V

University Asked Questions:-University Asked Questions:-

Q.Explain Tristate logic o/p. (6M)Q.Explain Tristate logic o/p. (6M)

Q.Explain with neat diagram interfacing of a TTL Q.Explain with neat diagram interfacing of a TTL gate driving CMOS gate & vice versa. (8M)gate driving CMOS gate & vice versa. (8M)

Q.Difference between TTL & CMOS. (4M)Q.Difference between TTL & CMOS. (4M)