tute sample

8/11/2019 Tute Sample

1/4

T.A.Shashank Sheshar [email protected]

1.

Instruction Set Architecture (ISA)

Q.1.Consider an example processor which supports two-address, one-address and zero addressinstruction set. 24 bit instruction is placed in the 1024 word memory. If there exist 3 two-address

instruction, 100 one-address instructions then how many zero address instruction formulated.

SOL. 24 -bits

Step 1:

4 bit 10 bit 10 bit

Step 2: total #operation possible: 24

= 16.

Step 3: total #free combination possible after allocate higher instruction: 16-3=13.

Step 4: total # one address instruction possible: 13*210

.

Step 5: total #free combination possible after allocate one address instruction: 13312

(13*1024=13312). Zero address instruction = (13312-100)*210

=13212*210

.

2. Processor performance equation

Q.1.Assume a processor with instruction frequencies and costs

Integer ALU: 50%, 1 cycle

Load: 20%, 5cycle

Store: 10%, 1 cycle

Branch: 20%, 2cycle

Which change would improve performance more?

A. Branch prediction to reduce branch cost to 1 cycle?

B. Faster data memory to reduce load cost to 3 cycles?

SOL. Compute CPI

Base = 0.5*1 + 0.2*5 + 0.1*1 + 0.2*2 = 2 CPIA = 0.5*1 + 0.2*5 + 0.1*1+ 0.2*1 = 1.8 CPI (1.11x or 11% faster)

B = 0.5*1 + 0.2*3 + 0.1*1 + 0.2*2 = 1.6 CPI (1.25x or 25% faster)

B is the winner

Q.2. Suppose we have made the following measurements

Frequency of FP operations = 25%

Average CPI of FP operations = 4.0

O code Address 1 Address 2


2/4

Average CPI of other instructions = 1.33

Frequency of FPSQR= 2%

CPI of FPSQR = 20

Assume that the two design alternatives are to decrease the CPI of FPSQR to 2 or to decrease the

average CPI of all FP operations to 2.5. Compare these two design alternatives using the

processor performance equation.

SOL. CPIoriginal= CPI=1 k*Frequncy

= (4*25% ) + (1.33*75% ) = 2.0

CPIIwith newFPSQR= CPIoriginal - 2%*(CPIwith oldsFPSQR -CPIwith newFPSQR only)

= 2.02% *( 202) = 1.64

We can compute the CPI for the enhancement of all FP instructions the same way or by

summing the FP and non-FP CPIs. Using the latter gives us

CPInewFP = (75% *1.33) +( 25%*2.5) = 1.625

The speedup for the overall FP enhancement is

SpeedupnewFP = ( CPIoriginal / CPInewFP ) = (2/1.625) = 1.23

2. Number Representation

Q.1. Do the following calculations below in single precision floating point representation. Showthe floating point binary values for the operands, show the result of the add or subtract, then

show the final normalized binary representation.

(A) 0.5 + 0.3125,

(B) 123.875.

SOL. Each of the numbers can be represented in the following single precision floating point

format.

Sign (1 bit) Exponent (8 bits) (1),Fraction (23 bits)

(A)

0.5:

0 01111110 (1),00000000000000000000000

0.3125:

0 01111101 (1)01000000000000000000000


3/4

0.3125 After aligning the exponent:

0 01111110 (0)10100000000000000000000

0.3125+0.5:

0 01111110 (1)10100000000000000000000

Normalize the result:

0 01111110 10100000000000000000000

(B).12:

0 10000010 (1)10000000000000000000000

3.875

0 10000000 (1).11110000000000000000000

3.875 After aligning the exponent:

0 10000010 (0).0111110000000000000000012-3.875: use the 2s complement to represent the fractions, and do addition for two operands:

0 1.100000 (all zeros)

+ 1 1.100001 (all zeros)

0 1.000001 (all zeros)

Therefore the result is:

0 10000010 00000100000000000000000

3.

Addressing Modes

Q.1.A three byte long PC-relative instruction is stored in the memory with starting address of

304052 (decimal) onwards. If a (-31) signed displacement is present in the address field of the

instruction what is the next instruction address (effective address).

SOL.EA= PC+IR [address field value]

EA=304055 +(-31) =304024

Q.2. Find out the name of addressing modes presented and number of memory references of

following instructions-

1. ADD A [R0], @B


4/4

2. MOV R0, [2000][R1]

3. MOV Ax, [Bx][SI]

4. ADD @R0, @5000

SOL.1. Indexed and indirect addressing mode, 4[1(D)+1(S1)+2(S2)] memory references

2. Indirect Indexed addressing modes, 2[1-base address cal,1-read-write data] memory ref.

3. Base indexed addressing mode, 1[for read-write data] memory ref.

4. Memory indirect addressing mode, 4[1+1+2] memory ref.

tute sample

Documents