tutorial #1 for ise 8.1i project navigator using schematic ... · tutorial #1 for ise 8.1i project...

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Tutorial #1 for ISE 8.1i Project Navigator Using Schematic Example Written By Tariq Naqvi, CEng, MIET Step No.1: Click ISE Software Icon Link from your Desktop Step No.2: From the File menu open new project and fill out the screen as shown below and click Next

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Page 1: Tutorial #1 for ISE 8.1i Project Navigator Using Schematic ... · Tutorial #1 for ISE 8.1i Project Navigator Using Schematic Example Written By Tariq Naqvi, CEng, ... 1 for ISE Project

Tutorial #1 for ISE 8.1i Project Navigator Using Schematic Example Written By Tariq Naqvi, CEng, MIET

Step No.1: Click ISE Software Icon Link from your Desktop Step No.2: From the File menu open new project and fill out the screen as shown below and click Next

Page 2: Tutorial #1 for ISE 8.1i Project Navigator Using Schematic ... · Tutorial #1 for ISE 8.1i Project Navigator Using Schematic Example Written By Tariq Naqvi, CEng, ... 1 for ISE Project

Step No.3: Fill out the Device Properties Screen as shown below:

Page 3: Tutorial #1 for ISE 8.1i Project Navigator Using Schematic ... · Tutorial #1 for ISE 8.1i Project Navigator Using Schematic Example Written By Tariq Naqvi, CEng, ... 1 for ISE Project

What it all means? Hardware Identification:

What is Spartan-3 family ? The Spartan-3 solution is the latest platform FPGA offering from Xilinx it is bsed on the Virtex-II family architecture. What are the devices in the Spartan-3 family ? The Spartan-3 family consists of eight family members with following features: (Note: We are only using XC3S200 member)

Table 1: Spartan-3 Family XC3S200

XC3S200 System Gates 200K Logic Cells 4,320 Block RAM Blocks 12 Block RAM Bits 216K DCMs 4 IO Standards 23 Max Single Ended I/O 173 Max Differential I/O 76

Page 4: Tutorial #1 for ISE 8.1i Project Navigator Using Schematic ... · Tutorial #1 for ISE 8.1i Project Navigator Using Schematic Example Written By Tariq Naqvi, CEng, ... 1 for ISE Project

Step No. 4: Click New Srouce… Icon and choose Schematic as a source type. Fill out the fields as shown below:

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Step No.5: Click Add Symbol and from the left hand side sources menu, select Logic from under Categories section and select XOR2 from Symbols section. After adding the symbols place I/O markers at the inputs and the outputs. Complete the following simplified Half Adder circuit as shown below and click Save .

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Step No.6 Assigning Pin Location Constraints: This is to specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3 board. To constrain the design ports to package pins, do the following: 1. Verify that HalfAdder is selected in the Sources window. 2. Double-click the Assign Package Pins process found in the User Constraints process group. The Xilinx Pinout and Area Constraints Editor (PACE) opens. 3. Select the Package View tab. 4. In the Design Object List window, enter a pin location for each pin in the Loc column using the following information: . A input port connects to FPGA pin K13 (SW7 switch on board) . B input port connects to FPGA pin K14 (SW6 switch on board) . Sum output port connects to FPGA pin K12 (LD0 LED on board) . Carry output port connects to FPGA pin P14 (LD1 LED on board) Following figure shows the above process visually. SAVE and exit the following window

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Step No.7 Implementing the Design: 1. Select the HalfAdder source file in the Sources window. 2. Open the Design Summary by double-clicking the View Design Summary process in the Processes tab. 3. Double-click the Implement Design process in the Processes tab. 4. Notice that after Implementation is complete, the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings as shown in the following window.

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Step No.8 Download Design to the Spartan3 Board: This is the last step in the design verification process. This section provides simple instructions for downloading the HalfAdder design to the Spartan-3 board. 1. Connect the 5V DC power cable to the power input on the demo board (J4). 2. Connect the download cable between the PC and Spartan 3 board (J7). 3. Select Synthesis/Implementation from the drop-down list in the Sources window. 4. Select HalfAdder in the Sources window. 5. In the Processes window, click the “+” sign to expand the Generate Programming File processes. 6. Double-click the Configure Device (iMPACT) process. iMPACT opens and the Configure Devices dialog box is displayed as shown below: Picture

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7. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG). 8. Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected. 9. Click Finish. 10. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device in the JTAG chain as shown below, select the halfadder.bit file and click Open.

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11. If you get a Warning message, click OK. 12. Select Bypass to skip any remaining devices. 13. Right-click on the xc3s200 device image, and select Program... The Programming Properties dialog box opens as shown below. 14. Click OK to program the device. When programming is complete, the Program Succeeded message is displayed. On the board, LEDs 0 is lit (Carry Bit) when the Switches 7 & 8 are ON, indicating that the HalfAdder is running. 16. Close iMPACT without saving. You have completed the Tutorial #1 for ISE Project Navigator for Schematic Example