Tutorial: Creating an IP Core using Xilinx System Generator

Shawki Areibi, Matt Saunders

September 6, 2019

1 Introduction

Xilinx System Generator provides a set of Simulink blocks (models) for several hardware opera-tions that could be implemented on various Xilinx FPGAs. These blocks can be used to simulatethe functionality of the hardware system using the Simulink environment. The nature of mostDSP applications requires floating point format for data representation. While this is easy toimplement on several computer systems running high-level modeling software such as Simulink, itis more challenging in the hardware world due to the complexity of the implementation of floatingpoint arithmetic. These challenges increase with portable DSP systems where more restricting con-straints are applied to the system design. For these reasons, Xilinx System Generator uses fixedpoint format to represent all numerical values in the system. System generator provides someblocks to transform data provided from the software side of the simulation environment (in our caseit is Simulink) and the hardware side (System Generator blocks). This is an important concept tounderstand during the design process using Xilinx System Generator.

1.1 Objectives

This tutorial will demonstrate the process of creating a simple DSP system using Xilinx SystemGenerator 14.6. The System Generator runs within the Simulink simulation environment whichis part of the MATLAB mathematical package. In this tutorial a DSP system will be simulatedusing Simulink and then a Co-simulation is performed using the NEXYS A7 (Artix-7) Board. Co-simulation integrates Simulink simulation capabilities with a hardware implementation to verifythe functionality of the system.

The following steps are described in this tutorial:

• Starting System Generator with MATLAB.

• Creating a DSP system using Simulink.

• Preparing System Generator for co-simulation on the NEXYS A7 Board.

• Performing Hardware/Software Co-Simulation for the DSP system.

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1.2 System Requirements

You must have the following software installed on your PC to complete this tutorial:

• Windows 10 OS.

• Xilinx Vivado 2016.3

• System Generator 2016.3

• MATLAB R2015a with Simulink.

The following is required to complete this tutorial:

• Familiarity with Simulink Simulation Environment with MATLAB.

• Familiarity with Xilinx Vivado and FPGA design flow.

• NEXYS A7 (Artix-7) Board and micro USB cable.

2 Starting System Generator

• To start Xilinx System Generator, select → Xilinx Design Tools → System Gen-erator 2016.3. This will start MATLAB.

• Next, before opening Simulink, you will need to set up the environment, so MATLAB canrecognize your Nexys A7 board. Type the following command into the MATLAB CommandWindow:

xilinx.environment.setBoardFileRepos({’C:/Xilinx/Vivado/2016.3/data/boards/board files’})

• To start Simulink, create a new model by selecting New → Simulink Model. A blankSimulink model and the Library Browser should open, as shown in Figure 1.

• The Simulink Library Browser shows a list of all the different Toolboxes installed withinMATLAB. Xilinx System Generator components will appear under three categories:

1. Xilinx Blockset

2. Xilinx Reference Blockset

The category Xilinx Blockset contains all the basic blocks used in various applications andwill be used in this tutorial.

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Figure 1: A new Simulink model with the Library Browser visible.

3 Creating a DSP System

In this part of the tutorial, you will create a simple DSP system that will be used to evaluateEquation 1:

z = (5× x) + (3× y) (1)

The main operations required to implement this system are:

• Two multiplication operations

• One addition operation

• Two storage elements to store the factors (5, 3). In this tutorial we will use a constant blockfor these two factors.

For each of these operations, a Xilinx Blockset block exists. Additionally, every System Gener-ator model requires a System Generator block to perform various hardware operations on themodel.

3.1 Building the Hardware Model

In your model, we will place several blocks from the Xilinx Blockset category in the SimulinkLibrary Browser:

• Xilinx System Generator Block: The first block to be used in any System Generatormodel is the System Generator block. This block can be found in Xilinx Blockset → BasicElements → System Generator. Drag and drop the block into your model.

• Input/Output Gateways: are System Generator blocks that are used to convert datareceived from Simulink in the floating point format to fixed point format used inside the

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hardware system modeled using System Generator. Later, they convert the system outputback to floating point. There are two types of gateways provided by System Generator:

1. Input Gateways: are used at the input of the System Generator system to convertfloating point data into fixed point format. Select Xilinx Blockset→ Basic Elements→ Gateway In and drag and drop two of these blocks into your design.

The input gateways specify the details of the fixed point format. Three importantproperties are:

– Output type: three values can be assigned to this property: boolean (single bitdata), two-s complement, and unsigned.

– Number of bits: the higher number of bits, the higher the resolution of the system.

– Binary point: the position of the binary point in the fixed point format.

Double-click the input gateway to change its properties. The Gateway In propertieswindow will open. Set the output type for each gate to two’s complement, the numberof bits to 16, and the binary point to 12, as shown in Figure 2.

2. Output Gateways: are used to transform the data generated from the System Gener-ator in fixed point format into the floating point format required by Simulink. Outputgateways automatically detect the fixed point format from the system output and donot require any modification. Place one output gateway by selecting Xilinx Blockset→ Basic Elements → Gateway Out.

• Multipliers: Our model requires two multiplication operations. The Xilinx Blockset providesseveral blocks for arithmetic operations. To place a hardware multiplier block select XilinxBlockset → Math → Mult. Place two multipliers as shown in Figure 3. Double-click onthe Mult block to change its properties. There are two basic options for output precision:full, and user-defined. In our case, full precision requires 32 bits with the binary point at bitposition 24. In the user-defined precision mode, the designer can specify a different format,specifying the number of bits, the rounding mode, and the overflow behaviour. For thistutorial, we will use the full precision option. Additionally, under the Implementationmenu, the designer has the option of optimizing for speed or area, or just using lookup tables(LUTS) instead.

• Constants: The system we are building performs two multiplications between two inputs(variables) and two factors. For simplicity we will use constants to represent these two factors,although in a typical DSP application we might need to change these factors and we mayneed to use memory elements to do so. Constants are usually implemented using hardwiredconfigurations. Place two constants by selecting Xilinx Blockset → Basic Elements →Constant. Double-click on the constant block to display its properties, and change the valuesto 5 and 3 as shown in Figure 4. If you use fixed-point (signed two’s complement) then makesure you have enough bits to represent your number (e.g. 16 bits, binary point 12 would allowyou to represent fractions between +7 and -8). Connect the input gateways and the constantto the inputs of each multiplier: click the output terminal of the input gateway and, with themouse button held down, drag the connection link to one of the multiplier’s input terminals.Using the same approach connect the constants to the multiplier input as shown in Figure 4.

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Figure 2: Setting the parameters for the input gate.

• Adder/Subtractor: The final block we need to place in order to complete the system is theadder/subtractor block. Select Xilinx Blockset →Math → AddSub to place the AddSubblock. This block performs addition and subtraction operations for two operands. The fixedpoint format of the output is determined from the format of the inputs as shown in Figure5. Connect the outputs of the two multipliers to the inputs of the adder, and connect theoutput of the adder to the Gateway Out module.

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Figure 3: Adding multipliers.

Figure 5: Adding an Adder/Subtractor.

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Figure 4: Adding constants.

3.2 Preparing the Simulation Environment

After completing the hardware system we will use Simulink environment to verify its functionality.Simulink offers a very flexible simulation environment which allows building different testing sce-narios. For simplicity, we will build a testing scenario for our system by applying a constant inputto the system and display the result on a single value display.

• Inputs: Simulink provides several blocks that can be used as an input to models generatedand simulated using Simulink environment. These blocks can be found under the followingcategory: Simulink → Sources. From this category select Constant and place twoconstants in the model. Use the values 3.1 and 4.5 respectively. Connect these constants tothe two input gateways of the system as shown in Figure 6.

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Figure 6: Adding a Simulink Constant to apply an input to the system.

• Output: Simulink provides several blocks to display the simulation results of the model underinvestigation. These blocks can be found in the category: Simulink → Sinks. From thiscategory select Display which is used to display the value of a single output. Connect thisblock to the output of the system as shown in Figure 7.

Figure 7: Display the results in Simulink.

Figure 7 shows the complete model ready for simulation. Save your model to the file sg tut 1.mdlby selecting File → Save in the model window.

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4 Simulating a DSP system using System Generator and Simulink

The execution of the model can be simulated using several methods. First, we will use Simulink toperform a real-time simulation to verify the functionality of the design.

The simulation process can be started by clicking the Run button in the toolbar of themodel window.

After starting the simulation process, System Generator starts to process each block in themodel and generate a simulation model according to the specific configurations of each block.When simulation is complete, the results will be shown in the Display as shown in Figure 8.

Figure 8: Simulating the DSP system in System Generator.

This step is performed only once as long as the configurations for each block does not change.Using the values of 3.1 and 4.5 as inputs for both multipliers, the expected output of the systemshould be 29, shown in the Display block. This verifies the functionality of the DSP model generatedby Xilinx System Generator and Simulink.

5 Preparing System Generator for Hardware/Software Co-Sim

In the previous section we verified the functionality of our simple DSP system using Simulinksimulation. Frequently, several issues may arise when the model is transformed into hardware.System Generator provides several methods to transform the models built using Simulink into

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hardware. One of these methods is called Hardware/Software Co-simulation. Hardware/SoftwareCo-simulation enables building a hardware version of the model, and using the flexible simulationenvironment of Simulink we can perform several tests to verify the functionality of the system inhardware. HW/SW Co-simulation supports FPGAs from Xilinx on boards that support JTAG orEthernet connectivity.

5.1 Board requirements for co-simulation

For a specific FPGA board to be used for co-simulation, the following is required:

• A Xilinx FPGA which has enough resources for JTAG/Ethernet communication.

• Support for either JTAG or Ethernet communication.

• A free running clock.

• A Xilinx parallel or USB programming cable for JTAG configuration and communication.

5.2 Generating the co-simulation module

Double-click on the System Generator block. A dialog box will show up as shown in Figure 9which allows you to select the type of hardware generated. If the board was successfully added toMATLAB at the beginning of the tutorial, it will appear in the Board list.

• Under Board, select the Nexys A7-100T D.0. The Part will be selected automatically.

• Under Compilation, select Hardware Co-Simulation → JTAG.

• Click Generate to build the hardware system. The compilation and generation process maytake ten to fifteen minutes to complete.

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Figure 9: Configuring the System Generator block for HW/SW Co-Sim.

When the compilation is complete, a new library is created, containing a single block, as shownin Figure 10. The library name should be sg tut 1 hwcosim lib and the block name should besg tut 1 hwcosim. The block has two inputs and one output as defined by the DSP system. Thisblock includes all functionality required for the system to be executed on the FPGA.

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Figure 10: Configuring the System Generator block for HW/SW Co-Sim.

We are now ready to perform HW/SW Co-Simulation for our DSP system.

6 Hardware/Software Co-Simulation

In this section we will modify the DSP model to use the new co-simulation block and replace thesimulation models used before.

• Make a copy of the “sg tut 1” model generated in Section 3.1 by selecting File → Save asand use the file name sg tut 1 co.

• In the model sg tut1 co replace all the hardware components with the “sg tut 1 hwcosim”block from the “sg tut 1 hwcosim lib” library as shown in Figure 11. Leave the SystemGenerator block in place.

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Figure 11: Configuring the System Generator block for HW/SW Co-Sim.

• Connect the PROG UART port of the Nexys A7 board to your workstation using a microUSB cable and power the board on.

• The design is ready for co-simulation. Click the Run button to start the co-simulation.System Generator will load the bitstream onto the FPGA board.

When the download completes, the green Done LED will light up on the Nexys A7 board.System Generator then reads the inputs from the Simulink environment, sends them to the designon the board using the JTAG connection, reads the output back from JTAG and sends it to Simulinkto be displayed.

We can verify the results by comparing the simulation output to the expected output (i.e. 29).

7 Generating the HDL Code

One of the advantages of Xilinx System Generator is the capability of generating HDL code fromyour designs. Make sure you are using the original model sg tut 1, and not the one usedfor co-simulation. By following the steps below you should be able to generate the VHDL codeand analyze the implemented design using reports generated in Vivado.

• Re-open the sg tut 1 model.

• double-click to open a multiplier block.

• Under the Basic tab, set the latency of the multiplier block to 2.

• Under the Implementation tab, ensure Use behavioral VHDL is selected.

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• Repeat for the other multiplier block.

• Double-click the System Generator block and specify the following settings:

– Board: Nexys A7-100T D.0

– Compilation: HDL Netlist

– Hardware description language: VHDL

– Target directory: ./netlist

– Create testbench: unchecked

– FPGA clock period (ns): 10

• Click Generate to generate the HDL code and Vivado project files.

• Select → Xilinx Design Tools → Vivado 2016.3

• Open the generated project by selecting Open Project and navigating to the generatedfile sg tut 1.xpr. You will find it in your MATLAB current working directory, under thenetlist/hdl netlist subfolder.

• Highlight the top-level file, called sg tut 1.vhd, and select Run Implementation in theFlow Navigator pane.

• Once implementation is complete, you can view the device utilization in the Project Sum-mary tab in the workspace.

8 Summary

In this tutorial we demonstrated the use of Xilinx System Generator to perform the following tasks:

• Build a simple DSP system using basic DSP blocks from the Xilinx System Generator blocksetwithin the Simulink simulation environment.

• Simulate the DSP system using System Generator and Simulink.

• Configure System Generator for co-simulation using the Nexys A7 Artix-7 board.

• Perform hardware/software co-simulation for the proposed DSP system.

• Implemented the designed system in VHDL and examined the post-implementation deviceutilization.

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