twepp - 11 – 26-30 september 2011 – vienna, austria

TWEPP-11 – 26-30 September 2011 – Vienna, Austria

Low Noise Front End ASIC with Current Mode Active

Cooled Termination for the Upgrade of the LHCb

CalorimeterE. Picatoste, C. Abellan, O. Duarte, L. Garrido, D. Gascon, J.

Lefrançois, E. Grauges, F. Machefert, X. Vilasis

Universitat de Barcelona

Institut de Ciències del Cosmos ICC-UB

2

Outline

1. Introduction

2. Channel Architecture

3. First prototype

4. Second prototype

5. Summary

27th September 2011 TWEPP-11

TWEPP-11 3

LHCb Upgrade

• In ~5 years of data taking, most of the proposed physics program will be covered.

• In order to distinguish between models of new physics, a large increase in data rate is required.

• LHCb Collaboration intends to upgrade the detector during the long LHC shutdown in 2016.

OT

VELO

RICH-1

TT

ITMagnet

Muon StationsM2-M5

-5m

5m

y

10m 0m

Calorimeters

RICH-2

M1

27th September 2011

4

Current ECAL/HCAL FE

AD

C

L0

Pipeline

ECAL

HCAL sameelectronics

PM

PM

Analogue 10 mclip

clip

Readout

Trigger

•Pulse shaping in 25 ns•Residue < 1% after 25 ns •Integrator plateau : 4 ns•Linearity < 0.5%•Rise time ~ 5 ns

LAL-OrsayLAL-Orsay

TWEPP-1127th September 2011

5

Motivation

• PM current has to be reduced:– Otherwise PMT would die rapidly (require a factor ~ 5)– FE electronics gain has to be increased correspondingly– FE noise should not be increased in the operation!

• New front end board is required:– Low noise analog electronics– GBT for data transmission @ 40MHz

• For 12 bit DR, input referred noise:– Voltage amplifier: < 1 nV/sqrt(Hz)– Current amplifier: < 10 pA/sqrt(Hz)– Active cooled termination required

• But 2/3 of the signal are lost by clipping:– Alternative solution: remove clipping at the PM base (detector)– Perform clipping after amplification in FE– Alternative discrete elements + delay line solution


6

Channel Architecture

• Current mode amplifier• Switched integrator

– Fully differential Op Amp

• Track and Hold– 12 bit: flip-around architecture

• Analog multiplexer• ADC driver

– To match ADC input impedanceMP2MP1

Q1

Re

Ib1 MN2

MP4MP3

MN1

Rf

Vee

Vcc

1 : K : mK : mK

Ib2

Ii

Io ∫

∫

I I

Current amplifier (mirrors)

TH

TH

AnalogueMultiplexer

Drv

ADC driver

Very difficult to integrate HQ analog

delay lines

2 switched alternated paths as in PS/SPD (LHCb

CALO)

Switching noise!

Fully diferential ASAP


7

Channel Architecture: Current Amplifier Input Stage

• Current mode feedback: – Inner loop: lower input impedance

• Current feedback (gain): mirror: K

– Outer loop: control input impedance

• Current feedback: mirror: m

• Current gain: m• Electronically cooled input

impedance

• Current mode feedback used – Optical comunications– SiPMreadout

• Low voltage– Only 1 Vbe for the super common

base input stage

• Better in terms of ESD:– No input pad connected to any

transistor gate or base

fem

i mRK

K

K

RgZ

11

1 1

MP2MP1

Q1

Re

Ib1 MN1

MP4MP3

MN2

Rf

Vcc

1 : K : K : nK : nK

Ib2

Ii+

MP5

MN3 MN4

m : 1 : n : n

Vref

Io+_Sucbh1 Io+_Sucbh2

Io-_Sucbh1 Io-_Sucbh2

Inner loopOuter loop

2 differential outputs


8

Channel Architecture: Switched Integrator

• Switched integrator– Integrator plateau : 4 ns

– Linearity < 1%

– Residue < 1% after 25 ns

– Reset time < 5 ns

+

-

-

+

In+

In-Out+

Out-

FDOA

CMOS switches

• Rf to improve plateau- 100 ns time constant

- Cancel slow component of the clipped signal (remanent)

-1,2

-1,0

-0,8

-0,6

-0,4

-0,2

0,0

0,2

0 25 50 75 100 125 150 175 200

t (ns)

V n

orm

aliz

ed

Clipped Pulse (Anatoli)

Test Pulse


9

Channel Architecture: Track-And-Hold

• Track-And-Hold:- 12 bit: flip-around architecture

Vin+

Vin-

Vrefth

clkd

clkd

clk

clk_n

clk_n

clkFDOA

-

+

+

-

clk

Vo-

Vo+


10

Channel Architecture: FDOA

• Fully differential Op Amp:- Folded cascode + Miller stage with CMFB

M

M

Vin+

M

Vcas

VrefCE

Vout+

M

M

M

M

Vin-

M

Vcas

VrefCE

Vout-

M

MM

M

Vcmref

M

M

Vb1

Vb2 Vb2Vb2

Vb1

Vb2

Folded cascode

NPN CE amp

Pole compensation

RDegenertion

Common Mode Feedback

FDOA specifications

Parameter Value

Gain bandwidth 500 MHz

Phase margin > 65º

Slew rate > 0.4 V/ns

VCM 1.65 V


11

Choice of Technology

TWEPP-11

SiGe BiCMOS is preferred: SiGe HBTs have higher gm/Ibias than MOS: less noise, less Zi variation SiGe HBTs have higher ft (>50 GHz): easier to design high GBW amplifiers

Several technologies available: IBM IHP AMS BiCMOS 0.35 um

AMS is preferred Factor 2 or 3 cheaper Too deep submicron CMOS not required / not wanted:

Few channels per chip (4 ?) Smaller supply voltage Worst matching

Radiation hardness seems to be high enough 30 Krad seems to be OK (checked by other Upgrade projects)

IBM IHP AMS

HBT ft > 100 GHz 190 GHz 60 GHz

CMOS 0.13 um 0.13 um 0.35 um

Proto Cost [€ /mm2]

> 3 K > 3 K 1 K

27th September 2011

12

First prototype

Switched integrator

Track and Hold

MP2MP1

Q1

Re

Ib1 MN2

MP4MP3

MN1

Rf

Vee

Vcc

1 : K : mK : mK

Ib2

Ii

Io ∫

∫

I I


TH

TH

AnalogueMultiplexer

Drv

ADC driver

ICECAL chip:SiGe BiCMOS 0.35umAMS 2 mm2

Received: October 201012 chips

• Purpose: test key points of a novel circuit idea– Input impedance control by current feedback– Low noise performance– Dynamic range: Linearity

• Also, to test critical aspects of a switched solution:– Offset between subchannels– Noise– Plateau of the integrator output

• Effect of the clock jitter versus signal


13

SCOPE

AWG2021

50 Ohms50

cm

10m

IN OUT

ICECALDiff

eren

tial

Pro

be

Differential Probe

50 Ohms

First Prototype: Input Impedance

IC in

put s

igna

l

(PC

B)Integrator

clock

Waveform Generator

Source signal

sbch

1sb

ch2

Reflection Coefficients for source, IC input, and output signals:

Refl. Coeff. = 1st pulse integral / 2nd pulse integral


14

SCOPE

AWG2021

50 Ohms50

cm

10m

IN OUT

ICECALDiff

eren

tial

Pro

be

Differential Probe

50 Ohms

Input impedance

IC in

put s

igna

l

(PC

B)

Waveform Generator

Source signal

sbch

1sb

ch2

ICECAL OFF

Large reflections

Integrator clock


15

Input impedance

AWG signal

50 470

1uF

1uF

ICECALIN

sbch1

sbch2

INT

INT_BAR

CLOCKPCB

Rp

• PCB input circuit with AC coupling with Rp:– Zin a little higher than 50Ω – Rp used to fine tune Zin– Optimal Rp is between 360 and 390 Ω

• Dynamic variation of input impedance is << 1 % for full dynamic (50 pC)

• Measurement error for second reflection is quite high for low amplitudes (diff probe noise)

• Low Refl. Coef. dispersion < 0.5%

Impedance adaptation

-5

-4

-3

-2

-1

0

1

2

3

4

5

0,0E+00 1,0E-11 2,0E-11 3,0E-11 4,0E-11 5,0E-11 6,0E-11 7,0E-11

PM delivered charge [C]

Area

Coe

ffici

et [%

]

First Reflection

Second reflection

Integrator output

Rp = 390 Ohm

Histogram of input impedance matching for 12 chips

0

2

4

6

8

10

12

14

16

18

-2,5 -2 -1,5 -1 -0,5 0 0,5 1 1,5 2 2,5

Area coefficient [%]

Entr

ies

First

Second

Int Output

-1.75±0.43%

0.82±0.11%

1.99±0.21%


16

First Prototype: Noise

• The noise:– Generate a histogram of the voltage value by the end of the

cycle (from 100 waveforms).

– Gaussian fit => standard deviation

• Correlated Double Sampling (CDS) ↔ dynamic pedestal subtraction:

– LF pick-up noise at measurements (chip connection/socket)

– without CDS: 1.8 ADC counts (LF noise!)

– with CDS: 1.2 ADC counts (≈1 ADC count from simulations)

Integrator output

-6,00E-02

-4,00E-02

-2,00E-02

0,00E+00

2,00E-02

4,00E-02

6,00E-02

8,00E-02

1,00E-01

0,00E+00 2,00E-08 4,00E-08 6,00E-08 8,00E-08 1,00E-07 1,20E-07

Time [s]

[V]

Output fluctuation at different sampling times

0

10

20

30

40

50

60

-10 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10

ADC counts

Entr

ies

Value @ T0

Value @ T0-50 ns

Value @ T0 - 100ns

Output fluctuation sampled with dynamic pedestal subtraction

05

101520253035404550

-10 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10

ADC counts

Entr

ies

CDS 50n

CDS 100n


17

First Prototype: Offset

Offset measurement:V at cycle end

-2ns

V offset measurement

Preamp current offset is integrated

=> Offset at output

Distribution of offset difference between subchannels

0

0,5

1

1,5

2

2,5

3

3,5

-100 -80 -60 -40 -20 0 20 40 60 80 100

Offset difference [mV]

Entr

ies

Diff Subch1-Subch2

ABS (Diff Subch1-Subch2)

5 % of dynamics

• With AC coupling between ICECAL and ADC what really matters is the difference between the offset of the 2 subchannels

• Well below the 5 % of the full scale range (2 V)


18

First Prototype: Linearity

• Relative linearity error < 1% for the full range (2V)

• Error is large for very low amplitude values

• Attenuator + WaveCatcher offer better linearity than the oscilloscope but the differential probe may need calibration

-5

-4

-3

-2

-1

0

1

2

3

4

5

0 0,5 1 1,5 2 2,5Vout (V)

Lini

eari

ty E

rror

(%)


19

Plateau at the integrator output

• Due to clock jitter, the signal at the output must be stable (<1%) for 4 ns.

• Input signal AWG generated similar to clipped.

• Method:– Delay clock signal in 1ns increments– Use LEMO cable

Effect of time alingment (signal versus clock)

-5

-4

-3

-2

-1

0

1

2

3

4

5

-10 -5 0 5 10

Delay variation [ns]

Re

lati

ve

va

ria

tio

n [

%]

150 mV output600 mV output1.2 V output

• The output variation is smaller than 1% for about 3 ns delay variation

– Consistent for different signal amplitudes

• Can be improved using a resistor in parallel to the integrator capacitor (ICECAL2)

+

-

-

+

CF

CF

In+

In-Out+

Out-

RF

RF


20

Second prototype

Switched integrator

Track and Hold

MP2MP1

Q1

Re

Ib1 MN2

MP4MP3

MN1

Rf

Vee

Vcc

1 : K : mK : mK

Ib2

Ii

Io ∫

∫

I I


TH

TH

AnalogueMultiplexer

Drv

ADC driver

ICECAL2 chip:SiGe BiCMOS 0.35umAMS 2 mm2

Submitted: June 6th 2011To be received in September

• Purpose: test key points of the circuit– Input impedance control by current feedback– Low noise performance– Dynamic range: Linearity

• Also, to test critical aspects of a switched solution:– Offset between subchannels– Noise– Plateau of the integrator output

• Effect of the clock jitter versus signal• Integrator Rf effect


21

Second Prototype

Clock input

Input signal

Integrator output

TH output

TWEPP-11

Main signal Tail

Main signal

Tail

27th September 2011

22

Second Prototype Simulations

TWEPP-11

• Input impedance is the same as the 1st prototype

• Linearity:– After TH linearity < 1% for output

amplitudes < 1.8V– The linearity is limited by the

output stage NMOS of the FDOA• Apply offset to the

differential signal so the output voltage is reduced

• The noise:– Generate a histogram of the

voltage value by the end of the cycle (from 100 waveforms).

– Zero input signal– Gaussian fit => standard deviation– Noise 0.8 ADC counts≲

27th September 2011

23

• An integrated circuit for the Upgrade of the LHCb Calorimeter Front End electronics has been presented. Architecture based on:

Current mode preamplifier with cooled termination for reduced input noise 2 fully differential interleaved channels Switched integrator Track-and-Hold

• Measurements of the first prototype of the input stage (preamp+integrator) are about finished Principle is ok Good results with 12 chips statistics Need to study the effect of bias (op. paint) variation

• A second prototype was submitted in June It includes: preamp + integrator + track-and-hold Added a feedback resistor to improve the integrator output stability

Summary


24

Back-up:


25

Test set-up

Waveform Generator signal vs. Measured clipped signal (Anatoli)

-1,2

-1,0

-0,8

-0,6

-0,4

-0,2

0,0

0,2

0 25 50 75 100 125 150 175 200

t (ns)

V n

orm

aliz

ed


Test Pulse -1,2

-1,0

-0,8

-0,6

-0,4

-0,2

0,0

0,2

0 25 50 75 100 125 150 175 200

t (ns)

V n

orm

aliz

ed


Test Pulse

Fast pulse (no tail) to measure reflections


26

SCOPE

AWG2021 50 Ohms

50

cm

10m

IN OUT

ICECALDiff

ere

ntia

l P

robe

Differential Probe

50 Ohms

Test set-up

Tektronix AWG2021 Waveform Generator:

•250 MS/s•12 bit

50Ω || 50Ω = 25Ω emulate clipping impedance

Tektronix TDS7154B Oscilloscope:

•BW = 1.7 GHz•20 GS/s•8 bit

Differential probe:•BW = 400 MHz•Cin = 1 pF


27

Test set-up: linearity

AWG2021

50cm

10m

IN OUT

ICECALProbe Probe

50 Ohms

ATTENUATOR

Signal

CLK

Trigger

WaveCatcherCH0

CH1

PC

Attenuator: Better linearity

than AWG (<1%) No need for

timing corrections

WaveCatcher: Better linearity

than oscilloscope

PC: Automatized

systemTWEPP-1127th September 2011

28

Test set-up


twepp - 11 – 26-30 september 2011 – vienna, austria

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