two-port parameterswebpages.eng.wayne.edu/cadence/ece6570/doc/lect4_1.pdf · two-port parameters he...
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TWO-PORT PARAMETERS
he two-port current equations are given by:
s Y-parameter matrix is
oltage Gain
The constraint due to load is:
(1)--- VyVyI +=
+
Zi Zo
Zs
ZL[Y]
I1 I2
+V1
-
+
-
V2Vs
IL
T
(2)--- VyVyI 2221212
2121111
+=
It
2221 yy =Y 1211 yy
V
1V V
A =
IZV L2 −=
2V
(3)--- VYIor 2L22 −= Substitute (3) to (2)
1
(4)--- Yy
yVVA
)VY(yVy0
L22
21
1
2V
2L22121
2221212L
+−==
++=
urrent Gain
urrent Gain
CC
Substitute (3) to (1) and (2), Substitute (3) to (1) and (2),
11
VyVyVY +=−
(5)--- IZy- 2L121
2LI II ;II
−=2L IIA −==
I Vy111 =
From (5) solve for V1
From (5) solve for V1
(6)--- IZy-VyI 2L221212 =
Substitute (7) to (6) Substitute (7) to (6) 11
yIZyIyI
11
2L121212 −
+=
Input Impedance
Input Impedance
(8)--- YydetY
YyydetYZ
yII-A
L11
L21
11L
21
1
2I
1212L11
+−=
+−==
1VZ =
Substitute (3) to (2)Substitute (3) to (2)
(7)--- IZyI 2L121 +=y1V
IyI)YZdety(IYZdetIyIZyy-IZ
IZy
2L1212L22112L1
2L22
=+−=yyIyIy 212121211 +=
i1I
2
3
Summarizing the network functions in term of Y-parameter.
Substitute (9) to (1)
ubstitute (11) and (12) to (2)
Output Impedance
1
IVZ
0V2
2o
S
==
Substitute (11) to (1)
(12)--- VYy
VyIYy-I
2S12
2121S
111
=
+=
S
(9)--- YyVy-V
VyVyVYI
L22
121
2221212L2
+=
+=−=
2
YyV
yyYyVyy-VyI
L221
11
L22
121121111
+
=
+=
(10)--- Y
VYy
YydetYVYy
Yyyy-
Li
1L22
L111
L22
L11211222
==
++
=
+
+
ZydetYI 111 +
(11)--- IY
-IZ 1S
1S1 =−=V
IYy S11
1 +
y)Y(yY
VYyy-
VyIYy-I
22S11S
2S1221
2221S
212
++
=
+=
(13)--- YydetY
YyIV
VYy
YydetYV
YyYyyyyy-
V
S112o
2S11
S222
S11
S22221112212
++
==
++
=+
++=
ZS222
Filename=”cursrc2.doc”
Simple Current Sink
L22
21
1
2V
L11
L21
1
2I
Yyy
VVA
YydetYI-A
+−==
+−==
Figure 1(a) shows a single NMOS transistor as a simple current sink. It is implemented
y biasing the transistor at saturation. The current equation at saturation region is given by:
fer characteristic represents the ac output conductance of the simple current sink. he conductance depends on the parameter λ and its value is derived as follows:
DS finite inimum output voltage is zero.
os entation actually capture both positive and negative output voltage swing, but
nly the positive swing is normally shown. The reason can be explained uisng Figure (d) and (e). An nmos device is a symmetrical device the source (S) and drain (D) are
b
2n WK
The parameter λ is the spice parameter LAMBDA, which typically is a small number. From the Spice parameters file, LAMBDA=.02 (NMOS); .02 (PMOS). The slope of the ranst
T
D2
TnGSnnD
ds I)V-V(LW
2K
VIg λλ ≈
=
∂∂
=
The minimum output voltage of the simple current sink occurs when VDS=VGSn-VTn=∆V.The characteristic of the simple current sink is shown in Figure 1(b). The ideal current sink shown in Figure 1(c) has a horizontal transfer characteristic, indicating that the current is constant for any output voltage V . That is, an ideal current sink has inoutput impedance (or zero output conductance), and the mIn addition, the output voltage swing both positive and negative. The nmimplemo1physically indistinguishable. The designation is not known until the output voltage VDS is applied. The positive side is always the drain(D) side of the nmos transistor.
S222o YydetYI +
S112
L11
L22
1
1
YyI
YyVYydetY
YyIV
+==
++
==iZ
Z
DSTnGSn2
TnGSnn
DSTnGSnD VV-V ; )V-V(LW
2K
)V1()V-V(L2
≤
≈+
= λI
DS
4
-GS
(a)
∆V
ID
VDS(b)
ID
VDS(c)VSD
+ 1(G)
2(D)
3(S)
4(B)1(G)
2(S)
3(D)
4(B)
+
(d) (e)
+
ID
+
VDSV
5
Figure 1. Simple Current Sink.
Cascode Current Sink
To achieve a more ideal current sink, one needs to increase the output impedance. This can be achieve by adding a cascode (common gate) stage at the output of the simple current sink. The cascode is an impedance converter. It magnify the output impedance of the simple current sink by the gain of the cascode stage. This will be derived shortly. The cascode current sink is shown in Figure 2. Two reference voltages (VG1 and VG2) are required to establish the operating point of the common source and cascode stage respectively. To determine the ac output impedance, one needs to perturb the input signal by adding (super-imposing) vgs1 to VG1, this is shown in Figure 2. The small signal equivalent circuit shown in Figure 3 is used to determine the output impedance of the cascode current sink. Figure 3(a) is transformed to Figure 3(b) using the following ac voltage signal equivalent derived from Figure 2:
two-port an ieve this. The current equation of network
is obtained as
Figure 2. Cascode current sink.
+
VG2
VG1
+
-
Vo
rovgs1
vgs2vbs2
D2G2
S2
M2
M1
B2
G1D1
S1
B1
vgs1
ds1bs2
ds1gs2
vv
vv
−=
−=
A alysis method will be used to achfollows:
6
a1 0I =
I a2ds1
a1m1
a2 VgVg +=
The corresponding Y-param
00Ya
=
eter matrix is :
The corresponding Y-parameter matrix is:
hat is, the output impedance is equal to the output impedance of the simple current sink
bbb Vg)Vggg(I +++−=
0detY
gga
ds1m1
=
The current equation of network b is:
b2ds2
b1ds2mb2m2
b1 Vg-)Vggg(I ++=
2ds21ds2mb2m22
g)ggg(g-)ggg(
Y
b
ds2ds2mb2m2
ds2ds2mb2m2b
++−++
=
0detY =
To calculate the output impedance, one needs to first calculate the output impedance of network a. That is,
The output impedance is computed as follows:
0or Z Y since ;g1
y1
YydetYYy
Z aS
aS
ds1a22
aS
a22
a
aS
a11a
o =∞===++
=
ds2mb2m2bbb
bS
b11b
oog)ggg(Yy
Zr+++
=+
==
ds1ds2m2ds2mb2m2ds1ds2ds2ds2mb2ds1ds2
ds1ao
bS
ds1ds2
ds1
S22
)rr(g1])ggg([rrr)ggg(rr
gYY since ;ggYydetY
≈+++=+++=
==+
m2
Tmagnified by the gain of the common gate stage.
7
NOTE: vgs2=-vds1; vbs2=-vds1
Figure 3. Cascode current sink small signal equivalent circuit.
S1
gm1vgs1
+
vi=vgs1
-
gds1
+
vds1
-
D2S2
G2
gds2
gm2vgs2
gmb2vbs2 +
-
vo
D1
S1
G1
gm1vgs1
+
ivgs1
-
+
vds1
-
D2S2
G2
gds2
gm2vds1
gmb2vds1 +
-
vo
Ya Yb
(a)
I1a
+
V1a
+V2a =V1b
+
I2a I1b I2b
+V2b
-
Ya Yb
(c)
D1G1
v =gds1
(b)
- - -
8
Single Voltage Reference
+
-
VR1
M1
I
+
-
VR1
M1
+
-
VR1
M1
M2
R
(a)
(b) (c)
Figure 4. Single voltage reference circuit. The voltage reference is achieved by passing a current through a resistor, implemented by a diode connected transistor, shown in Figure 4 (a). There are two ways of implementing the current source. In Figure 4(b), a current source is implemented by a pmos transistor with a constant gate to source voltage. The gate is connected to the constant voltage reference, VR1, and the source is connected to the constant positive power supply VDD. The pmos and nmos are connected in series in Figure 4(b). That is,
9
The design parameter is given by:
This determine the transconductance ratio for a given reference voltage. The power dissipation of this circuit is:
In Figure 4( c ), the current source is implemented by resitor R with constant voltage applied across it. That is,
The reference voltage is given by:
g the single voltage reference and simple current
nk. PSpice simulation will be shown in the last section.
2TnR1
n2TpR1DD
p
2TnR1
1
n2TpR1DD
2
p
np
)VV(2
)VV-V(2
)VV(LW
2K)VV-V(
LW
2K
II
−=−
−
=−
=
ββ
Solving for VR1,
pβn
TpDDTnp
n
R1
1
)V-V(V
Vβ
ββ
+
+
=
R1DDnV-V −
=β
2
TnR1
Tp
p V-V
V
β
DD2
TnR1n
DDD V)V-V(2
VIP
==β
2TnR1
nR1DD )V-V(2R
V-VI β==
TnV+βn
R1I2V =
Figure 5 shows the circuit combininsi
10
Figure 5. Single voltage reference circuit and current sink.
+
-
VR1M2
M3
M1(21.6U/1.2U)
(100.8U/3.6U)
(3.6U/3.6U)
(2)
(3)
(1)
(4)
=1.3V
I=200uA
11
Multiple-Voltage Reference Circuit
nce circuit. Multiple-voltage reference is achieved by cascading a number of resistors equal to the number desired of voltage references. The resistor is implemented by diode connected
mos transistor. The dual -voltage reference is shown in Figure 6(a). The current source implemented by resistor R in Figure 6(b) with constant voltage applied across it. The
,
olving for VR1,
Figure 6. Dual voltage refere
(a)
+
-
VR2
M2
I
M1
+
-
VR1
+
-
VR2
M2
+
-
VR1
M1
R
(b)
nisresistor and the two nmos transistors are connected in series, hence the currents in the elements are equal. That is
S
2Tn1R1
n12Tn2R1R2
n2R2DD )V-V(2
)V-V-V(2R
V-VI
ββ===
Tn1n1
R1 VI2V +=β
12
Solving for VR2-VR1,
n2β Tn2R1R2 VI2-V +=V
Substituting VR1, and solving for V
R2
Where:
γ = GAMMA =1.0V φ=PHI =0.6V λ=LAMBDA =0.02 1/V
ias increases the threshold voltage. That is, VTn2>VTn1.
Biasing Cascode Current Sink
Tn2Tn1n1n2
R2 VVI2I2V +++=ββ
)V(VV BSTonTni φφγ −−+=
The corresponding nmos SPICE parameters are: VTon= VTO =1.0V
1/2
Note the bulk to source b
BSTonTn2 V(VV −+= φγ R1BSR1R1
BS1TonTn1
VV ;V6.06.00.1)6.0V6.0(0.10.1)
0V ;1VV
−=++−=−++=−
===
φ
inimum VDS for which the
transistors M1 and M2 are in series or have the same current then:
The principle used in biasing MOS transistor. The mevice remain in saturation is: d
V
( )2D
TGSDSmin
VLW
2K
VV-V
∆
=
∆==
I
If
( ) ( )22
2
221
1
1
D2D1
VLW
2KV
LW
2K
II
∆
=∆
=
13
If M1 and M2 are of the same type either both are nmos or pmos. Then the expression reduces to:
( ) ( )22
2
21
1
VLWV
LW
∆
=∆
( ) ( )
2
21
22
2
22
1
21
n/LW
LW
then
VLWVn
LW
VnV If
=
∆
=∆
∆=∆
/L) can be used to control the values of ∆V. If the transistors are in parallel
ype (K1=K2), the expression reduces to:
re ansistor have the same (W/L) and are of the same type
means (∆V)i=∆V. That is, the gate to source VGS of each transistor must be VT+∆V to be in saturation. This is shown in Figure 7(a). M3 and M4 operate as voltage divider, each transistor is diode connected. The voltage at the gate of M4 ,VG4, is the sum of VGS (or
DS) of transistor M3 and M4. That is,
tput voltage is determined as follows:
That is, (Wor ∆V1=∆V2 , then:
22
D2
11
D1
21
(W/L)KI2
(W/L)KI2
VV
=
∆=∆
22
D2
11
D1
(W/L)KI
(W/L)I
=K
If transistor M1 and M2 are of the same t
Applying the above biasing principle to the cascode current sink shown in Figure 7. All the transistors are assumed to be operating in saturation, have the same (W/L) and all aof the nmos type. Since all tr
1D2
2D1 L
WIL
I
=
W
V
V2V2V)V(V)V(VV TTTG2G4 ∆+=∆++∆+==
The minimum ou
14
V2V(min)VV(min)V
VVV)](V-V2V2(min)V(min)V(min)V
Tout
DS2
TTT2
DS2DS1out
∆+=∆=
∆+=∆+∆+=+=
V-V(min)V GSG2DS1 =
he transfer characteristic is illustrated in Figure 7(b). The value of VT is typically about V, while ∆V is typically about 0.2 to 0.3 V, the sum is about 1.4 to 1.6. This value will
e f the output voltage, specially in low voltage application.
T1significantly limit the dynamic rang o
15
∆V
VT+∆V VT+∆V
T
+
−
+
−
VT+∆V
+
−
Iin Iout
M1
M2
M3
M4
Vout
Iout
VT+2∆V
(a)
(b)
VDD(3)(2)
(5)
(1)
VSS (4)
(6)
2VT+2∆V
VT+∆V V +∆V Vout=VT+2∆V
16
Figure 7. Cascode current sink bias requirement.
Simple Current Mirror
Sink
I
(a)
M1
I
M2
(W/L) (W/L)
D2
S2
D1
S1
m2
S1S2
gds1gm1vgs1
=vgs1=V1
V2
(b)
G2 G1
g
D1D2=G2=G1
vgs2++
V1
+
I1 I2
Figure 8. Simple current mirror and its small signal equivalent circuit. The purpose of current mirror is to generate another current sources or sinks from a stabilized current source or sink. Figure 8 shows how to create a current sink from a known current source I. The diode connected transistor M2 is connected to the current source. The gate and source of both transistor are connected to each other; hence, VGS1=VGS2=VGS. The current ratio is given by:
17
n(W/L)(W/L) ; nII(W/L)(W/L) ; II
(W/L)(W/L) , II I;(W/L)(W/L)I
(W/L)(W/L)
II
)V-(VK(W/L))V-(VK(W/L)
II
11
11
221
1
2
1
2
1
2TGS2
2TGS1
2
1
====
===
=
=
Figure 9 (a) shows current msingle current source. Figure 9 (b) shows current m
irrors generating current sinks of different values from a
a
pedance of the mirrored source or sink. Figure 8(b) shows the small signal equivalent circuit. The output impedance is computed using the two-port analysis. The current equations are computed:
The corresponding Y-parameter matrix is:
The output impedance is calculated as follows:
That is, the mirrored current sink impedance is rds1 only.
irrors generating current sources of different values fromsingle current sink. These generated current sinks or sources are usually used as load of the various circuits. It is of interest to know what is the im
2ds11m12
1m21
VgVgIVgI
+==
ds1m2
ds1m1
m2
ggdetYgg0g
Y
=
=
0or Z Y since ; rg1
YydetYYy
rZ SSds1ds1S22
S11oo =∞===
++
==
18
Figure 9. Using simple current mirror to generate multiple current sinks and current sources.
Source
(b)
(W/L) (W/L) n(W/L)
I I nI
Sink Sink
Source
(W/L) (W/L) n(W/L)
(a)
I I nI
19
20
Cascode Current Mirror
igure 10. Cascode current mirror.
Sink
I
(a)
(b)
M1M3
D3G3
S3
G1D1
S1
VG
D4
S4
G4B4 G2
D2
B2
S2M2M4
II
I
M1M2
(W/L) (W/L)
D2G2
S2
G1D1
S1
(W/L) (W/L)
F
Although the current source is ideal with ∞ impedance, the mirrored impedance
rds only. Since the mirrored current sink or source are used as load of gain stages, it is esired that the impedance be as high as possible. Figure 10 shows the corresponding ascode current mirror by adding cascode (common gate) stage at the diode connected age and the mirror stage. As in the earlier analysis, the output impedance is magnified y the gain of the cascode stage. That is,
ransistor M3 and M4 is the two-transistor version of diode connected transistor. In the ascode current mirror, the voltage at gate of M2 or M4 must be biased properly to
produce minimum output voltage. Figure 11 shows the biasing requirement to achieved a wide-swing cascode current mirror. That is, to achieve minimum output voltage, VDS1(min)=∆ V. This can be achieved, if the gate voltage of M2 is VT+(n+1)∆V. This voltage is also the gate to source voltage of transistor M5. It is generated by controlling the (W/L) of M5, (W/L)5=(W/L)/(n+1)2 , see Figure 11(a). To guarantee that the transistor M4 is in saturation, one must guarantee that VDS4>n ∆V; since (W/L)4=(W/L)/n2. The diode connection with M3 also put another constraint on VDS4.
That is, one must guarantee that VT>n ∆V for M4 to be in saturation. For VT=1V and ∆V=.2, then n <5 to guarantee that M4 will operate in saturation. In the special of n=1, the minimum output voltage is 2 ∆V. In the above analysis, the effect of the bulk to source voltage on the threshold voltage of M2 and M4 were ignored. The threshold voltage of both M2 and M4 are significantly higher than that of M1 and M3. In the PSpice simulation, it will be shown that the bulk to source voltage can not be ignored.
V)n(VV TDS4 ∆>=
isdcstb Z ds1ds2m1oo )rrg(r == Tc
That is,
VV)(-V)V(V-VV TTDS3G3DS4 =∆∆+==
21
Figure 11. Generalized wide-swing cascode current mirror.
VT+∆V
VT+n∆V
+
−
+
−
∆V
+
−
Iout
M1
M2
Ib
VT+∆V
VT+(n+1)∆V
VT+n∆V
M3
M4
Vout=(n+1)∆V
Iin
Vout
Iout
(b)(n+1)∆V
(a)
(W/L)/n2 (W/L)/n2
(W/L)(W/L)
(W/L)/(n+1)2
M5n∆V
VT+(n+1)∆V
=Iin
VDD(3)
VDD(3)
(5)
(1)
(2)
VSS (4)
(6)(7)
22
Experiments on Current Sink/Source and Voltage Reference
A design of 200 uA current sink will be illustrated in the following. To prevent going to weak inversion region, VGS - VT >0.2 V. For VT = 1, this can be satisfied by selecting
GS = 1.3.
V
Simple Current Sink A current sink or source can be obtained by operating the MOS transistor in the saturation mode with fixed gate to source bias, VGS. Current sink is implemented using NMOS transistor as shown in Figure 5.
V
I VD N GS T= −( / )( )β 2 2 where: βN NK W / L)= ( Solve for W/L,
WL
IK V V
IK V V V
D
N GS T
D
N G SS T
=−
=− −
2 22 2( ) ( )
Substituting the given design parameters,
1.1111)-0-6)(1.3-(40E
6)-E200(2LW
2 ==
Let L=1.2u (the minimum feature length), its effective length is Leff = L -2LD=1.2u- 2(0.5u)=0.2u. The W is calculated from W=111.1*Leff = 111.1*(0.2u) = 22.22u, rounded to say 21.6u (or 36 λ).
In the design of 200uA current sink, to establish the gate to source voltage of VGS 1.3 requires a gate voltage of VG =1.3 to be generated from the available supply oltages. Figure 5 shows a voltage divider circuit, it consists of two diode connected
here:
=vtransistors, acting as two resistors connected in series. Each transistor is design to operates in the saturation mode. Its current equation must satisfy: I IP N= w I V VP P GSP TP= −( / )(| | | | )β 2 2 , and βP P P PK W / L )= ( I V VN N GSN TN= −( / )( )β 2 2 , and βN N N NK W / L )= ( Equating and solving for W/L ratio:
W LW L
K V VK V V
N N
P P
P GSP TP
N GSN TN
//
(| | | | )( )
=−−
2
2
When laying out the voltage divider, the lengths of both transistors are usually made qual , LP=LN. Thus the equation simplify to width ratio. e
WW
K V VK V V
K V V VK V V V
N
P
P GSP TP
N GSN TN
P G DD TP
N G SS TN
=−−
=− −− −
(| | | | )( )
(| | | | )( )
2
2
2
2
Substituting for the given parameters:
23
375.301)-0-6)(1.3-E40(
|)-1|-|0-1.36)(|-E15(WW
2
2
P
N ==
The minimum gate length (L) is 2λ, while the minimum gate width (W) is 6λ The omputed W/L ratio of the voltage divider is rounded to 30. Let WP=6λ,
WN=30*WP=180λ. Some fine tuning was found necessary to achieved the desired voltage of 1.3v , the resulting WN=168λ=100.8u. The output resistance is computed as follows:
This is within 3% of the value obtained from PSpice simulation, 2.572x105. *Pspice file for 200uA Current Source * Filename=”c200fg4.cir” VDD 3 0 DC 5VOLT VSS 4 0 DC 0VOLT VO 2 4 DC 1.5VOLT M1 2 1 4 4 MN W=21.6U L=1.2U M2 1 1 4 4 MN W=100.8U L=3.6U M3 1 1 3 3 MP W=3.6U L=3.6U .MODEL MN NMOS VTO=1.0 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL MP PMOS VTO=-1.0 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .DC VO 0 5.0 0.05 .TF V(2) VO .PROBE .END
c
5
DQdso or2.5x10 M25.0
)6E200)(02(.1
I1rr =
−===
λ
24
ODE VOLTAGE: ( 1) 1.3000 ( 2) 1.5000 ( 3) 5.0000 ( 4) 0.0000
Casc
N
OUTPUT RESISTANCE AT VO = 2.572E+05
ode Current Sink
d rom Figure 7, the
urce of M2 is connected at a potential of VT0+∆V=1+0.3=1.3, and the bulk at VSS=0. hat is, VBS=-1.3. The threshold voltage is calculated as follows:
:
The biasing formula derive earlier assume that the effect of the bulk to source voltage can be ignored. This is the not case in the cascode current sink, the thresholvoltage of M2 and M4 are significantly higher than M1 and M3. FsoT
6.16.0)3.1(61)V(V BSTOT −−−=−−+= φφγ ).0(1V =+ T
he gate voltage of M2 need to be modified from
:toV2V2V TG2 ∆+=
3.22(0.3)11.6V2VV TOTG2 =++=∆++=V
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The calculated value is within .09% of the actual value obtained from PSpice simulation, which is the voltage at node 5 of 3.203V. The minimum output voltage of M1 is given
y:
The PSpice transfer characteristic shows that the output current stabilized at 200uA when the output voltage is about 1.6V
1.195x10 which is 6% of the calculated pedance of the simple current sink
8. This value is now within 0.83% of
Pspice file for 200uA Current Source Filename="c200fg7.cir" VDD 3 0 DC 5VOLT VSS 4 0 DC 0VOLT VO 2 4 DC 2.5VOLT I 3 5 DC 200UA M1 6 1 4 4 MN W=21.6U L=1.2U M2 2 5 6 4 MN W=21.6U L=1.2U M3 1 1 4 4 MN W=21.6U L=1.2U M4 5 5 1 4 MN W=21.6U L=1.2U
b V This voltage correspond to node 6 in the PSpice simulation of 1.2989V, which is within 0.08% of the calculated value. The minimum output voltage is given by:
TOTDS1 1.30.31VVVV(min) =+=∆+=∆+=
1.62(0.3)1V2VV2V(min)V TOTout =+=∆+=∆+=
The output impedance can be calculated as follows:
g
ds
3-
-3
g
6-4E6)-E200)(02(.
mho0.4768x103)-E3145.1()3.1(6.02
1
mho x103145.16)-1))(200E-.26)(21.6/(1-E40(2K(W/L)I2
==
=−−
=
=== DQm2
m2mb2 gg =γ
BSV2 −φ
DQdsds1ds2 Iggg === λ
or
dsds1ds2 6E25.01rrr +====
ds2mb2m2ds1ds2O 1])gg(g[rrr +++=81.122x101]6)-4E =+3-.4768E3-6)(1.3145E6)[(.25E(.25E ++++=
8The PSpice simulation output impedance is
value. If one substitutes the Pspice output imro=rds=.2572x106, the calculated results is 1.185x10the PSpice result. **
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.MODEL MN NMOS VTO=1.0 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .MODEL MP PMOS VTO=-1.0 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .DC VO 0 5.0 0.05 .TF V(2) VO .PROBE .END NODE VOLTAGE: ( 1) 1.3004 ( 2) 2.5000 ( 3) 5.0000 ( 4) 0.0000 ( 5) 3.2030 ( 6) 1.2989 ARACTERISTICS **** SMALL-SIGNAL CH V(2)/VO = 1.000E+00 08 OUTPUT RESISTANCE AT VO = 1.195E+
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Wide-Swing Cascode Current Mirror The analysis in Figure 11 assumed that the effect of the bulk to source is
egligible. That is, all the transistor have the same voltage of VTO. The threshold voltage f M2/M4 will be calculated, based on the knowledge that the source of M2 is at a
age of VG2, because y generate
VTO+2∆V=1.6, which is less than 1.774. That is, the required W/L of M5 to generate 1.774 is computed using the simple voltage reference formula with constant bias current IB=200uA.
16.69(1.2-1)=3.338u. This is less than the minimum
16.69(2.4-1)=23.37u. That is, the ratio
t node 5 is 1.7607 rather 1.774. lated using voltage source to supply the
or
le for 200uA Current Source Filename="c200fg11.cir" DD 3 0 DC 5VOLT SS 4 0 DC 0VOLT
1.6U L=1.2U .6U L=1.2U
=21.6U L=1.2U
nopotential of ∆V, when M1 is at saturation, and the bulk is at VSS=0.That is, VBS2=VBS4=-∆V=0.3. The threshold is given by:
The calculated threshold voltage is 17% more than V . Its effect can not be ignored. In act transistor M5 can no longer b
T2G2 1.7742(0.6)1.174V2V174.1)6.0)3.0(6.0(11)V(VV BST0T2
=+=∆+=
=−−−+=−−+= φφγV
TOe used to generate the required volt
e thre can onlfth shold voltage of M5 is VTO. Its gate to source voltage
69.161)-6)(1.774-E40(
6)-E200(2)V-K(V
2IW/L
VK(W/L)
I2VI2V
22TOR1
TOTOR1
===
+=+=β
Selecting L=1.2u , results in W=width of 6λ=6(0.6)=3.6u. Let L=2.4u, then W=(W/L)1/(W/L)5= (21.6/(1.2-1))/16.69=6.47 rather than 4 (for n=1) as shown in the nalysis in Figure 11. The realized voltage using M5 ahe wide-swing cascode current mirror is simu
aTrequired gate voltage of 1.774 and using M5 to generate it with (W/L)/6.47 rather than(W/L)/4 used in the ideal analysis. The transfer characteristic is practically the same fboth simulations. Pspice fi**VVVO 2 4 DC 1.5VOLT VG2 5 0 DC 1.774VOLTI IR 3 1 DC 200UA M1 6 1 4 4 MN W=2M2 2 5 6 6 MN W=21M3 7 1 4 4 MN WM4 1 5 7 4 MN W=21.6U L=1.2U
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.MODEL MN NMOS VTO=1.0 KP=40U + GAMMA=1.0 LAMBDA=0.02 PHI=0.6
TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
ed using a voltage source.
VOLTAGE:
7) .2991
+ + .MODEL MP PMOS VTO=-1.0 KP=15U + GAMMA=0.6 LAMBDA=0.02 PHI=0.6 + TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10 + U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9 .DC VO 0 5.0 0.05 .TF V(2) VO .PROBE .END Node 5 is generat NODE ( 1) 1.3034 ( 2) 1.5000 ( 3) 5.0000 ( 4) 0.0000 ( 5) 1.7740 ( 6) .4722 ( **** SMALL-SIGNAL CHARACTERISTICS AT VO = 8.554E+07 OUTPUT RESISTANCE
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Node 5 is generated by transistor M5. NODE VOLTAGE: ( 1) 1.3037 ( 2) 1.5000 ( 3) 5.0000 ( 4) 0.0000 ( 5) 1.7607 ( 6) .4587 ( 7) .2904
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